diff --git a/Platforms/FVP/ARMv81MML/LinkScripts/GCC/lnk.ld b/Platforms/FVP/ARMv81MML/LinkScripts/GCC/lnk.ld
index 08ce5cac..9aee29b7 100755
--- a/Platforms/FVP/ARMv81MML/LinkScripts/GCC/lnk.ld
+++ b/Platforms/FVP/ARMv81MML/LinkScripts/GCC/lnk.ld
@@ -1,11 +1,11 @@
/******************************************************************************
* @file gcc_arm.ld
* @brief GNU Linker Script for Cortex-M based device
- * @version V2.0.0
- * @date 21. May 2019
+ * @version V1.1.0
+ * @date 04. August 2020
******************************************************************************/
/*
- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -21,18 +21,86 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-#include "mem_ARMv81MML.h"
-__STACK_SIZE = 0x2000;
-__HEAP_SIZE = 0x50000;
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/* memory regions are:
+ secure ROM: 0x10000000
+ non-secure ROM: 0x00000000
+
+ secure RAM: 0x30000000
+ non-secure RAM: 0x20000000
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+ Flash Configuration
+ Flash Base Address <0x0-0xFFFFFFFF:8>
+ Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x00000000;
+__ROM_SIZE = 0x00110000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+ RAM Configuration
+ RAM Base Address <0x0-0xFFFFFFFF:8>
+ RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00100000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+ Stack / Heap Configuration
+ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00002000;
+__HEAP_SIZE = 0x00050000;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
MEMORY
{
- ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 512K
- DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
- DTCM2 (xrw) : ORIGIN = 0x20020000, LENGTH = 384K
+ FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
ENTRY(Reset_Handler)
SECTIONS
@@ -62,7 +130,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
- } > ITCM
+ } > FLASH
/*
* SG veneers:
@@ -79,30 +147,32 @@ SECTIONS
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
- } > ITCM
+ } > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > ITCM
+ } > FLASH
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
+
LONG (__etext)
LONG (__data_start__)
- LONG (__data_end__ - __data_start__)
+ LONG ((__data_end__ - __data_start__) / 4)
+
/* Add each additional data section here */
/*
LONG (__etext2)
LONG (__data2_start__)
- LONG (__data2_end__ - __data2_start__)
+ LONG ((__data2_end__ - __data2_start__) / 4)
*/
__copy_table_end__ = .;
- } > ITCM
+ } > FLASH
.zero.table :
{
@@ -111,18 +181,19 @@ SECTIONS
/* Add each additional bss section here */
/*
LONG (__bss2_start__)
- LONG (__bss2_end__ - __bss2_start__)
+ LONG ((__bss2_end__ - __bss2_start__) / 4)
*/
__zero_table_end__ = .;
- } > DTCM
+ } > FLASH
/**
* Location counter can end up 2byte aligned with narrow Thumb code but
* __etext is assumed by startup code to be the LMA of a section in RAM
- * which must be 4byte aligned
+ * which must be 4byte aligned
*/
-
- .data :
+ __etext = ALIGN (4);
+
+ .data : AT (__etext)
{
__data_start__ = .;
*(vtable)
@@ -142,7 +213,6 @@ SECTIONS
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
-
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
@@ -155,9 +225,7 @@ SECTIONS
/* All data end */
__data_end__ = .;
- } > ITCM AT > DTCM
-
- __etext = ADDR(.data);
+ } > RAM
/*
* Secondary data section, optional
@@ -190,7 +258,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
- } > DTCM2
+ } > RAM AT > RAM
/*
* Secondary bss section, optional
@@ -219,21 +287,19 @@ SECTIONS
. = . + __HEAP_SIZE;
. = ALIGN(8);
__HeapLimit = .;
- } > DTCM2
+ } > RAM
+ PROVIDE(__HeapBase = __end__);
- .stack (ORIGIN(DTCM2) + LENGTH(DTCM2) - __STACK_SIZE) (COPY) :
+ .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :
{
. = ALIGN(8);
__StackLimit = .;
. = . + __STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
- } > DTCM2
+ } > RAM
PROVIDE(__stack = __StackTop);
- /* Check if data + heap + stack exceeds DTCM2 limit */
- ASSERT(__StackLimit >= __HeapLimit, "region DTCM2 overflowed with stack")
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
-
-
-
diff --git a/Platforms/FVP/ARMv81MML/Startup/GCC/startup_ARMv81MML.c b/Platforms/FVP/ARMv81MML/Startup/GCC/startup_ARMv81MML.c
index 06cbb5e3..4e5bf5b9 100755
--- a/Platforms/FVP/ARMv81MML/Startup/GCC/startup_ARMv81MML.c
+++ b/Platforms/FVP/ARMv81MML/Startup/GCC/startup_ARMv81MML.c
@@ -22,7 +22,6 @@
* limitations under the License.
*/
-
#if defined (ARMv81MML_DSP_DP_MVE_FP)
#include "ARMv81MML_DSP_DP_MVE_FP.h"
#else
@@ -125,10 +124,7 @@ extern const pFunc __VECTOR_TABLE[240];
#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS)
-
-
-
-
+ extern void _start(void) __NO_RETURN;
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
@@ -140,7 +136,9 @@ __NO_RETURN void Reset_Handler(void)
SystemInit(); /* CMSIS System Initialization */
- __PROGRAM_START();
+ __PROGRAM_START();
+
+ //_start();
}
@@ -150,6 +148,9 @@ __NO_RETURN void Reset_Handler(void)
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
+ SERIAL_DATA = 'H';
+ SERIAL_DATA = '\n';
+
while(1);
}
@@ -158,6 +159,8 @@ void HardFault_Handler(void)
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
+ SERIAL_DATA = 'D';
+ SERIAL_DATA = '\n';
while(1);
}
diff --git a/Platforms/FVP/ARMv81MML/Startup/GCC/support.c b/Platforms/FVP/ARMv81MML/Startup/GCC/support.c
index 740f6b08..e284cd95 100755
--- a/Platforms/FVP/ARMv81MML/Startup/GCC/support.c
+++ b/Platforms/FVP/ARMv81MML/Startup/GCC/support.c
@@ -15,7 +15,7 @@ char __HeapBase, __HeapLimit; // make sure to define these symbols in linker co
#endif
static int totalBytesProvidedBySBRK = 0;
-
+/*
//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file).
char * sbrk(int incr) {
static char *currentHeapEnd = &__HeapBase;
@@ -31,6 +31,6 @@ char * sbrk(int incr) {
}
//! Synonym for sbrk.
char * _sbrk(int incr) { return sbrk(incr); };
-
+*/
void __malloc_lock() { };
void __malloc_unlock() { };
\ No newline at end of file
diff --git a/Source/CommonTables/arm_const_structs_f16.c b/Source/CommonTables/arm_const_structs_f16.c
index fa4a420c..97db8af5 100755
--- a/Source/CommonTables/arm_const_structs_f16.c
+++ b/Source/CommonTables/arm_const_structs_f16.c
@@ -42,7 +42,7 @@ for compilation.
/* Floating-point structs */
-#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE)
+#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE)
/*
@@ -50,7 +50,7 @@ for compilation.
Those structures cannot be used to initialize the MVE version of the FFT F32 instances.
So they are not compiled when MVE is defined.
-For the MVE version, the new arm_cfft_init_f32 must be used.
+For the MVE version, the new arm_cfft_init_f16 must be used.
*/
diff --git a/Source/fft.cmake b/Source/fft.cmake
index c1f9d8ca..57190307 100644
--- a/Source/fft.cmake
+++ b/Source/fft.cmake
@@ -7,7 +7,7 @@ function(fft PROJECT)
if (CONFIGTABLE AND CFFT_F32_16)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_16)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_16)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_16)
@@ -16,7 +16,7 @@ endif()
if (CONFIGTABLE AND CFFT_F32_32)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_32)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_32)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_32)
@@ -25,7 +25,7 @@ endif()
if (CONFIGTABLE AND CFFT_F32_64)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_64)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_64)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_64)
@@ -34,7 +34,7 @@ endif()
if (CONFIGTABLE AND CFFT_F32_128)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_128)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_128)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_128)
@@ -43,7 +43,7 @@ endif()
if (CONFIGTABLE AND CFFT_F32_256)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_256)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_256)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_256)
@@ -52,7 +52,7 @@ endif()
if (CONFIGTABLE AND CFFT_F32_512)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_512)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_512)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_512)
@@ -61,7 +61,7 @@ endif()
if (CONFIGTABLE AND CFFT_F32_1024)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_1024)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_1024)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_1024)
@@ -70,7 +70,7 @@ endif()
if (CONFIGTABLE AND CFFT_F32_2048)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_2048)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_2048)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_2048)
@@ -79,7 +79,7 @@ endif()
if (CONFIGTABLE AND CFFT_F32_4096)
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_TWIDDLECOEF_F32_4096)
-if (HELIUM OR MVEF)
+if (HELIUM OR MVEF AND (NOT GCC))
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FXT_4096)
else()
target_compile_definitions(${PROJECT} PUBLIC ARM_TABLE_BITREVIDX_FLT_4096)
diff --git a/Testing/Source/Tests/BIQUADF16.cpp b/Testing/Source/Tests/BIQUADF16.cpp
index 3c72cfd5..54ba98aa 100755
--- a/Testing/Source/Tests/BIQUADF16.cpp
+++ b/Testing/Source/Tests/BIQUADF16.cpp
@@ -2,7 +2,7 @@
#include
#include "Error.h"
-#define SNR_THRESHOLD 30
+#define SNR_THRESHOLD 27
/*
@@ -25,7 +25,7 @@ a double precision computation.
const float16_t *inputp = inputs.ptr();
float16_t *outp = output.ptr();
- #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
arm_biquad_mod_coef_f16 *coefsmodp = (arm_biquad_mod_coef_f16*)vecCoefs.ptr();
#endif
@@ -50,7 +50,7 @@ a double precision computation.
The filter is initialized with the coefs, blockSize and numTaps.
*/
-#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
arm_biquad_cascade_df1_mve_init_f16(&this->Sdf1,3,coefsp,coefsmodp,statep);
#else
arm_biquad_cascade_df1_init_f16(&this->Sdf1,3,coefsp,statep);
@@ -162,7 +162,7 @@ a double precision computation.
const float16_t *inputp = inputs.ptr();
float16_t *outp = output.ptr();
- #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
arm_biquad_mod_coef_f16 *coefsmodp = (arm_biquad_mod_coef_f16*)vecCoefs.ptr();
#endif
@@ -194,7 +194,7 @@ a double precision computation.
The filter is initialized with the coefs, blockSize and numTaps.
*/
-#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
arm_biquad_cascade_df1_mve_init_f16(&this->Sdf1,numStages,coefsp,coefsmodp,statep);
#else
arm_biquad_cascade_df1_init_f16(&this->Sdf1,numStages,coefsp,statep);
@@ -381,7 +381,7 @@ a double precision computation.
inputs.reload(BIQUADF16::BIQUADINPUTS_F16_ID,mgr);
coefs.reload(BIQUADF16::BIQUADCOEFS_F16_ID,mgr);
ref.reload(BIQUADF16::BIQUADREFS_F16_ID,mgr);
- #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
/* Max num stages is 47 in Python script */
vecCoefs.create(96*47,BIQUADF16::OUT_F16_ID,mgr);
#endif
@@ -401,7 +401,7 @@ a double precision computation.
coefs.reload(BIQUADF16::ALLBIQUADCOEFS_F16_ID,mgr);
ref.reload(BIQUADF16::ALLBIQUADREFS_F16_ID,mgr);
configs.reload(BIQUADF16::ALLBIQUADCONFIGS_S16_ID,mgr);
- #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
/* Max num stages is 47 in Python script */
vecCoefs.create(96*47,BIQUADF16::OUT_F16_ID,mgr);
#endif