CMSIS-DSP: Corrected compilation issues with ARM AC5 compiler.
Added AC5 support to the test framework. Upgraded gcc support.pull/19/head
Christophe Favergeon
7 years ago
parent
8ccf6883fa
commit
5309ff3334
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#! armcc -E
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; command above MUST be in first line (no comment above!)
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/*
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;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
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*/
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#include "mem_ARMCM7.h"
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/*--------------------- Flash Configuration ----------------------------------
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; <h> Flash Configuration
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; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
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; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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*----------------------------------------------------------------------------*/
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#define __ROM_BASE 0x00000000
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#define __ROM_SIZE 0x00200000
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/*--------------------- Embedded RAM Configuration ---------------------------
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; <h> RAM Configuration
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; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
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; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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*----------------------------------------------------------------------------*/
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#define __RAM_BASE 0x20000000
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#define __RAM_SIZE 0x00200000
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/*--------------------- Stack / Heap Configuration ---------------------------
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; <h> Stack / Heap Configuration
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; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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*----------------------------------------------------------------------------*/
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#define __STACK_SIZE STACK_SIZE
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#define __HEAP_SIZE HEAP_SIZE
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/*----------------------------------------------------------------------------
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User Stack & Heap boundery definition
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*----------------------------------------------------------------------------*/
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#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
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#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
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/*----------------------------------------------------------------------------
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Scatter File Definitions definition
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*----------------------------------------------------------------------------*/
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#define __RO_BASE __ROM_BASE
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#define __RO_SIZE __ROM_SIZE
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#define __RW_BASE (__RAM_BASE )
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#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
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LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
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ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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.ANY (+XO)
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}
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RW_RAM __RW_BASE __RW_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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#if __HEAP_SIZE > 0
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ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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}
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#endif
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ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
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}
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}
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@ -0,0 +1,38 @@
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/**************************************************************************//**
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* @file mem_ARMCM7.h
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* @brief Memory base and size definitions (used in scatter file)
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* @version V1.1.0
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* @date 15. May 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __MEM_ARMCM7_H
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#define __MEM_ARMCM7_H
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#define STACK_SIZE 0x00003000
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#define HEAP_SIZE 0x00100000
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#endif /* __MEM_ARMCM7_H */
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@ -0,0 +1,168 @@
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;/**************************************************************************//**
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; * @file startup_ARMCM7.s
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; * @brief CMSIS Core Device Startup File for
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; * ARMCM7 Device
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; * @version V5.4.0
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; * @date 12. December 2018
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; ******************************************************************************/
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;/*
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; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Licensed under the Apache License, Version 2.0 (the License); you may
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; * not use this file except in compliance with the License.
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; * You may obtain a copy of the License at
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; *
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; * www.apache.org/licenses/LICENSE-2.0
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; *
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; * Unless required by applicable law or agreed to in writing, software
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; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; * See the License for the specific language governing permissions and
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; * limitations under the License.
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; */
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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#include "mem_ARMCM7.h"
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;<h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;</h>
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Stack_Size EQU STACK_SIZE
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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__stack_limit
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Stack_Mem SPACE Stack_Size
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__initial_sp
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;<h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;</h>
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Heap_Size EQU HEAP_SIZE
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IF Heap_Size != 0 ; Heap is provided
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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ENDIF
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; -14 NMI Handler
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DCD HardFault_Handler ; -13 Hard Fault Handler
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DCD MemManage_Handler ; -12 MPU Fault Handler
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DCD BusFault_Handler ; -11 Bus Fault Handler
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DCD UsageFault_Handler ; -10 Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; -5 SVCall Handler
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DCD DebugMon_Handler ; -4 Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; -2 PendSV Handler
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DCD SysTick_Handler ; -1 SysTick Handler
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; Interrupts
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DCD Interrupt0_Handler ; 0 Interrupt 0
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DCD Interrupt1_Handler ; 1 Interrupt 1
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DCD Interrupt2_Handler ; 2 Interrupt 2
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DCD Interrupt3_Handler ; 3 Interrupt 3
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DCD Interrupt4_Handler ; 4 Interrupt 4
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DCD Interrupt5_Handler ; 5 Interrupt 5
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DCD Interrupt6_Handler ; 6 Interrupt 6
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DCD Interrupt7_Handler ; 7 Interrupt 7
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DCD Interrupt8_Handler ; 8 Interrupt 8
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DCD Interrupt9_Handler ; 9 Interrupt 9
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SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Macro to define default exception/interrupt handlers.
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; Default handler are weak symbols with an endless loop.
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; They can be overwritten by real handlers.
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MACRO
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Set_Default_Handler $Handler_Name
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$Handler_Name PROC
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EXPORT $Handler_Name [WEAK]
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B .
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ENDP
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MEND
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; Default exception/interrupt handler
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Set_Default_Handler NMI_Handler
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Set_Default_Handler HardFault_Handler
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Set_Default_Handler MemManage_Handler
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Set_Default_Handler BusFault_Handler
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Set_Default_Handler UsageFault_Handler
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Set_Default_Handler SVC_Handler
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Set_Default_Handler DebugMon_Handler
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Set_Default_Handler PendSV_Handler
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Set_Default_Handler SysTick_Handler
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Set_Default_Handler Interrupt0_Handler
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Set_Default_Handler Interrupt1_Handler
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Set_Default_Handler Interrupt2_Handler
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Set_Default_Handler Interrupt3_Handler
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Set_Default_Handler Interrupt4_Handler
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Set_Default_Handler Interrupt5_Handler
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Set_Default_Handler Interrupt6_Handler
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Set_Default_Handler Interrupt7_Handler
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Set_Default_Handler Interrupt8_Handler
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Set_Default_Handler Interrupt9_Handler
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ALIGN
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; User setup Stack & Heap
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IF :LNOT::DEF:__MICROLIB
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IMPORT __use_two_region_memory
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ENDIF
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EXPORT __stack_limit
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EXPORT __initial_sp
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IF Heap_Size != 0 ; Heap is provided
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EXPORT __heap_base
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EXPORT __heap_limit
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ENDIF
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END
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