From 57db4eeff92377eda4cbf7f852d8a1c7c26dd8b3 Mon Sep 17 00:00:00 2001 From: Christophe Favergeon Date: Thu, 30 Apr 2020 09:07:33 +0200 Subject: [PATCH] CMSIS-DSP: Add support for IPSS to test framework. --- Platforms/IPSS/ARMCM7/Include/ARMCM7.h | 132 ++++ Platforms/IPSS/ARMCM7/Include/ARMCM7_DP.h | 132 ++++ Platforms/IPSS/ARMCM7/Include/ARMCM7_SP.h | 132 ++++ Platforms/IPSS/ARMCM7/Include/system_ARMCM7.h | 55 ++ Platforms/IPSS/ARMCM7/LinkScripts/AC6/lnk.sct | 35 + .../IPSS/ARMCM7/LinkScripts/AC6/mem_ARMCM7.h | 38 + .../IPSS/ARMCM7/Startup/AC5/startup_ARMCM7.s | 168 +++++ .../IPSS/ARMCM7/Startup/AC6/startup_ARMCM7.s | 168 +++++ .../IPSS/ARMCM7/Startup/GCC/startup_ARMCM7.S | 170 +++++ Platforms/IPSS/ARMCM7/Startup/GCC/support.c | 36 + Platforms/IPSS/ARMCM7/system_ARMCM7.c | 525 +++++++++++++ .../Include/ARMv81MML_DSP_DP_MVE_FP.h | 132 ++++ .../IPSS/ARMv81MML/Include/system_ARMv81MML.h | 55 ++ .../IPSS/ARMv81MML/LinkScripts/AC6/lnk.sct | 29 + .../ARMv81MML/LinkScripts/AC6/mem_ARMv81MML.h | 38 + .../ARMv81MML/Startup/AC6/startup_ARMv81MML.c | 150 ++++ Platforms/IPSS/ARMv81MML/system_ARMv81MML.c | 711 ++++++++++++++++++ Platforms/IPSS/platform.cmake | 2 + Testing/TestScripts/Regression/Commands.py | 3 +- Testing/runAllTests.py | 1 - configPlatform.cmake | 6 + 21 files changed, 2716 insertions(+), 2 deletions(-) create mode 100755 Platforms/IPSS/ARMCM7/Include/ARMCM7.h create mode 100755 Platforms/IPSS/ARMCM7/Include/ARMCM7_DP.h create mode 100755 Platforms/IPSS/ARMCM7/Include/ARMCM7_SP.h create mode 100755 Platforms/IPSS/ARMCM7/Include/system_ARMCM7.h create mode 100755 Platforms/IPSS/ARMCM7/LinkScripts/AC6/lnk.sct create mode 100755 Platforms/IPSS/ARMCM7/LinkScripts/AC6/mem_ARMCM7.h create mode 100755 Platforms/IPSS/ARMCM7/Startup/AC5/startup_ARMCM7.s create mode 100755 Platforms/IPSS/ARMCM7/Startup/AC6/startup_ARMCM7.s create mode 100755 Platforms/IPSS/ARMCM7/Startup/GCC/startup_ARMCM7.S create mode 100755 Platforms/IPSS/ARMCM7/Startup/GCC/support.c create mode 100755 Platforms/IPSS/ARMCM7/system_ARMCM7.c create mode 100755 Platforms/IPSS/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h create mode 100755 Platforms/IPSS/ARMv81MML/Include/system_ARMv81MML.h create mode 100755 Platforms/IPSS/ARMv81MML/LinkScripts/AC6/lnk.sct create mode 100755 Platforms/IPSS/ARMv81MML/LinkScripts/AC6/mem_ARMv81MML.h create mode 100755 Platforms/IPSS/ARMv81MML/Startup/AC6/startup_ARMv81MML.c create mode 100755 Platforms/IPSS/ARMv81MML/system_ARMv81MML.c create mode 100755 Platforms/IPSS/platform.cmake diff --git a/Platforms/IPSS/ARMCM7/Include/ARMCM7.h b/Platforms/IPSS/ARMCM7/Include/ARMCM7.h new file mode 100755 index 00000000..4db95277 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/Include/ARMCM7.h @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file ARMCM7.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCM7 Device (configured for CM7 without FPU) + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCM7_H +#define ARMCM7_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ------------------- Processor Interrupt Numbers ------------------------------ */ + Interrupt0_IRQn = 0, + Interrupt1_IRQn = 1, + Interrupt2_IRQn = 2, + Interrupt3_IRQn = 3, + Interrupt4_IRQn = 4, + Interrupt5_IRQn = 5, + Interrupt6_IRQn = 6, + Interrupt7_IRQn = 7, + Interrupt8_IRQn = 8, + Interrupt9_IRQn = 9 + /* Interrupts 10 .. 224 are left out */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CM7_REV 0x0000U /* Core revision r0p0 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /* no FPU present */ +#define __FPU_DP 0U /* unused */ +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U +#define __DTCM_PRESENT 1U + +#include "core_cm7.h" /* Processor and core peripherals */ +#include "system_ARMCM7.h" /* System Header */ + + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCM7/Include/ARMCM7_DP.h b/Platforms/IPSS/ARMCM7/Include/ARMCM7_DP.h new file mode 100755 index 00000000..d1626fa4 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/Include/ARMCM7_DP.h @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file ARMCM7_DP.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCM7 Device (configured for CM7 with double precision FPU) + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCM7_DP_H +#define ARMCM7_DP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ------------------- Processor Interrupt Numbers ------------------------------ */ + Interrupt0_IRQn = 0, + Interrupt1_IRQn = 1, + Interrupt2_IRQn = 2, + Interrupt3_IRQn = 3, + Interrupt4_IRQn = 4, + Interrupt5_IRQn = 5, + Interrupt6_IRQn = 6, + Interrupt7_IRQn = 7, + Interrupt8_IRQn = 8, + Interrupt9_IRQn = 9 + /* Interrupts 10 .. 224 are left out */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CM7_REV 0x0000U /* Core revision r0p0 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __FPU_DP 1U /* double precision FPU */ +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U +#define __DTCM_PRESENT 1U + +#include "core_cm7.h" /* Processor and core peripherals */ +#include "system_ARMCM7.h" /* System Header */ + + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCM7_DP_H */ diff --git a/Platforms/IPSS/ARMCM7/Include/ARMCM7_SP.h b/Platforms/IPSS/ARMCM7/Include/ARMCM7_SP.h new file mode 100755 index 00000000..c9932103 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/Include/ARMCM7_SP.h @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file ARMCM7_SP.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCM7 Device (configured for CM7 with single precision FPU) + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCM7_SP_H +#define ARMCM7_SP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ------------------- Processor Interrupt Numbers ------------------------------ */ + Interrupt0_IRQn = 0, + Interrupt1_IRQn = 1, + Interrupt2_IRQn = 2, + Interrupt3_IRQn = 3, + Interrupt4_IRQn = 4, + Interrupt5_IRQn = 5, + Interrupt6_IRQn = 6, + Interrupt7_IRQn = 7, + Interrupt8_IRQn = 8, + Interrupt9_IRQn = 9 + /* Interrupts 10 .. 224 are left out */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CM7_REV 0x0000U /* Core revision r0p0 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __FPU_DP 0U /* single precision FPU */ +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U +#define __DTCM_PRESENT 1U + +#include "core_cm7.h" /* Processor and core peripherals */ +#include "system_ARMCM7.h" /* System Header */ + + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCM7_SP_H */ diff --git a/Platforms/IPSS/ARMCM7/Include/system_ARMCM7.h b/Platforms/IPSS/ARMCM7/Include/system_ARMCM7.h new file mode 100755 index 00000000..ec831e09 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/Include/system_ARMCM7.h @@ -0,0 +1,55 @@ +/**************************************************************************//** + * @file system_ARMCM7.h + * @brief CMSIS Device System Header File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_ARMCM7_H +#define SYSTEM_ARMCM7_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCM7/LinkScripts/AC6/lnk.sct b/Platforms/IPSS/ARMCM7/LinkScripts/AC6/lnk.sct new file mode 100755 index 00000000..7cc17d07 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/LinkScripts/AC6/lnk.sct @@ -0,0 +1,35 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +#include "mem_ARMCM7.h" + +LOAD_REGION 0x0 +{ + CODE +0 0x30000 + { + *.o (RESET, +First) + * (InRoot$$$Sections) + * (+RO-CODE) + } + + DATA 0x20000000 0xF0000 + { + * (+RO-DATA) + * (+RW,+ZI) + } + + ARM_LIB_STACK 0x21000000 ALIGN 64 EMPTY 0x00002000 + {} + ARM_LIB_HEAP 0x22000000 ALIGN 64 EMPTY 0x00100000 + {} +} + + + + + + diff --git a/Platforms/IPSS/ARMCM7/LinkScripts/AC6/mem_ARMCM7.h b/Platforms/IPSS/ARMCM7/LinkScripts/AC6/mem_ARMCM7.h new file mode 100755 index 00000000..84a1ff1d --- /dev/null +++ b/Platforms/IPSS/ARMCM7/LinkScripts/AC6/mem_ARMCM7.h @@ -0,0 +1,38 @@ +/**************************************************************************//** + * @file mem_ARMCM7.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCM7_H +#define __MEM_ARMCM7_H + + + +#define STACK_SIZE 0x00003000 +#define HEAP_SIZE 0x00100000 + + + +#endif /* __MEM_ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCM7/Startup/AC5/startup_ARMCM7.s b/Platforms/IPSS/ARMCM7/Startup/AC5/startup_ARMCM7.s new file mode 100755 index 00000000..333d3581 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/Startup/AC5/startup_ARMCM7.s @@ -0,0 +1,168 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.4.0 +; * @date 12. December 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +#include "mem_ARMCM7.h" + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU STACK_SIZE + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU HEAP_SIZE + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + IF :LNOT::DEF:__MICROLIB + IMPORT __use_two_region_memory + ENDIF + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Platforms/IPSS/ARMCM7/Startup/AC6/startup_ARMCM7.s b/Platforms/IPSS/ARMCM7/Startup/AC6/startup_ARMCM7.s new file mode 100755 index 00000000..333d3581 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/Startup/AC6/startup_ARMCM7.s @@ -0,0 +1,168 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.4.0 +; * @date 12. December 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +#include "mem_ARMCM7.h" + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU STACK_SIZE + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU HEAP_SIZE + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + IF :LNOT::DEF:__MICROLIB + IMPORT __use_two_region_memory + ENDIF + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Platforms/IPSS/ARMCM7/Startup/GCC/startup_ARMCM7.S b/Platforms/IPSS/ARMCM7/Startup/GCC/startup_ARMCM7.S new file mode 100755 index 00000000..4c03cfcd --- /dev/null +++ b/Platforms/IPSS/ARMCM7/Startup/GCC/startup_ARMCM7.S @@ -0,0 +1,170 @@ +/**************************************************************************//** + * @file startup_ARMCM7.S + * @brief CMSIS-Core(M) Device Startup File for Cortex-M7 Device + * @version V2.0.0 + * @date 20. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + .syntax unified + .arch armv7e-m + + .section .vectors + .align 2 + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long Interrupt0_Handler /* 0 Interrupt 0 */ + .long Interrupt1_Handler /* 1 Interrupt 1 */ + .long Interrupt2_Handler /* 2 Interrupt 2 */ + .long Interrupt3_Handler /* 3 Interrupt 3 */ + .long Interrupt4_Handler /* 4 Interrupt 4 */ + .long Interrupt5_Handler /* 5 Interrupt 5 */ + .long Interrupt6_Handler /* 6 Interrupt 6 */ + .long Interrupt7_Handler /* 7 Interrupt 7 */ + .long Interrupt8_Handler /* 8 Interrupt 8 */ + .long Interrupt9_Handler /* 9 Interrupt 9 */ + + .space (214 * 4) /* Interrupts 10 .. 224 are left out */ +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors + + + .thumb + .section .text + .align 2 + + .thumb_func + .type Reset_Handler, %function + .globl Reset_Handler + .fnstart +Reset_Handler: + bl SystemInit + + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 +.L_loop0_done: + + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: + + bl _start + + .fnend + .size Reset_Handler, . - Reset_Handler + + + .thumb_func + .type Default_Handler, %function + .weak Default_Handler + .fnstart +Default_Handler: + b . + .fnend + .size Default_Handler, . - Default_Handler + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + + .end diff --git a/Platforms/IPSS/ARMCM7/Startup/GCC/support.c b/Platforms/IPSS/ARMCM7/Startup/GCC/support.c new file mode 100755 index 00000000..740f6b08 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/Startup/GCC/support.c @@ -0,0 +1,36 @@ + +#ifdef __cplusplus +extern "C" +{ +#endif + +char * _sbrk(int incr); + +void __malloc_lock() ; +void __malloc_unlock(); + +char __HeapBase, __HeapLimit; // make sure to define these symbols in linker command file +#ifdef __cplusplus +} +#endif + +static int totalBytesProvidedBySBRK = 0; + +//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file). +char * sbrk(int incr) { + static char *currentHeapEnd = &__HeapBase; + char *previousHeapEnd = currentHeapEnd; + if (currentHeapEnd + incr > &__HeapLimit) { + return (char *)-1; // the malloc-family routine that called sbrk will return 0 + } + currentHeapEnd += incr; + + totalBytesProvidedBySBRK += incr; + + return (char *) previousHeapEnd; +} +//! Synonym for sbrk. +char * _sbrk(int incr) { return sbrk(incr); }; + +void __malloc_lock() { }; +void __malloc_unlock() { }; \ No newline at end of file diff --git a/Platforms/IPSS/ARMCM7/system_ARMCM7.c b/Platforms/IPSS/ARMCM7/system_ARMCM7.c new file mode 100755 index 00000000..732aa491 --- /dev/null +++ b/Platforms/IPSS/ARMCM7/system_ARMCM7.c @@ -0,0 +1,525 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define SERIAL_BASE_ADDRESS (0xA8000000ul) + +#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS) + + + + + +int stdout_putchar(char txchar) +{ + SERIAL_DATA = txchar; +} + +int stderr_putchar(char txchar) +{ + return stdout_putchar(txchar); +} + +void ttywrch (int ch) +{ + stdout_putchar(ch); +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} + +#if __IS_COMPILER_ARM_COMPILER_6__ +__asm(".global __use_no_semihosting\n\t"); +# ifndef __MICROLIB +__asm(".global __ARM_use_no_argv\n\t"); +# endif +#endif + +/** + Writes the character specified by c (converted to an unsigned char) to + the output stream pointed to by stream, at the position indicated by the + associated file position indicator (if defined), and advances the + indicator appropriately. If the file position indicator is not defined, + the character is appended to the output stream. + + \param[in] c Character + \param[in] stream Stream handle + + \return The character written. If a write error occurs, the error + indicator is set and fputc returns EOF. +*/ +__attribute__((weak)) +int fputc (int c, FILE * stream) +{ + if (stream == &__stdout) { + return (stdout_putchar(c)); + } + + if (stream == &__stderr) { + return (stderr_putchar(c)); + } + + return (-1); +} + +/* IO device file handles. */ +#define FH_STDIN 0x8001 +#define FH_STDOUT 0x8002 +#define FH_STDERR 0x8003 + +const char __stdin_name[] = ":STDIN"; +const char __stdout_name[] = ":STDOUT"; +const char __stderr_name[] = ":STDERR"; + +#define RETARGET_SYS 1 +#define RTE_Compiler_IO_STDOUT 1 +#define RTE_Compiler_IO_STDERR 1 +/** + Defined in rt_sys.h, this function opens a file. + + The _sys_open() function is required by fopen() and freopen(). These + functions in turn are required if any file input/output function is to + be used. + The openmode parameter is a bitmap whose bits mostly correspond directly to + the ISO mode specification. Target-dependent extensions are possible, but + freopen() must also be extended. + + \param[in] name File name + \param[in] openmode Mode specification bitmap + + \return The return value is ?1 if an error occurs. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +FILEHANDLE _sys_open (const char *name, int openmode) { +#if (!defined(RTE_Compiler_IO_File)) + (void)openmode; +#endif + + if (name == NULL) { + return (-1); + } + + if (name[0] == ':') { + if (strcmp(name, ":STDIN") == 0) { + return (FH_STDIN); + } + if (strcmp(name, ":STDOUT") == 0) { + return (FH_STDOUT); + } + if (strcmp(name, ":STDERR") == 0) { + return (FH_STDERR); + } + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_open(name, openmode)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function closes a file previously opened + with _sys_open(). + + This function must be defined if any input/output function is to be used. + + \param[in] fh File handle + + \return The return value is 0 if successful. A nonzero value indicates + an error. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_close (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (0); + case FH_STDOUT: + return (0); + case FH_STDERR: + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_close(fh)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function writes the contents of a buffer to a file + previously opened with _sys_open(). + + \note The mode parameter is here for historical reasons. It contains + nothing useful and must be ignored. + + \param[in] fh File handle + \param[in] buf Data buffer + \param[in] len Data length + \param[in] mode Ignore this parameter + + \return The return value is either: + - a positive number representing the number of characters not + written (so any nonzero return value denotes a failure of + some sort) + - a negative number indicating an error. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) { +#if (defined(RTE_Compiler_IO_STDOUT) || defined(RTE_Compiler_IO_STDERR)) + int ch; +#elif (!defined(RTE_Compiler_IO_File)) + (void)buf; + (void)len; +#endif + (void)mode; + + switch (fh) { + case FH_STDIN: + return (-1); + case FH_STDOUT: +#ifdef RTE_Compiler_IO_STDOUT + for (; len; len--) { + ch = *buf++; + + stdout_putchar(ch); + } +#endif + return (0); + case FH_STDERR: +#ifdef RTE_Compiler_IO_STDERR + for (; len; len--) { + ch = *buf++; + + stderr_putchar(ch); + } +#endif + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_write(fh, buf, len)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function reads the contents of a file into a buffer. + + Reading up to and including the last byte of data does not turn on the EOF + indicator. The EOF indicator is only reached when an attempt is made to read + beyond the last byte of data. The target-independent code is capable of + handling: + - the EOF indicator being returned in the same read as the remaining bytes + of data that precede the EOF + - the EOF indicator being returned on its own after the remaining bytes of + data have been returned in a previous read. + + \note The mode parameter is here for historical reasons. It contains + nothing useful and must be ignored. + + \param[in] fh File handle + \param[in] buf Data buffer + \param[in] len Data length + \param[in] mode Ignore this parameter + + \return The return value is one of the following: + - The number of bytes not read (that is, len - result number of + bytes were read). + - An error indication. + - An EOF indicator. The EOF indication involves the setting of + 0x80000000 in the normal result. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) { +#ifdef RTE_Compiler_IO_STDIN + int ch; +#elif (!defined(RTE_Compiler_IO_File)) + (void)buf; + (void)len; +#endif + (void)mode; + + switch (fh) { + case FH_STDIN: +#ifdef RTE_Compiler_IO_STDIN + ch = stdin_getchar(); + if (ch < 0) { + return ((int)(len | 0x80000000U)); + } + *buf++ = (uint8_t)ch; +#if (STDIN_ECHO != 0) + stdout_putchar(ch); +#endif + len--; + return ((int)(len)); +#else + return ((int)(len | 0x80000000U)); +#endif + case FH_STDOUT: + return (-1); + case FH_STDERR: + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_read(fh, buf, len)); +#endif +#else + return (-1); +#endif +} +#endif + + + + + +/** + Defined in rt_sys.h, this function determines if a file handle identifies + a terminal. + + When a file is connected to a terminal device, this function is used to + provide unbuffered behavior by default (in the absence of a call to + set(v)buf) and to prohibit seeking. + + \param[in] fh File handle + + \return The return value is one of the following values: + - 0: There is no interactive device. + - 1: There is an interactive device. + - other: An error occurred. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_istty (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (1); + case FH_STDOUT: + return (1); + case FH_STDERR: + return (1); + } + + return (0); +} +#endif + + +/** + Defined in rt_sys.h, this function puts the file pointer at offset pos from + the beginning of the file. + + This function sets the current read or write position to the new location pos + relative to the start of the current file fh. + + \param[in] fh File handle + \param[in] pos File pointer offset + + \return The result is: + - non-negative if no error occurs + - negative if an error occurs +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_seek (FILEHANDLE fh, long pos) { +#if (!defined(RTE_Compiler_IO_File)) + (void)pos; +#endif + + switch (fh) { + case FH_STDIN: + return (-1); + case FH_STDOUT: + return (-1); + case FH_STDERR: + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_seek(fh, (uint32_t)pos)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function returns the current length of a file. + + This function is used by _sys_seek() to convert an offset relative to the + end of a file into an offset relative to the beginning of the file. + You do not have to define _sys_flen() if you do not intend to use fseek(). + If you retarget at system _sys_*() level, you must supply _sys_flen(), + even if the underlying system directly supports seeking relative to the + end of a file. + + \param[in] fh File handle + + \return This function returns the current length of the file fh, + or a negative error indicator. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +long _sys_flen (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (0); + case FH_STDOUT: + return (0); + case FH_STDERR: + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_flen(fh)); +#endif +#else + return (0); +#endif +} +#endif + +#define log_str(...) \ + do { \ + const char *pchSrc = __VA_ARGS__; \ + uint_fast16_t hwSize = sizeof(__VA_ARGS__); \ + do { \ + stdout_putchar(*pchSrc++); \ + } while(--hwSize); \ + } while(0) + + +void _sys_exit(int n) +{ + (void)n; + log_str("\n"); + log_str("_[TEST COMPLETE]_________________________________________________\n"); + log_str("\n\n"); + stdout_putchar(4); + while(1); +} + +extern void ttywrch (int ch); +__attribute__((weak)) +void _ttywrch (int ch) +{ + ttywrch(ch); +} diff --git a/Platforms/IPSS/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h b/Platforms/IPSS/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h new file mode 100755 index 00000000..335f001f --- /dev/null +++ b/Platforms/IPSS/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file ARMv81MML_DP.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * Armv8.1-M Mainline Device Series (configured for Armv8.1-M Mainline with double precision FPU, with DSP extension, with TrustZone) + * @version V1.0.0 + * @date 25. February 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMv81MML_DSP_DP_H +#define ARMv81MML_DSP_DP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* -------------------- Armv8.1-M Mainline Processor Exceptions Numbers --------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ------------------- Processor Interrupt Numbers ------------------------------ */ + Interrupt0_IRQn = 0, + Interrupt1_IRQn = 1, + Interrupt2_IRQn = 2, + Interrupt3_IRQn = 3, + Interrupt4_IRQn = 4, + Interrupt5_IRQn = 5, + Interrupt6_IRQn = 6, + Interrupt7_IRQn = 7, + Interrupt8_IRQn = 8, + Interrupt9_IRQn = 9 + /* Interrupts 10 .. 480 are left out */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* --- Configuration of the Armv8.1-M Mainline Processor and Core Peripherals --- */ +#define __ARMv81MML_REV 0x0001U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __FPU_DP 1U /* double precision FPU */ +#define __DSP_PRESENT 1U /* DSP extension present */ +#define __MVE_PRESENT 1U /* MVE extensions present */ +#define __MVE_FP 1U /* MVE floating point present */ + +#include "core_armv81mml.h" /* Processor and core peripherals */ +#include "system_ARMv81MML.h" /* System Header */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMv81MML_DSP_DP_H */ diff --git a/Platforms/IPSS/ARMv81MML/Include/system_ARMv81MML.h b/Platforms/IPSS/ARMv81MML/Include/system_ARMv81MML.h new file mode 100755 index 00000000..43218c6a --- /dev/null +++ b/Platforms/IPSS/ARMv81MML/Include/system_ARMv81MML.h @@ -0,0 +1,55 @@ +/**************************************************************************//** + * @file system_ARMv81MML.h + * @brief CMSIS Device System Header File for + * Armv8.1-M Mainline Device Series + * @version V1.0.0 + * @date 25. February 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_ARMv81MML_H +#define SYSTEM_ARMv81MML_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ARMv81MML_H */ diff --git a/Platforms/IPSS/ARMv81MML/LinkScripts/AC6/lnk.sct b/Platforms/IPSS/ARMv81MML/LinkScripts/AC6/lnk.sct new file mode 100755 index 00000000..923e3952 --- /dev/null +++ b/Platforms/IPSS/ARMv81MML/LinkScripts/AC6/lnk.sct @@ -0,0 +1,29 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +#include "mem_ARMv81MML.h" + +LOAD_REGION 0x0 +{ + CODE +0 0x30000 + { + *.o (RESET, +First) + * (InRoot$$$Sections) + * (+RO-CODE) + } + + DATA 0x20000000 0xF0000 + { + * (+RO-DATA) + * (+RW,+ZI) + } + + ARM_LIB_STACK 0x21000000 ALIGN 64 EMPTY 0x00002000 + {} + ARM_LIB_HEAP 0x22000000 ALIGN 64 EMPTY 0x00100000 + {} +} diff --git a/Platforms/IPSS/ARMv81MML/LinkScripts/AC6/mem_ARMv81MML.h b/Platforms/IPSS/ARMv81MML/LinkScripts/AC6/mem_ARMv81MML.h new file mode 100755 index 00000000..74cb2123 --- /dev/null +++ b/Platforms/IPSS/ARMv81MML/LinkScripts/AC6/mem_ARMv81MML.h @@ -0,0 +1,38 @@ +/**************************************************************************//** + * @file mem_ARMCM7.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMV81MML_H +#define __MEM_ARMV81MML_H + + + +#define STACK_SIZE 0x00003000 +#define HEAP_SIZE 0x00100000 + + + +#endif /* __MEM_ARMV81MML_H */ diff --git a/Platforms/IPSS/ARMv81MML/Startup/AC6/startup_ARMv81MML.c b/Platforms/IPSS/ARMv81MML/Startup/AC6/startup_ARMv81MML.c new file mode 100755 index 00000000..eccf7258 --- /dev/null +++ b/Platforms/IPSS/ARMv81MML/Startup/AC6/startup_ARMv81MML.c @@ -0,0 +1,150 @@ +/****************************************************************************** + * @file startup_ARMv81MML.c + * @brief CMSIS Core Device Startup File for ARMv81MML Device + * @version V2.0.1 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMv81MML_DSP_DP_MVE_FP) + #include "ARMv81MML_DSP_DP_MVE_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void) __NO_RETURN; +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[496]; + const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Platforms/IPSS/ARMv81MML/system_ARMv81MML.c b/Platforms/IPSS/ARMv81MML/system_ARMv81MML.c new file mode 100755 index 00000000..7fef3e97 --- /dev/null +++ b/Platforms/IPSS/ARMv81MML/system_ARMv81MML.c @@ -0,0 +1,711 @@ +/**************************************************************************//** + * @file system_ARMv81MML.c + * @brief CMSIS Device System Source File for + * Armv8.1-M Mainline Device Series + * @version V1.2.0 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include + + +#if defined (ARMv81MML_DSP_DP_MVE_FP) + #include "ARMv81MML_DSP_DP_MVE_FP.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMv81MML.h" +#endif + + + +#include "cmsis_compiler.h" + +//! \name The macros to identify the compiler +//! @{ + +//! \note for IAR +#ifdef __IS_COMPILER_IAR__ +# undef __IS_COMPILER_IAR__ +#endif +#if defined(__IAR_SYSTEMS_ICC__) +# define __IS_COMPILER_IAR__ 1 +#endif + + + + +//! \note for arm compiler 5 +#ifdef __IS_COMPILER_ARM_COMPILER_5__ +# undef __IS_COMPILER_ARM_COMPILER_5__ +#endif +#if ((__ARMCC_VERSION >= 5000000) && (__ARMCC_VERSION < 6000000)) +# define __IS_COMPILER_ARM_COMPILER_5__ 1 +#endif +//! @} + +//! \note for arm compiler 6 +#ifdef __IS_COMPILER_ARM_COMPILER_6__ +# undef __IS_COMPILER_ARM_COMPILER_6__ +#endif +#if ((__ARMCC_VERSION >= 6000000) && (__ARMCC_VERSION < 7000000)) +# define __IS_COMPILER_ARM_COMPILER_6__ 1 +#endif + +#ifdef __IS_COMPILER_LLVM__ +# undef __IS_COMPILER_LLVM__ +#endif +#if defined(__clang__) && !__IS_COMPILER_ARM_COMPILER_6__ +# define __IS_COMPILER_LLVM__ 1 +#else +//! \note for gcc +#ifdef __IS_COMPILER_GCC__ +# undef __IS_COMPILER_GCC__ +#endif +#if defined(__GNUC__) && !(__IS_COMPILER_ARM_COMPILER_6__ || __IS_COMPILER_LLVM__) +# define __IS_COMPILER_GCC__ 1 +#endif +//! @} +#endif +//! @} + +#define SAFE_ATOM_CODE(...) \ +{ \ + uint32_t wOrig = __disable_irq(); \ + __VA_ARGS__; \ + __set_PRIMASK(wOrig); \ +} + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M */ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + +#define DEBUG_DEMCR (*((unsigned int *)0xE000EDFC)) +#define DEBUG_TRCENA (1<<24) //Global debug enable bit + +#define CCR (*((volatile unsigned int *)0xE000ED14)) +#define CCR_DL (1 << 19) + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + UART functions + *----------------------------------------------------------------------------*/ + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */ + +/* CMSDK_UART STATE Register Definitions */ +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */ + +/* CMSDK_UART CTRL Register Definitions */ +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */ + +/* CMSDK_UART BAUDDIV Register Definitions */ +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define SERIAL_BASE_ADDRESS (0xA8000000ul) + +#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS) + + + + + +int stdout_putchar(char txchar) +{ + SERIAL_DATA = txchar; +} + +int stderr_putchar(char txchar) +{ + return stdout_putchar(txchar); +} + +void ttywrch (int ch) +{ + stdout_putchar(ch); +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__MVE_USED) && (__MVE_USED == 1U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + // TZ_SAU_Setup(); +#endif + + // SystemCoreClock = SYSTEM_CLOCK; + + //Disable debug + // DEBUG_DEMCR &=~ DEBUG_TRCENA; + + // enable DL branch cache + CCR |= CCR_DL; + + + +} + +__attribute__((constructor(255))) +void platform_init(void) +{ + printf("\nMPS3 ARMv81MML Generic Template...\n"); + printf("\n_[TEST START]____________________________________________________\n"); +} + + +#if __IS_COMPILER_ARM_COMPILER_6__ +__asm(".global __use_no_semihosting\n\t"); +# ifndef __MICROLIB +__asm(".global __ARM_use_no_argv\n\t"); +# endif +#endif + +/** + Writes the character specified by c (converted to an unsigned char) to + the output stream pointed to by stream, at the position indicated by the + associated file position indicator (if defined), and advances the + indicator appropriately. If the file position indicator is not defined, + the character is appended to the output stream. + + \param[in] c Character + \param[in] stream Stream handle + + \return The character written. If a write error occurs, the error + indicator is set and fputc returns EOF. +*/ +__attribute__((weak)) +int fputc (int c, FILE * stream) +{ + if (stream == &__stdout) { + return (stdout_putchar(c)); + } + + if (stream == &__stderr) { + return (stderr_putchar(c)); + } + + return (-1); +} + +/* IO device file handles. */ +#define FH_STDIN 0x8001 +#define FH_STDOUT 0x8002 +#define FH_STDERR 0x8003 + +const char __stdin_name[] = ":STDIN"; +const char __stdout_name[] = ":STDOUT"; +const char __stderr_name[] = ":STDERR"; + +#define RETARGET_SYS 1 +#define RTE_Compiler_IO_STDOUT 1 +#define RTE_Compiler_IO_STDERR 1 +/** + Defined in rt_sys.h, this function opens a file. + + The _sys_open() function is required by fopen() and freopen(). These + functions in turn are required if any file input/output function is to + be used. + The openmode parameter is a bitmap whose bits mostly correspond directly to + the ISO mode specification. Target-dependent extensions are possible, but + freopen() must also be extended. + + \param[in] name File name + \param[in] openmode Mode specification bitmap + + \return The return value is ?1 if an error occurs. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +FILEHANDLE _sys_open (const char *name, int openmode) { +#if (!defined(RTE_Compiler_IO_File)) + (void)openmode; +#endif + + if (name == NULL) { + return (-1); + } + + if (name[0] == ':') { + if (strcmp(name, ":STDIN") == 0) { + return (FH_STDIN); + } + if (strcmp(name, ":STDOUT") == 0) { + return (FH_STDOUT); + } + if (strcmp(name, ":STDERR") == 0) { + return (FH_STDERR); + } + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_open(name, openmode)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function closes a file previously opened + with _sys_open(). + + This function must be defined if any input/output function is to be used. + + \param[in] fh File handle + + \return The return value is 0 if successful. A nonzero value indicates + an error. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_close (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (0); + case FH_STDOUT: + return (0); + case FH_STDERR: + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_close(fh)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function writes the contents of a buffer to a file + previously opened with _sys_open(). + + \note The mode parameter is here for historical reasons. It contains + nothing useful and must be ignored. + + \param[in] fh File handle + \param[in] buf Data buffer + \param[in] len Data length + \param[in] mode Ignore this parameter + + \return The return value is either: + - a positive number representing the number of characters not + written (so any nonzero return value denotes a failure of + some sort) + - a negative number indicating an error. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) { +#if (defined(RTE_Compiler_IO_STDOUT) || defined(RTE_Compiler_IO_STDERR)) + int ch; +#elif (!defined(RTE_Compiler_IO_File)) + (void)buf; + (void)len; +#endif + (void)mode; + + switch (fh) { + case FH_STDIN: + return (-1); + case FH_STDOUT: +#ifdef RTE_Compiler_IO_STDOUT + for (; len; len--) { + ch = *buf++; + + stdout_putchar(ch); + } +#endif + return (0); + case FH_STDERR: +#ifdef RTE_Compiler_IO_STDERR + for (; len; len--) { + ch = *buf++; + + stderr_putchar(ch); + } +#endif + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_write(fh, buf, len)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function reads the contents of a file into a buffer. + + Reading up to and including the last byte of data does not turn on the EOF + indicator. The EOF indicator is only reached when an attempt is made to read + beyond the last byte of data. The target-independent code is capable of + handling: + - the EOF indicator being returned in the same read as the remaining bytes + of data that precede the EOF + - the EOF indicator being returned on its own after the remaining bytes of + data have been returned in a previous read. + + \note The mode parameter is here for historical reasons. It contains + nothing useful and must be ignored. + + \param[in] fh File handle + \param[in] buf Data buffer + \param[in] len Data length + \param[in] mode Ignore this parameter + + \return The return value is one of the following: + - The number of bytes not read (that is, len - result number of + bytes were read). + - An error indication. + - An EOF indicator. The EOF indication involves the setting of + 0x80000000 in the normal result. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) { +#ifdef RTE_Compiler_IO_STDIN + int ch; +#elif (!defined(RTE_Compiler_IO_File)) + (void)buf; + (void)len; +#endif + (void)mode; + + switch (fh) { + case FH_STDIN: +#ifdef RTE_Compiler_IO_STDIN + ch = stdin_getchar(); + if (ch < 0) { + return ((int)(len | 0x80000000U)); + } + *buf++ = (uint8_t)ch; +#if (STDIN_ECHO != 0) + stdout_putchar(ch); +#endif + len--; + return ((int)(len)); +#else + return ((int)(len | 0x80000000U)); +#endif + case FH_STDOUT: + return (-1); + case FH_STDERR: + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_read(fh, buf, len)); +#endif +#else + return (-1); +#endif +} +#endif + + + + + +/** + Defined in rt_sys.h, this function determines if a file handle identifies + a terminal. + + When a file is connected to a terminal device, this function is used to + provide unbuffered behavior by default (in the absence of a call to + set(v)buf) and to prohibit seeking. + + \param[in] fh File handle + + \return The return value is one of the following values: + - 0: There is no interactive device. + - 1: There is an interactive device. + - other: An error occurred. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_istty (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (1); + case FH_STDOUT: + return (1); + case FH_STDERR: + return (1); + } + + return (0); +} +#endif + + +/** + Defined in rt_sys.h, this function puts the file pointer at offset pos from + the beginning of the file. + + This function sets the current read or write position to the new location pos + relative to the start of the current file fh. + + \param[in] fh File handle + \param[in] pos File pointer offset + + \return The result is: + - non-negative if no error occurs + - negative if an error occurs +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_seek (FILEHANDLE fh, long pos) { +#if (!defined(RTE_Compiler_IO_File)) + (void)pos; +#endif + + switch (fh) { + case FH_STDIN: + return (-1); + case FH_STDOUT: + return (-1); + case FH_STDERR: + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_seek(fh, (uint32_t)pos)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function returns the current length of a file. + + This function is used by _sys_seek() to convert an offset relative to the + end of a file into an offset relative to the beginning of the file. + You do not have to define _sys_flen() if you do not intend to use fseek(). + If you retarget at system _sys_*() level, you must supply _sys_flen(), + even if the underlying system directly supports seeking relative to the + end of a file. + + \param[in] fh File handle + + \return This function returns the current length of the file fh, + or a negative error indicator. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +long _sys_flen (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (0); + case FH_STDOUT: + return (0); + case FH_STDERR: + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_flen(fh)); +#endif +#else + return (0); +#endif +} +#endif + +#define log_str(...) \ + do { \ + const char *pchSrc = __VA_ARGS__; \ + uint_fast16_t hwSize = sizeof(__VA_ARGS__); \ + do { \ + stdout_putchar(*pchSrc++); \ + } while(--hwSize); \ + } while(0) + + +void _sys_exit(int n) +{ + (void)n; + log_str("\n"); + log_str("_[TEST COMPLETE]_________________________________________________\n"); + log_str("\n\n"); + stdout_putchar(4); + while(1); +} + +extern void ttywrch (int ch); +__attribute__((weak)) +void _ttywrch (int ch) +{ + ttywrch(ch); +} + diff --git a/Platforms/IPSS/platform.cmake b/Platforms/IPSS/platform.cmake new file mode 100755 index 00000000..8a097de3 --- /dev/null +++ b/Platforms/IPSS/platform.cmake @@ -0,0 +1,2 @@ +function(configure_platform PROJECTNAME ROOT CORE PLATFORMFOLDER) +endfunction() \ No newline at end of file diff --git a/Testing/TestScripts/Regression/Commands.py b/Testing/TestScripts/Regression/Commands.py index 6ccccb56..a9e94c85 100755 --- a/Testing/TestScripts/Regression/Commands.py +++ b/Testing/TestScripts/Regression/Commands.py @@ -10,6 +10,7 @@ import glob from pathlib import Path DEBUGMODE = False +KEEPBUILDFOLDER = False NOTESTFAILED = 0 MAKEFAILED = 1 @@ -207,7 +208,7 @@ class BuildConfig: def cleanFolder(self): print("Delete %s\n" % self.path()) #DEBUG - if not DEBUGMODE: + if not DEBUGMODE and not KEEPBUILDFOLDER: shutil.rmtree(self.path()) # Archive results and currentConfig.csv to another folder diff --git a/Testing/runAllTests.py b/Testing/runAllTests.py index 816f70b9..0ff06cb6 100755 --- a/Testing/runAllTests.py +++ b/Testing/runAllTests.py @@ -234,7 +234,6 @@ for t in config["TOOLCHAINS"]: msg("Testing toolchain %s\n" % cmake) buildAndTest(t,localConfig,cmake,sim) -exit(1) logFailedBuild(args.r,failedBuild) sys.exit(testFailed) diff --git a/configPlatform.cmake b/configPlatform.cmake index 866c42ec..1b6514e7 100644 --- a/configPlatform.cmake +++ b/configPlatform.cmake @@ -18,6 +18,12 @@ SET(PLATFORMID "SDSIM") list(APPEND CMAKE_MODULE_PATH ${SDSIMROOT}) endif() +if (PLATFORM STREQUAL "IPSS") +SET(PLATFORMFOLDER ${ROOT}/CMSIS/DSP/Platforms/IPSS) +SET(PLATFORMID "IPSS") +list(APPEND CMAKE_MODULE_PATH ${ROOT}/CMSIS/DSP/Platforms/IPSS) +endif() + SET(CORE ARMCM7)