Christophe Favergeon
6 years ago
parent
e1c24fcafc
commit
986ace8499
@ -0,0 +1,132 @@
|
||||
/**************************************************************************//**
|
||||
* @file ARMCM7.h
|
||||
* @brief CMSIS Core Peripheral Access Layer Header File for
|
||||
* ARMCM7 Device (configured for CM7 without FPU)
|
||||
* @version V5.3.1
|
||||
* @date 09. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef ARMCR52_H
|
||||
#define ARMCR52_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ------------------------- Interrupt Number Definition ------------------------ */
|
||||
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* ------------------- Processor Exceptions Numbers ----------------------------- */
|
||||
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
|
||||
|
||||
/* ------------------- Processor Interrupt Numbers ------------------------------ */
|
||||
Interrupt0_IRQn = 0,
|
||||
Interrupt1_IRQn = 1,
|
||||
Interrupt2_IRQn = 2,
|
||||
Interrupt3_IRQn = 3,
|
||||
Interrupt4_IRQn = 4,
|
||||
Interrupt5_IRQn = 5,
|
||||
Interrupt6_IRQn = 6,
|
||||
Interrupt7_IRQn = 7,
|
||||
Interrupt8_IRQn = 8,
|
||||
Interrupt9_IRQn = 9
|
||||
/* Interrupts 10 .. 224 are left out */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Processor and Core Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/* ------- Start of section using anonymous unions and disabling warnings ------- */
|
||||
#if defined (__CC_ARM)
|
||||
#pragma push
|
||||
#pragma anon_unions
|
||||
#elif defined (__ICCARM__)
|
||||
#pragma language=extended
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wc11-extensions"
|
||||
#pragma clang diagnostic ignored "-Wreserved-id-macro"
|
||||
#elif defined (__GNUC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined (__TMS470__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined (__TASKING__)
|
||||
#pragma warning 586
|
||||
#elif defined (__CSMC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#else
|
||||
#warning Not supported compiler type
|
||||
#endif
|
||||
|
||||
|
||||
/* -------- Configuration of Core Peripherals ----------------------------------- */
|
||||
#define __CR8_REV 0x0000U /* Core revision r0p0 */
|
||||
#define __MPU_PRESENT 1U /* MPU present */
|
||||
#define __VTOR_PRESENT 1U /* VTOR present */
|
||||
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /* no FPU present */
|
||||
#define __FPU_DP 1U /* unused */
|
||||
#define __ICACHE_PRESENT 1U
|
||||
#define __DCACHE_PRESENT 1U
|
||||
#define __DTCM_PRESENT 1U
|
||||
|
||||
#include "core_cr52.h" /* Processor and core peripherals */
|
||||
#include "system_ARMCR52.h" /* System Header */
|
||||
|
||||
|
||||
|
||||
/* -------- End of section using anonymous unions and disabling warnings -------- */
|
||||
#if defined (__CC_ARM)
|
||||
#pragma pop
|
||||
#elif defined (__ICCARM__)
|
||||
/* leave anonymous unions enabled */
|
||||
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
#pragma clang diagnostic pop
|
||||
#elif defined (__GNUC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined (__TMS470__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined (__TASKING__)
|
||||
#pragma warning restore
|
||||
#elif defined (__CSMC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#else
|
||||
#warning Not supported compiler type
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARMCM7_H */
|
||||
@ -0,0 +1,55 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM7.h
|
||||
* @brief CMSIS Device System Header File for
|
||||
* ARMCM7 Device
|
||||
* @version V5.3.1
|
||||
* @date 09. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_ARMCM7_H
|
||||
#define SYSTEM_ARMCM7_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Setup the microcontroller system.
|
||||
|
||||
Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Update SystemCoreClock variable.
|
||||
|
||||
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_ARMCM7_H */
|
||||
@ -0,0 +1,40 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc
|
||||
; command above MUST be in first line (no comment above!)
|
||||
|
||||
/*
|
||||
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
|
||||
*/
|
||||
|
||||
#include "mem_ARMCR52.h"
|
||||
|
||||
|
||||
;*******************************************************
|
||||
;
|
||||
; Copyright (c) 2018 Arm Limited. All rights reserved.
|
||||
;
|
||||
;*******************************************************
|
||||
|
||||
; Scatter-file for Cortex-Rv8 bare-metal minimal example
|
||||
|
||||
LOAD_REGION 0x0
|
||||
{
|
||||
CODE +0 0x80000
|
||||
{
|
||||
*.o (VECTORS, +First)
|
||||
* (InRoot$$$Sections)
|
||||
* (+RO-CODE)
|
||||
}
|
||||
|
||||
DATA 0x80000 NOCOMPRESS 0x100000
|
||||
{
|
||||
* (+RO-DATA)
|
||||
* (+RW,+ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_STACKHEAP 0x180000 ALIGN 64 EMPTY 0x00060000
|
||||
{}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,38 @@
|
||||
/**************************************************************************//**
|
||||
* @file mem_ARMCM7.h
|
||||
* @brief Memory base and size definitions (used in scatter file)
|
||||
* @version V1.1.0
|
||||
* @date 15. May 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __MEM_ARMCR52_H
|
||||
#define __MEM_ARMCR52_H
|
||||
|
||||
|
||||
|
||||
#define STACK_SIZE 0x00003000
|
||||
#define HEAP_SIZE 0x00100000
|
||||
|
||||
|
||||
|
||||
#endif /* __MEM_ARMCR52_H */
|
||||
@ -0,0 +1,38 @@
|
||||
/**************************************************************************//**
|
||||
* @file mem_ARMCM7.h
|
||||
* @brief Memory base and size definitions (used in scatter file)
|
||||
* @version V1.1.0
|
||||
* @date 15. May 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __MEM_ARMCM7_H
|
||||
#define __MEM_ARMCM7_H
|
||||
|
||||
|
||||
|
||||
#define STACK_SIZE 0x00003000
|
||||
#define HEAP_SIZE 0x00100000
|
||||
|
||||
|
||||
|
||||
#endif /* __MEM_ARMCM7_H */
|
||||
@ -0,0 +1,168 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM7.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM7 Device
|
||||
; * @version V5.4.0
|
||||
; * @date 12. December 2018
|
||||
; ******************************************************************************/
|
||||
;/*
|
||||
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
|
||||
#include "mem_ARMCM7.h"
|
||||
|
||||
;<h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;</h>
|
||||
|
||||
Stack_Size EQU STACK_SIZE
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
__stack_limit
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
;<h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;</h>
|
||||
|
||||
Heap_Size EQU HEAP_SIZE
|
||||
|
||||
IF Heap_Size != 0 ; Heap is provided
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
ENDIF
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; -14 NMI Handler
|
||||
DCD HardFault_Handler ; -13 Hard Fault Handler
|
||||
DCD MemManage_Handler ; -12 MPU Fault Handler
|
||||
DCD BusFault_Handler ; -11 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; -10 Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; -5 SVCall Handler
|
||||
DCD DebugMon_Handler ; -4 Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; -2 PendSV Handler
|
||||
DCD SysTick_Handler ; -1 SysTick Handler
|
||||
|
||||
; Interrupts
|
||||
DCD Interrupt0_Handler ; 0 Interrupt 0
|
||||
DCD Interrupt1_Handler ; 1 Interrupt 1
|
||||
DCD Interrupt2_Handler ; 2 Interrupt 2
|
||||
DCD Interrupt3_Handler ; 3 Interrupt 3
|
||||
DCD Interrupt4_Handler ; 4 Interrupt 4
|
||||
DCD Interrupt5_Handler ; 5 Interrupt 5
|
||||
DCD Interrupt6_Handler ; 6 Interrupt 6
|
||||
DCD Interrupt7_Handler ; 7 Interrupt 7
|
||||
DCD Interrupt8_Handler ; 8 Interrupt 8
|
||||
DCD Interrupt9_Handler ; 9 Interrupt 9
|
||||
|
||||
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
|
||||
__Vectors_End
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Macro to define default exception/interrupt handlers.
|
||||
; Default handler are weak symbols with an endless loop.
|
||||
; They can be overwritten by real handlers.
|
||||
MACRO
|
||||
Set_Default_Handler $Handler_Name
|
||||
$Handler_Name PROC
|
||||
EXPORT $Handler_Name [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MEND
|
||||
|
||||
|
||||
; Default exception/interrupt handler
|
||||
|
||||
Set_Default_Handler NMI_Handler
|
||||
Set_Default_Handler HardFault_Handler
|
||||
Set_Default_Handler MemManage_Handler
|
||||
Set_Default_Handler BusFault_Handler
|
||||
Set_Default_Handler UsageFault_Handler
|
||||
Set_Default_Handler SVC_Handler
|
||||
Set_Default_Handler DebugMon_Handler
|
||||
Set_Default_Handler PendSV_Handler
|
||||
Set_Default_Handler SysTick_Handler
|
||||
|
||||
Set_Default_Handler Interrupt0_Handler
|
||||
Set_Default_Handler Interrupt1_Handler
|
||||
Set_Default_Handler Interrupt2_Handler
|
||||
Set_Default_Handler Interrupt3_Handler
|
||||
Set_Default_Handler Interrupt4_Handler
|
||||
Set_Default_Handler Interrupt5_Handler
|
||||
Set_Default_Handler Interrupt6_Handler
|
||||
Set_Default_Handler Interrupt7_Handler
|
||||
Set_Default_Handler Interrupt8_Handler
|
||||
Set_Default_Handler Interrupt9_Handler
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User setup Stack & Heap
|
||||
|
||||
IF :LNOT::DEF:__MICROLIB
|
||||
IMPORT __use_two_region_memory
|
||||
ENDIF
|
||||
|
||||
EXPORT __stack_limit
|
||||
EXPORT __initial_sp
|
||||
IF Heap_Size != 0 ; Heap is provided
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,443 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCR8.c
|
||||
* @brief Unvalidated Startup File for a Cortex-R8 Device
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
// MPU region defines
|
||||
|
||||
// Protection Base Address Register
|
||||
#define Execute_Never 0b1 // Bit 0
|
||||
#define RW_Access 0b01 // AP[2:1]
|
||||
#define RO_Access 0b11
|
||||
#define Non_Shareable 0b00 // SH[1:0]
|
||||
#define Outer_Shareable 0x10
|
||||
#define Inner_Shareable 0b11
|
||||
|
||||
// Protection Limit Address Register
|
||||
#define ENable 0b1 // Bit 0
|
||||
#define AttrIndx0 0b000 // AttrIndx[2:0]
|
||||
#define AttrIndx1 0b001
|
||||
#define AttrIndx2 0b010
|
||||
#define AttrIndx3 0b011
|
||||
#define AttrIndx4 0b100
|
||||
#define AttrIndx5 0b101
|
||||
#define AttrIndx6 0b110
|
||||
#define AttrIndx7 0b111
|
||||
|
||||
//----------------------------------------------------------------
|
||||
|
||||
// Define some values
|
||||
#define Mode_USR 0x10
|
||||
#define Mode_FIQ 0x11
|
||||
#define Mode_IRQ 0x12
|
||||
#define Mode_SVC 0x13
|
||||
#define Mode_MON 0x16
|
||||
#define Mode_ABT 0x17
|
||||
#define Mode_UND 0x1B
|
||||
#define Mode_SYS 0x1F
|
||||
#define Mode_HYP 0x1A
|
||||
#define I_Bit 0x80 // when I bit is set, IRQ is disabled
|
||||
#define F_Bit 0x40 // when F bit is set, FIQ is disabled
|
||||
|
||||
|
||||
// Initial Setup & Entry point
|
||||
//----------------------------------------------------------------
|
||||
|
||||
.eabi_attribute Tag_ABI_align8_preserved,1
|
||||
.section VECTORS,"ax"
|
||||
.align 3
|
||||
|
||||
.global Reset_Handler
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
// Reset Handlers (EL1 and EL2)
|
||||
//----------------------------------------------------------------
|
||||
|
||||
EL2_Reset_Handler:
|
||||
|
||||
.global Image$$ARM_LIB_STACKHEAP$$ZI$$Limit
|
||||
LDR SP, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Disable MPU and caches
|
||||
//----------------------------------------------------------------
|
||||
|
||||
// Disable MPU and cache in case it was left enabled from an earlier run
|
||||
// This does not need to be done from a cold reset
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
|
||||
BIC r0, r0, #0x05 // Disable MPU (M bit) and data cache (C bit)
|
||||
BIC r0, r0, #0x1000 // Disable instruction cache (I bit)
|
||||
DSB // Ensure all previous loads/stores have completed
|
||||
MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
|
||||
ISB // Ensure subsequent insts execute wrt new MPU settings
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Cache invalidation. However Cortex-R52 provides CFG signals to
|
||||
// invalidate cache automatically out of reset (CFGL1CACHEINVDISx)
|
||||
//----------------------------------------------------------------
|
||||
|
||||
DSB // Complete all outstanding explicit memory operations
|
||||
|
||||
MOV r0, #0
|
||||
|
||||
MCR p15, 0, r0, c7, c5, 0 // Invalidate entire instruction cache
|
||||
|
||||
// Invalidate Data/Unified Caches
|
||||
|
||||
MRC p15, 1, r0, c0, c0, 1 // Read CLIDR
|
||||
ANDS r3, r0, #0x07000000 // Extract coherency level
|
||||
MOV r3, r3, LSR #23 // Total cache levels << 1
|
||||
BEQ Finished // If 0, no need to clean
|
||||
|
||||
MOV r10, #0 // R10 holds current cache level << 1
|
||||
Loop1: ADD r2, r10, r10, LSR #1 // R2 holds cache "Set" position
|
||||
MOV r1, r0, LSR r2 // Bottom 3 bits are the Cache-type for this level
|
||||
AND r1, r1, #7 // Isolate those lower 3 bits
|
||||
CMP r1, #2
|
||||
BLT Skip // No cache or only instruction cache at this level
|
||||
|
||||
MCR p15, 2, r10, c0, c0, 0 // Write the Cache Size selection register
|
||||
ISB // ISB to sync the change to the CacheSizeID reg
|
||||
MRC p15, 1, r1, c0, c0, 0 // Reads current Cache Size ID register
|
||||
AND r2, r1, #7 // Extract the line length field
|
||||
ADD r2, r2, #4 // Add 4 for the line length offset (log2 16 bytes)
|
||||
LDR r4, =0x3FF
|
||||
ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned)
|
||||
CLZ r5, r4 // R5 is the bit position of the way size increment
|
||||
LDR r7, =0x7FFF
|
||||
ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned)
|
||||
|
||||
Loop2: MOV r9, r4 // R9 working copy of the max way size (right aligned)
|
||||
|
||||
#ifdef __THUMB__
|
||||
Loop3: LSL r12, r9, r5
|
||||
ORR r11, r10, r12 // Factor in the Way number and cache number into R11
|
||||
LSL r12, r7, r2
|
||||
ORR r11, r11, r12 // Factor in the Set number
|
||||
#else
|
||||
Loop3: ORR r11, r10, r9, LSL r5 // Factor in the Way number and cache number into R11
|
||||
ORR r11, r11, r7, LSL r2 // Factor in the Set number
|
||||
#endif
|
||||
MCR p15, 0, r11, c7, c6, 2 // Invalidate by Set/Way
|
||||
SUBS r9, r9, #1 // Decrement the Way number
|
||||
BGE Loop3
|
||||
SUBS r7, r7, #1 // Decrement the Set number
|
||||
BGE Loop2
|
||||
Skip: ADD r10, r10, #2 // Increment the cache number
|
||||
CMP r3, r10
|
||||
BGT Loop1
|
||||
|
||||
Finished:
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// TCM Configuration
|
||||
//----------------------------------------------------------------
|
||||
|
||||
// Cortex-R52 optionally provides three Tightly-Coupled Memory (TCM) blocks (ATCM, BTCM and CTCM)
|
||||
// for fast access to code or data.
|
||||
|
||||
// The following illustrates basic TCM configuration, as the basis for exploration by the user
|
||||
|
||||
#ifdef TCM
|
||||
|
||||
MRC p15, 0, r0, c0, c0, 2 // Read TCM Type Register
|
||||
// r0 now contains TCM availability
|
||||
|
||||
MRC p15, 0, r0, c9, c1, 0 // Read ATCM Region Register
|
||||
// r0 now contains ATCM size in bits [5:2]
|
||||
LDR r0, =Image$$CODE$$Base // Set ATCM base address
|
||||
ORR r0, r0, #3 // Enable it
|
||||
MCR p15, 0, r0, c9, c1, 0 // Write ATCM Region Register
|
||||
|
||||
MRC p15, 0, r0, c9, c1, 1 // Read BTCM Region Register
|
||||
// r0 now contains BTCM size in bits [5:2]
|
||||
LDR r0, =Image$$DATA$$Base // Set BTCM base address
|
||||
ORR r0, r0, #3 // Enable it
|
||||
MCR p15, 0, r0, c9, c1, 1 // Write BTCM Region Register
|
||||
|
||||
MRC p15, 0, r0, c9, c1, 2 // Read CTCM Region Register
|
||||
// r0 now contains CTCM size in bits [5:2]
|
||||
LDR r0, =Image$$CTCM$$Base // Set CTCM base address
|
||||
ORR r0, r0, #1 // Enable it
|
||||
MCR p15, 0, r0, c9, c1, 2 // Write CTCM Region Register
|
||||
|
||||
#endif
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// MPU Configuration
|
||||
//----------------------------------------------------------------
|
||||
|
||||
// Notes:
|
||||
// * Regions apply to both instruction and data accesses.
|
||||
// * Each region base address must be a multiple of its size
|
||||
// * Any address range not covered by an enabled region will abort
|
||||
// * The region at 0x0 over the Vector table is needed to support semihosting
|
||||
|
||||
// Region 0: Code Base = See scatter file Limit = Based on usage Normal Non-shared Read-only Executable
|
||||
// Region 1: Data Base = See scatter file Limit = Based on usage Normal Non-shared Full access Not Executable
|
||||
// Region 2: Stack/Heap Base = See scatter file Limit = Based on usage Normal Non-shared Full access Not Executable
|
||||
// Region 3: Peripherals Base = 0xB0000000 Limit = 0xBFFFFFC0 Device Full access Not Executable
|
||||
// Region 4: ATCM Base = Configurable Limit = Based on usage Normal Non-shared Full access Executable
|
||||
// Region 5: BTCM Base = Configurable Limit = Based on usage Normal Non-shared Full access Executable
|
||||
// Region 6: CTCM Base = Configurable Limit = Based on usage Normal Non-shared Full access Executable
|
||||
|
||||
LDR r0, =64
|
||||
|
||||
// Region 0 - Code
|
||||
REG0:
|
||||
LDR r1, =Image$$CODE$$Base
|
||||
LDR r2, =((Non_Shareable<<3) | (RO_Access<<1))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c8, 0 // write PRBAR0
|
||||
LDR r1, =Image$$CODE$$Limit
|
||||
ADD r1, r1, #63
|
||||
BFC r1, #0, #6 // align Limit to 64bytes
|
||||
LDR r2, =((AttrIndx0<<1) | (ENable))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c8, 1 // write PRLAR0
|
||||
|
||||
// Region 1 - Data
|
||||
REG1:
|
||||
LDR r1, =Image$$DATA$$Base
|
||||
LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c8, 4 // write PRBAR1
|
||||
LDR r1, =Image$$DATA$$ZI$$Limit
|
||||
ADD r1, r1, #63
|
||||
BFC r1, #0, #6 // align Limit to 64bytes
|
||||
LDR r2, =((AttrIndx0<<1) | (ENable))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c8, 5 // write PRLAR1
|
||||
|
||||
// Region 2 - Stack-Heap
|
||||
REG2:
|
||||
LDR r1, =Image$$ARM_LIB_STACKHEAP$$Base
|
||||
LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c9, 0 // write PRBAR2
|
||||
LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit
|
||||
ADD r1, r1, #63
|
||||
BFC r1, #0, #6 // align Limit to 64bytes
|
||||
LDR r2, =((AttrIndx0<<1) | (ENable))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c9, 1 // write PRLAR2
|
||||
|
||||
// Region 3 - Peripherals
|
||||
REG3:
|
||||
LDR r1, =0xAA000000
|
||||
LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c9, 4 // write PRBAR3
|
||||
LDR r1, =0xBFFFFFC0
|
||||
ADD r1, r1, #63
|
||||
BFC r1, #0, #6 // align Limit to 64bytes
|
||||
LDR r2, =((AttrIndx0<<1) | (ENable))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c9, 5 // write PRLAR3
|
||||
|
||||
#ifdef TCM
|
||||
// Region 4 - ATCM
|
||||
LDR r1, =Image$$ATCM$$Base
|
||||
LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c10, 0 // write PRBAR4
|
||||
LDR r1, =Image$$ATCM$$Limit
|
||||
ADD r1, r1, #63
|
||||
BFC r1, #0, #6 // align Limit to 64bytes
|
||||
LDR r2, =((AttrIndx1<<1) | (ENable))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c10, 1 // write PRLAR4
|
||||
|
||||
// Region 5 - BTCM
|
||||
LDR r1, =Image$$BTCM$$Base
|
||||
LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c10, 4 // write PRBAR5
|
||||
LDR r1, =Image$$BTCM$$Limit
|
||||
ADD r1, r1, #63
|
||||
BFC r1, #0, #6 // align Limit to 64bytes
|
||||
LDR r2, =((AttrIndx0<<1) | (ENable))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c10, 5 // write PRLAR5
|
||||
|
||||
// Region 6 - CTCM
|
||||
LDR r1, =Image$$CTCM$$Base
|
||||
LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c11, 0 // write PRBAR6
|
||||
LDR r1, =Image$$CTCM$$Limit
|
||||
ADD r1, r1, #63
|
||||
BFC r1, #0, #6 // align Limit to 64bytes
|
||||
LDR r2, =((AttrIndx0<<1) | (ENable))
|
||||
ORR r1, r1, r2
|
||||
MCR p15, 0, r1, c6, c11, 1 // write PRLAR6
|
||||
#endif
|
||||
|
||||
|
||||
other_mems_en:
|
||||
// Enable PERIPHREGIONR (LLPP)
|
||||
mrc p15, 0, r1, c15, c0, 0 // PERIPHREGIONR
|
||||
orr r1, r1, #(0x1 << 1) // Enable PERIPHREGIONR EL2
|
||||
orr r1, r1, #(0x1) // Enable PERIPHREGIONR EL10
|
||||
mcr p15, 0, r1, c15, c0, 0 // PERIPHREGIONR
|
||||
|
||||
//#ifdef __ARM_FP
|
||||
//----------------------------------------------------------------
|
||||
// Enable access to VFP by enabling access to Coprocessors 10 and 11.
|
||||
// Enables Full Access i.e. in both privileged and non privileged modes
|
||||
//----------------------------------------------------------------
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR)
|
||||
ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11
|
||||
MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR)
|
||||
ISB
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Switch on the VFP hardware
|
||||
//----------------------------------------------------------------
|
||||
|
||||
MOV r0, #0x40000000
|
||||
VMSR FPEXC, r0 // Write FPEXC register, EN bit set
|
||||
//#endif
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Enable MPU and branch to C library init
|
||||
// Leaving the caches disabled until after scatter loading.
|
||||
//----------------------------------------------------------------
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
|
||||
ORR r0, r0, #0x01 // Set M bit to enable MPU
|
||||
DSB // Ensure all previous loads/stores have completed
|
||||
MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
|
||||
ISB // Ensure subsequent insts execute wrt new MPU settings
|
||||
|
||||
//Check which CPU I am
|
||||
MRC p15, 0, r0, c0, c0, 5 // Read MPIDR
|
||||
ANDS r0, r0, 0xF
|
||||
BEQ cpu0 // If CPU0 then initialise C runtime
|
||||
CMP r0, #1
|
||||
BEQ loop_wfi // If CPU1 then jump to loop_wfi
|
||||
CMP r0, #2
|
||||
BEQ loop_wfi // If CPU2 then jump to loop_wfi
|
||||
CMP r0, #3
|
||||
BEQ loop_wfi // If CPU3 then jump to loop_wfi
|
||||
error:
|
||||
B error // else.. something is wrong
|
||||
|
||||
loop_wfi:
|
||||
DSB SY // Clear all pending data accesses
|
||||
WFI // Go to sleep
|
||||
B loop_wfi
|
||||
|
||||
|
||||
cpu0:
|
||||
|
||||
// Branch to __main
|
||||
//------------------------
|
||||
.global __main
|
||||
B __main
|
||||
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Global Enable for Instruction and Data Caching
|
||||
//----------------------------------------------------------------
|
||||
.global enable_caches
|
||||
.type enable_caches, "function"
|
||||
.cfi_startproc
|
||||
enable_caches:
|
||||
|
||||
MRC p15, 4, r0, c1, c0, 0 // read System Control Register
|
||||
ORR r0, r0, #(0x1 << 12) // Set I bit 12 to enable I Cache
|
||||
ORR r0, r0, #(0x1 << 2) // Set C bit 2 to enable D Cache
|
||||
MCR p15, 4, r0, c1, c0, 0 // write System Control Register
|
||||
ISB
|
||||
|
||||
BX lr
|
||||
.cfi_endproc
|
||||
|
||||
.size enable_caches, . - enable_caches
|
||||
|
||||
|
||||
// Exception Vector Table & Handlers
|
||||
//----------------------------------------------------------------
|
||||
|
||||
EL2_Vectors:
|
||||
|
||||
LDR PC, EL2_Reset_Addr
|
||||
LDR PC, EL2_Undefined_Addr
|
||||
LDR PC, EL2_HVC_Addr
|
||||
LDR PC, EL2_Prefetch_Addr
|
||||
LDR PC, EL2_Abort_Addr
|
||||
LDR PC, EL2_HypModeEntry_Addr
|
||||
LDR PC, EL2_IRQ_Addr
|
||||
LDR PC, EL2_FIQ_Addr
|
||||
|
||||
EL2_Reset_Addr: .word EL2_Reset_Handler
|
||||
EL2_Undefined_Addr: .word EL2_Undefined_Handler
|
||||
EL2_HVC_Addr: .word EL2_HVC_Handler
|
||||
EL2_Prefetch_Addr: .word EL2_Prefetch_Handler
|
||||
EL2_Abort_Addr: .word EL2_Abort_Handler
|
||||
EL2_HypModeEntry_Addr: .word EL2_HypModeEntry_Handler
|
||||
EL2_IRQ_Addr: .word EL2_IRQ_Handler
|
||||
EL2_FIQ_Addr: .word EL2_FIQ_Handler
|
||||
|
||||
EL2_Undefined_Handler: B EL2_Undefined_Handler
|
||||
EL2_HVC_Handler: B EL2_HVC_Handler
|
||||
EL2_Prefetch_Handler: B EL2_Prefetch_Handler
|
||||
EL2_Abort_Handler: B EL2_Abort_Handler
|
||||
EL2_HypModeEntry_Handler: B EL2_HypModeEntry_Handler
|
||||
EL2_IRQ_Handler: B EL2_IRQ_Handler
|
||||
EL2_FIQ_Handler: B EL2_FIQ_Handler
|
||||
|
||||
|
||||
EL1_Vectors:
|
||||
|
||||
LDR PC, EL1_Reset_Addr
|
||||
LDR PC, EL1_Undefined_Addr
|
||||
LDR PC, EL1_SVC_Addr
|
||||
LDR PC, EL1_Prefetch_Addr
|
||||
LDR PC, EL1_Abort_Addr
|
||||
LDR PC, EL1_Reserved
|
||||
LDR PC, EL1_IRQ_Addr
|
||||
LDR PC, EL1_FIQ_Addr
|
||||
|
||||
EL1_Reset_Addr: .word EL1_Reset_Handler
|
||||
EL1_Undefined_Addr: .word EL1_Undefined_Handler
|
||||
EL1_SVC_Addr: .word EL1_SVC_Handler
|
||||
EL1_Prefetch_Addr: .word EL1_Prefetch_Handler
|
||||
EL1_Abort_Addr: .word EL1_Abort_Handler
|
||||
EL1_Reserved_Addr: .word EL1_Reserved
|
||||
EL1_IRQ_Addr: .word EL1_IRQ_Handler
|
||||
EL1_FIQ_Addr: .word EL1_FIQ_Handler
|
||||
|
||||
EL1_Reset_Handler: B EL1_Reset_Handler
|
||||
EL1_Undefined_Handler: B EL1_Undefined_Handler
|
||||
EL1_SVC_Handler: B EL1_SVC_Handler
|
||||
EL1_Prefetch_Handler: B EL1_Prefetch_Handler
|
||||
EL1_Abort_Handler: B EL1_Abort_Handler
|
||||
EL1_Reserved: B EL1_Reserved
|
||||
EL1_IRQ_Handler: B EL1_IRQ_Handler
|
||||
EL1_FIQ_Handler: B EL1_FIQ_Handler
|
||||
@ -0,0 +1,155 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCM7.c
|
||||
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
|
||||
* @version V2.0.3
|
||||
* @date 31. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined (ARMCR52)
|
||||
#include "ARMC52.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler Function Prototype
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef void( *pFunc )( void );
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __INITIAL_SP;
|
||||
|
||||
extern __NO_RETURN void __PROGRAM_START(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler (void);
|
||||
void Default_Handler(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak));
|
||||
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpedantic"
|
||||
#endif
|
||||
|
||||
extern const pFunc __VECTOR_TABLE[240];
|
||||
const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
Reset_Handler, /* Reset Handler */
|
||||
NMI_Handler, /* -14 NMI Handler */
|
||||
HardFault_Handler, /* -13 Hard Fault Handler */
|
||||
MemManage_Handler, /* -12 MPU Fault Handler */
|
||||
BusFault_Handler, /* -11 Bus Fault Handler */
|
||||
UsageFault_Handler, /* -10 Usage Fault Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
SVC_Handler, /* -5 SVCall Handler */
|
||||
DebugMon_Handler, /* -4 Debug Monitor Handler */
|
||||
0, /* Reserved */
|
||||
PendSV_Handler, /* -2 PendSV Handler */
|
||||
SysTick_Handler, /* -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
Interrupt0_Handler, /* 0 Interrupt 0 */
|
||||
Interrupt1_Handler, /* 1 Interrupt 1 */
|
||||
Interrupt2_Handler, /* 2 Interrupt 2 */
|
||||
Interrupt3_Handler, /* 3 Interrupt 3 */
|
||||
Interrupt4_Handler, /* 4 Interrupt 4 */
|
||||
Interrupt5_Handler, /* 5 Interrupt 5 */
|
||||
Interrupt6_Handler, /* 6 Interrupt 6 */
|
||||
Interrupt7_Handler, /* 7 Interrupt 7 */
|
||||
Interrupt8_Handler, /* 8 Interrupt 8 */
|
||||
Interrupt9_Handler /* 9 Interrupt 9 */
|
||||
/* Interrupts 10 .. 223 are left out */
|
||||
};
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler(void)
|
||||
{
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wmissing-noreturn"
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Hard Fault Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic pop
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,165 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCM7.c
|
||||
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
|
||||
* @version V2.0.3
|
||||
* @date 31. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#if defined (ARMCM7)
|
||||
#include "ARMCM7.h"
|
||||
#elif defined (ARMCM7_SP)
|
||||
#include "ARMCM7_SP.h"
|
||||
#elif defined (ARMCM7_DP)
|
||||
#include "ARMCM7_DP.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler Function Prototype
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef void( *pFunc )( void );
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External References
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t __INITIAL_SP;
|
||||
|
||||
extern __NO_RETURN void __PROGRAM_START(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler (void);
|
||||
void Default_Handler(void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Exceptions */
|
||||
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void HardFault_Handler (void) __attribute__ ((weak));
|
||||
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector table
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpedantic"
|
||||
#endif
|
||||
|
||||
extern const pFunc __VECTOR_TABLE[240];
|
||||
const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
|
||||
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
|
||||
Reset_Handler, /* Reset Handler */
|
||||
NMI_Handler, /* -14 NMI Handler */
|
||||
HardFault_Handler, /* -13 Hard Fault Handler */
|
||||
MemManage_Handler, /* -12 MPU Fault Handler */
|
||||
BusFault_Handler, /* -11 Bus Fault Handler */
|
||||
UsageFault_Handler, /* -10 Usage Fault Handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
SVC_Handler, /* -5 SVCall Handler */
|
||||
DebugMon_Handler, /* -4 Debug Monitor Handler */
|
||||
0, /* Reserved */
|
||||
PendSV_Handler, /* -2 PendSV Handler */
|
||||
SysTick_Handler, /* -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
Interrupt0_Handler, /* 0 Interrupt 0 */
|
||||
Interrupt1_Handler, /* 1 Interrupt 1 */
|
||||
Interrupt2_Handler, /* 2 Interrupt 2 */
|
||||
Interrupt3_Handler, /* 3 Interrupt 3 */
|
||||
Interrupt4_Handler, /* 4 Interrupt 4 */
|
||||
Interrupt5_Handler, /* 5 Interrupt 5 */
|
||||
Interrupt6_Handler, /* 6 Interrupt 6 */
|
||||
Interrupt7_Handler, /* 7 Interrupt 7 */
|
||||
Interrupt8_Handler, /* 8 Interrupt 8 */
|
||||
Interrupt9_Handler /* 9 Interrupt 9 */
|
||||
/* Interrupts 10 .. 223 are left out */
|
||||
};
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#define SERIAL_BASE_ADDRESS (0xA8000000ul)
|
||||
|
||||
#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
__NO_RETURN void Reset_Handler(void)
|
||||
{
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
|
||||
|
||||
__PROGRAM_START();
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Hard Fault Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,36 @@
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
char * _sbrk(int incr);
|
||||
|
||||
void __malloc_lock() ;
|
||||
void __malloc_unlock();
|
||||
|
||||
char __end__, __HeapLimit; // make sure to define these symbols in linker command file
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
static int totalBytesProvidedBySBRK = 0;
|
||||
|
||||
//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file).
|
||||
char * sbrk(int incr) {
|
||||
static char *currentHeapEnd = &__end__;
|
||||
char *previousHeapEnd = currentHeapEnd;
|
||||
if (currentHeapEnd + incr > &__HeapLimit) {
|
||||
return (char *)-1; // the malloc-family routine that called sbrk will return 0
|
||||
}
|
||||
currentHeapEnd += incr;
|
||||
|
||||
totalBytesProvidedBySBRK += incr;
|
||||
|
||||
return (char *) previousHeapEnd;
|
||||
}
|
||||
//! Synonym for sbrk.
|
||||
char * _sbrk(int incr) { return sbrk(incr); };
|
||||
|
||||
void __malloc_lock() { };
|
||||
void __malloc_unlock() { };
|
||||
@ -0,0 +1,198 @@
|
||||
/**************************************************************************//**
|
||||
* @file mmu_ARMCA32.c
|
||||
* @brief MMU Configuration for Arm Cortex-A32 Device Series
|
||||
* @version V1.2.0
|
||||
* @date 15. May 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
|
||||
|
||||
Memory Type
|
||||
0xffffffff |--------------------------| ------------
|
||||
| FLAG SYNC | Device Memory
|
||||
0xfffff000 |--------------------------| ------------
|
||||
| Fault | Fault
|
||||
0xfff00000 |--------------------------| ------------
|
||||
| | Normal
|
||||
| |
|
||||
| Daughterboard |
|
||||
| memory |
|
||||
| |
|
||||
0x80505000 |--------------------------| ------------
|
||||
|TTB (L2 Sync Flags ) 4k | Normal
|
||||
0x80504C00 |--------------------------| ------------
|
||||
|TTB (L2 Peripherals-B) 16k| Normal
|
||||
0x80504800 |--------------------------| ------------
|
||||
|TTB (L2 Peripherals-A) 16k| Normal
|
||||
0x80504400 |--------------------------| ------------
|
||||
|TTB (L2 Priv Periphs) 4k | Normal
|
||||
0x80504000 |--------------------------| ------------
|
||||
| TTB (L1 Descriptors) | Normal
|
||||
0x80500000 |--------------------------| ------------
|
||||
| Stack | Normal
|
||||
|--------------------------| ------------
|
||||
| Heap | Normal
|
||||
0x80400000 |--------------------------| ------------
|
||||
| ZI Data | Normal
|
||||
0x80300000 |--------------------------| ------------
|
||||
| RW Data | Normal
|
||||
0x80200000 |--------------------------| ------------
|
||||
| RO Data | Normal
|
||||
|--------------------------| ------------
|
||||
| RO Code | USH Normal
|
||||
0x80000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| HSB AXI buses |
|
||||
0x40000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| test chips peripherals |
|
||||
0x2c002000 |--------------------------| ------------
|
||||
| Private Address | Device Memory
|
||||
0x2c000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| test chips peripherals |
|
||||
0x20000000 |--------------------------| ------------
|
||||
| Peripherals | Device Memory RW/RO
|
||||
| | & Fault
|
||||
0x00000000 |--------------------------|
|
||||
*/
|
||||
|
||||
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
|
||||
// Write-Through support *not* available
|
||||
// Write-Back support available.
|
||||
// Read allocation support available.
|
||||
// Write allocation support available.
|
||||
|
||||
//Note: You should use the Shareable attribute carefully.
|
||||
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
|
||||
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
|
||||
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
|
||||
|
||||
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
|
||||
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
|
||||
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
|
||||
|
||||
|
||||
//Following MMU configuration is expected
|
||||
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
|
||||
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
|
||||
//Domain 0 is always the Client domain
|
||||
//Descriptors should place all memory in domain 0
|
||||
|
||||
#include "ARMCR52.h"
|
||||
#include "mem_ARMCR52.h"
|
||||
|
||||
#if 0
|
||||
|
||||
// TTB base address
|
||||
#define TTB_BASE ((uint32_t*)__TTB_BASE)
|
||||
|
||||
// L2 table pointers
|
||||
//----------------------------------------
|
||||
#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
|
||||
// into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
|
||||
// The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
|
||||
|
||||
#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
|
||||
#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
|
||||
#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
|
||||
#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
|
||||
|
||||
//--------------------- PERIPHERALS -------------------
|
||||
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
|
||||
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
|
||||
|
||||
//--------------------- SYNC FLAGS --------------------
|
||||
#define FLAG_SYNC 0xFFFFF000
|
||||
#define F_SYNC_BASE 0xFFF00000 //1M aligned
|
||||
|
||||
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
|
||||
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
|
||||
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
|
||||
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
|
||||
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
|
||||
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
|
||||
|
||||
/* Define global descriptors */
|
||||
static uint32_t Page_L1_4k = 0x0; //generic
|
||||
static uint32_t Page_L1_64k = 0x0; //generic
|
||||
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
|
||||
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
|
||||
|
||||
void MMU_CreateTranslationTable(void)
|
||||
{
|
||||
mmu_region_attributes_Type region;
|
||||
|
||||
//Create 4GB of faulting entries
|
||||
MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
|
||||
|
||||
/*
|
||||
* Generate descriptors. Refer to core_ca.h to get information about attributes
|
||||
*
|
||||
*/
|
||||
//Create descriptors for Vectors, RO, RW, ZI sections
|
||||
section_normal(Sect_Normal, region);
|
||||
section_normal_cod(Sect_Normal_Cod, region);
|
||||
section_normal_ro(Sect_Normal_RO, region);
|
||||
section_normal_rw(Sect_Normal_RW, region);
|
||||
//Create descriptors for peripherals
|
||||
section_device_ro(Sect_Device_RO, region);
|
||||
section_device_rw(Sect_Device_RW, region);
|
||||
//Create descriptors for 64k pages
|
||||
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
|
||||
//Create descriptors for 4k pages
|
||||
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
|
||||
|
||||
|
||||
/*
|
||||
* Define MMU flat-map regions and attributes
|
||||
*
|
||||
*/
|
||||
|
||||
//Define Image
|
||||
MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
|
||||
MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
|
||||
|
||||
//--------------------- PERIPHERALS -------------------
|
||||
MMU_TTSection (TTB_BASE, VE_A32_PERIPH , 64, Sect_Device_RW); // 64MB NOR
|
||||
|
||||
/* Set location of level 1 page table
|
||||
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
|
||||
; 13:7 - 0x0
|
||||
; 6 - IRGN[0] 0x1 (Inner WB WA)
|
||||
; 5 - NOS 0x0 (Non-shared)
|
||||
; 4:3 - RGN 0x01 (Outer WB WA)
|
||||
; 2 - IMP 0x0 (Implementation Defined)
|
||||
; 1 - S 0x0 (Non-shared)
|
||||
; 0 - IRGN[1] 0x0 (Inner WB WA) */
|
||||
__set_TTBR0(__TTB_BASE | 0x48);
|
||||
__ISB();
|
||||
|
||||
/* Set up domain access control register
|
||||
; We set domain 0 to Client and all other domains to No Access.
|
||||
; All translation table entries specify domain 0 */
|
||||
__set_DACR(1);
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,591 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM7.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM7 Device
|
||||
* @version V5.3.1
|
||||
* @date 09. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <assert.h>
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include <rt_sys.h>
|
||||
#else
|
||||
#define GCCCOMPILER
|
||||
struct __FILE {int handle;};
|
||||
FILE __stdout;
|
||||
FILE __stdin;
|
||||
FILE __stderr;
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (ARMCR52)
|
||||
#include "ARMCR52.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (50000000UL) /* Oscillator frequency */
|
||||
|
||||
#define SYSTEM_CLOCK (XTAL / 2U)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Externals
|
||||
*----------------------------------------------------------------------------*/
|
||||
//#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
// extern uint32_t __VECTOR_TABLE;
|
||||
//#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Peripheral declaration ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
#define SERIAL_BASE_ADDRESS (0xb0000000ul)
|
||||
|
||||
#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS)
|
||||
|
||||
#define SOFTWARE_MARK *((volatile unsigned *) (SERIAL_BASE_ADDRESS+4))
|
||||
|
||||
void start_ipss_measurement()
|
||||
{
|
||||
SOFTWARE_MARK = 1;
|
||||
}
|
||||
|
||||
void stop_ipss_measurement()
|
||||
{
|
||||
SOFTWARE_MARK = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int stdout_putchar(char txchar)
|
||||
{
|
||||
SERIAL_DATA = txchar;
|
||||
return(txchar);
|
||||
}
|
||||
|
||||
int stderr_putchar(char txchar)
|
||||
{
|
||||
return stdout_putchar(txchar);
|
||||
}
|
||||
|
||||
void ttywrch (int ch)
|
||||
{
|
||||
stdout_putchar(ch);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System initialization function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if 0
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
SCB->VTOR = (uint32_t) &__VECTOR_TABLE;
|
||||
#endif
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
|
||||
(3U << 11U*2U) ); /* enable CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if __IS_COMPILER_ARM_COMPILER_6__
|
||||
__asm(".global __use_no_semihosting\n\t");
|
||||
# ifndef __MICROLIB
|
||||
__asm(".global __ARM_use_no_argv\n\t");
|
||||
# endif
|
||||
#endif
|
||||
|
||||
extern void $Super$$main(void);
|
||||
extern void enable_caches();
|
||||
|
||||
void simulation_exit()
|
||||
{
|
||||
stdout_putchar(4);
|
||||
}
|
||||
|
||||
void $Sub$$main(void)
|
||||
{
|
||||
enable_caches(); // Initalize caches right away. Implmentation varies by core
|
||||
|
||||
$Super$$main(); // calls original main()
|
||||
|
||||
simulation_exit(); // Stops simulation by writing a char of '4' to the trickbox
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Writes the character specified by c (converted to an unsigned char) to
|
||||
the output stream pointed to by stream, at the position indicated by the
|
||||
associated file position indicator (if defined), and advances the
|
||||
indicator appropriately. If the file position indicator is not defined,
|
||||
the character is appended to the output stream.
|
||||
|
||||
\param[in] c Character
|
||||
\param[in] stream Stream handle
|
||||
|
||||
\return The character written. If a write error occurs, the error
|
||||
indicator is set and fputc returns EOF.
|
||||
*/
|
||||
__attribute__((weak))
|
||||
int fputc (int c, FILE * stream)
|
||||
{
|
||||
if (stream == &__stdout) {
|
||||
return (stdout_putchar(c));
|
||||
}
|
||||
|
||||
if (stream == &__stderr) {
|
||||
return (stderr_putchar(c));
|
||||
}
|
||||
|
||||
return (-1);
|
||||
}
|
||||
|
||||
#ifndef GCCCOMPILER
|
||||
/* IO device file handles. */
|
||||
#define FH_STDIN 0x8001
|
||||
#define FH_STDOUT 0x8002
|
||||
#define FH_STDERR 0x8003
|
||||
|
||||
const char __stdin_name[] = ":STDIN";
|
||||
const char __stdout_name[] = ":STDOUT";
|
||||
const char __stderr_name[] = ":STDERR";
|
||||
|
||||
#define RETARGET_SYS 1
|
||||
#define RTE_Compiler_IO_STDOUT 1
|
||||
#define RTE_Compiler_IO_STDERR 1
|
||||
/**
|
||||
Defined in rt_sys.h, this function opens a file.
|
||||
|
||||
The _sys_open() function is required by fopen() and freopen(). These
|
||||
functions in turn are required if any file input/output function is to
|
||||
be used.
|
||||
The openmode parameter is a bitmap whose bits mostly correspond directly to
|
||||
the ISO mode specification. Target-dependent extensions are possible, but
|
||||
freopen() must also be extended.
|
||||
|
||||
\param[in] name File name
|
||||
\param[in] openmode Mode specification bitmap
|
||||
|
||||
\return The return value is ?1 if an error occurs.
|
||||
*/
|
||||
#ifdef RETARGET_SYS
|
||||
__attribute__((weak))
|
||||
FILEHANDLE _sys_open (const char *name, int openmode) {
|
||||
#if (!defined(RTE_Compiler_IO_File))
|
||||
(void)openmode;
|
||||
#endif
|
||||
|
||||
if (name == NULL) {
|
||||
return (-1);
|
||||
}
|
||||
|
||||
if (name[0] == ':') {
|
||||
if (strcmp(name, ":STDIN") == 0) {
|
||||
return (FH_STDIN);
|
||||
}
|
||||
if (strcmp(name, ":STDOUT") == 0) {
|
||||
return (FH_STDOUT);
|
||||
}
|
||||
if (strcmp(name, ":STDERR") == 0) {
|
||||
return (FH_STDERR);
|
||||
}
|
||||
return (-1);
|
||||
}
|
||||
|
||||
#ifdef RTE_Compiler_IO_File
|
||||
#ifdef RTE_Compiler_IO_File_FS
|
||||
return (__sys_open(name, openmode));
|
||||
#endif
|
||||
#else
|
||||
return (-1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
Defined in rt_sys.h, this function closes a file previously opened
|
||||
with _sys_open().
|
||||
|
||||
This function must be defined if any input/output function is to be used.
|
||||
|
||||
\param[in] fh File handle
|
||||
|
||||
\return The return value is 0 if successful. A nonzero value indicates
|
||||
an error.
|
||||
*/
|
||||
#ifdef RETARGET_SYS
|
||||
__attribute__((weak))
|
||||
int _sys_close (FILEHANDLE fh) {
|
||||
|
||||
switch (fh) {
|
||||
case FH_STDIN:
|
||||
return (0);
|
||||
case FH_STDOUT:
|
||||
return (0);
|
||||
case FH_STDERR:
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef RTE_Compiler_IO_File
|
||||
#ifdef RTE_Compiler_IO_File_FS
|
||||
return (__sys_close(fh));
|
||||
#endif
|
||||
#else
|
||||
return (-1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
Defined in rt_sys.h, this function writes the contents of a buffer to a file
|
||||
previously opened with _sys_open().
|
||||
|
||||
\note The mode parameter is here for historical reasons. It contains
|
||||
nothing useful and must be ignored.
|
||||
|
||||
\param[in] fh File handle
|
||||
\param[in] buf Data buffer
|
||||
\param[in] len Data length
|
||||
\param[in] mode Ignore this parameter
|
||||
|
||||
\return The return value is either:
|
||||
- a positive number representing the number of characters not
|
||||
written (so any nonzero return value denotes a failure of
|
||||
some sort)
|
||||
- a negative number indicating an error.
|
||||
*/
|
||||
#ifdef RETARGET_SYS
|
||||
__attribute__((weak))
|
||||
int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) {
|
||||
#if (defined(RTE_Compiler_IO_STDOUT) || defined(RTE_Compiler_IO_STDERR))
|
||||
int ch;
|
||||
#elif (!defined(RTE_Compiler_IO_File))
|
||||
(void)buf;
|
||||
(void)len;
|
||||
#endif
|
||||
(void)mode;
|
||||
|
||||
switch (fh) {
|
||||
case FH_STDIN:
|
||||
return (-1);
|
||||
case FH_STDOUT:
|
||||
#ifdef RTE_Compiler_IO_STDOUT
|
||||
for (; len; len--) {
|
||||
ch = *buf++;
|
||||
|
||||
stdout_putchar(ch);
|
||||
}
|
||||
#endif
|
||||
return (0);
|
||||
case FH_STDERR:
|
||||
#ifdef RTE_Compiler_IO_STDERR
|
||||
for (; len; len--) {
|
||||
ch = *buf++;
|
||||
|
||||
stderr_putchar(ch);
|
||||
}
|
||||
#endif
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef RTE_Compiler_IO_File
|
||||
#ifdef RTE_Compiler_IO_File_FS
|
||||
return (__sys_write(fh, buf, len));
|
||||
#endif
|
||||
#else
|
||||
return (-1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
Defined in rt_sys.h, this function reads the contents of a file into a buffer.
|
||||
|
||||
Reading up to and including the last byte of data does not turn on the EOF
|
||||
indicator. The EOF indicator is only reached when an attempt is made to read
|
||||
beyond the last byte of data. The target-independent code is capable of
|
||||
handling:
|
||||
- the EOF indicator being returned in the same read as the remaining bytes
|
||||
of data that precede the EOF
|
||||
- the EOF indicator being returned on its own after the remaining bytes of
|
||||
data have been returned in a previous read.
|
||||
|
||||
\note The mode parameter is here for historical reasons. It contains
|
||||
nothing useful and must be ignored.
|
||||
|
||||
\param[in] fh File handle
|
||||
\param[in] buf Data buffer
|
||||
\param[in] len Data length
|
||||
\param[in] mode Ignore this parameter
|
||||
|
||||
\return The return value is one of the following:
|
||||
- The number of bytes not read (that is, len - result number of
|
||||
bytes were read).
|
||||
- An error indication.
|
||||
- An EOF indicator. The EOF indication involves the setting of
|
||||
0x80000000 in the normal result.
|
||||
*/
|
||||
#ifdef RETARGET_SYS
|
||||
__attribute__((weak))
|
||||
int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) {
|
||||
#ifdef RTE_Compiler_IO_STDIN
|
||||
int ch;
|
||||
#elif (!defined(RTE_Compiler_IO_File))
|
||||
(void)buf;
|
||||
(void)len;
|
||||
#endif
|
||||
(void)mode;
|
||||
|
||||
switch (fh) {
|
||||
case FH_STDIN:
|
||||
#ifdef RTE_Compiler_IO_STDIN
|
||||
ch = stdin_getchar();
|
||||
if (ch < 0) {
|
||||
return ((int)(len | 0x80000000U));
|
||||
}
|
||||
*buf++ = (uint8_t)ch;
|
||||
#if (STDIN_ECHO != 0)
|
||||
stdout_putchar(ch);
|
||||
#endif
|
||||
len--;
|
||||
return ((int)(len));
|
||||
#else
|
||||
return ((int)(len | 0x80000000U));
|
||||
#endif
|
||||
case FH_STDOUT:
|
||||
return (-1);
|
||||
case FH_STDERR:
|
||||
return (-1);
|
||||
}
|
||||
|
||||
#ifdef RTE_Compiler_IO_File
|
||||
#ifdef RTE_Compiler_IO_File_FS
|
||||
return (__sys_read(fh, buf, len));
|
||||
#endif
|
||||
#else
|
||||
return (-1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
Defined in rt_sys.h, this function determines if a file handle identifies
|
||||
a terminal.
|
||||
|
||||
When a file is connected to a terminal device, this function is used to
|
||||
provide unbuffered behavior by default (in the absence of a call to
|
||||
set(v)buf) and to prohibit seeking.
|
||||
|
||||
\param[in] fh File handle
|
||||
|
||||
\return The return value is one of the following values:
|
||||
- 0: There is no interactive device.
|
||||
- 1: There is an interactive device.
|
||||
- other: An error occurred.
|
||||
*/
|
||||
#ifdef RETARGET_SYS
|
||||
__attribute__((weak))
|
||||
int _sys_istty (FILEHANDLE fh) {
|
||||
|
||||
switch (fh) {
|
||||
case FH_STDIN:
|
||||
return (1);
|
||||
case FH_STDOUT:
|
||||
return (1);
|
||||
case FH_STDERR:
|
||||
return (1);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
Defined in rt_sys.h, this function puts the file pointer at offset pos from
|
||||
the beginning of the file.
|
||||
|
||||
This function sets the current read or write position to the new location pos
|
||||
relative to the start of the current file fh.
|
||||
|
||||
\param[in] fh File handle
|
||||
\param[in] pos File pointer offset
|
||||
|
||||
\return The result is:
|
||||
- non-negative if no error occurs
|
||||
- negative if an error occurs
|
||||
*/
|
||||
#ifdef RETARGET_SYS
|
||||
__attribute__((weak))
|
||||
int _sys_seek (FILEHANDLE fh, long pos) {
|
||||
#if (!defined(RTE_Compiler_IO_File))
|
||||
(void)pos;
|
||||
#endif
|
||||
|
||||
switch (fh) {
|
||||
case FH_STDIN:
|
||||
return (-1);
|
||||
case FH_STDOUT:
|
||||
return (-1);
|
||||
case FH_STDERR:
|
||||
return (-1);
|
||||
}
|
||||
|
||||
#ifdef RTE_Compiler_IO_File
|
||||
#ifdef RTE_Compiler_IO_File_FS
|
||||
return (__sys_seek(fh, (uint32_t)pos));
|
||||
#endif
|
||||
#else
|
||||
return (-1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
Defined in rt_sys.h, this function returns the current length of a file.
|
||||
|
||||
This function is used by _sys_seek() to convert an offset relative to the
|
||||
end of a file into an offset relative to the beginning of the file.
|
||||
You do not have to define _sys_flen() if you do not intend to use fseek().
|
||||
If you retarget at system _sys_*() level, you must supply _sys_flen(),
|
||||
even if the underlying system directly supports seeking relative to the
|
||||
end of a file.
|
||||
|
||||
\param[in] fh File handle
|
||||
|
||||
\return This function returns the current length of the file fh,
|
||||
or a negative error indicator.
|
||||
*/
|
||||
#ifdef RETARGET_SYS
|
||||
__attribute__((weak))
|
||||
long _sys_flen (FILEHANDLE fh) {
|
||||
|
||||
switch (fh) {
|
||||
case FH_STDIN:
|
||||
return (0);
|
||||
case FH_STDOUT:
|
||||
return (0);
|
||||
case FH_STDERR:
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef RTE_Compiler_IO_File
|
||||
#ifdef RTE_Compiler_IO_File_FS
|
||||
return (__sys_flen(fh));
|
||||
#endif
|
||||
#else
|
||||
return (0);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#else /* gcc compiler */
|
||||
int _write(int file,
|
||||
char *ptr,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
(void)file;
|
||||
|
||||
for(i=0; i < len;i++)
|
||||
{
|
||||
stdout_putchar(*ptr++);
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#define log_str(...) \
|
||||
do { \
|
||||
const char *pchSrc = __VA_ARGS__; \
|
||||
uint_fast16_t hwSize = sizeof(__VA_ARGS__); \
|
||||
do { \
|
||||
stdout_putchar(*pchSrc++); \
|
||||
} while(--hwSize); \
|
||||
} while(0)
|
||||
|
||||
#ifdef GCCCOMPILER
|
||||
void _exit(int return_code)
|
||||
{
|
||||
(void)return_code;
|
||||
log_str("\n");
|
||||
log_str("_[TEST COMPLETE]_________________________________________________\n");
|
||||
log_str("\n\n");
|
||||
stdout_putchar(4);
|
||||
while(1);
|
||||
}
|
||||
#else
|
||||
void _sys_exit(int n)
|
||||
{
|
||||
(void)n;
|
||||
log_str("\n");
|
||||
log_str("_[TEST COMPLETE]_________________________________________________\n");
|
||||
log_str("\n\n");
|
||||
stdout_putchar(4);
|
||||
while(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern void ttywrch (int ch);
|
||||
__attribute__((weak))
|
||||
void _ttywrch (int ch)
|
||||
{
|
||||
ttywrch(ch);
|
||||
}
|
||||
Loading…
Reference in New Issue