From ae24b870e7928f3328e8c900d048b7f673cb9dec Mon Sep 17 00:00:00 2001 From: Christophe Favergeon Date: Mon, 11 Jul 2022 15:18:11 +0200 Subject: [PATCH] Added support for A5, A7 and A9 to test framework with cmsis build tools. AC6 only. There are still some limitations with gcc. --- .../cmsis_build/RTE/Device/ARMCA5/ARMCA5.ld | 181 ++++++++++++++ .../cmsis_build/RTE/Device/ARMCA5/ARMCA5.sct | 77 ++++++ .../RTE/Device/ARMCA5/mem_ARMCA5.h | 100 ++++++++ .../RTE/Device/ARMCA5/mmu_ARMCA5.c | 232 ++++++++++++++++++ .../RTE/Device/ARMCA5/startup_ARMCA5.c | 136 ++++++++++ .../RTE/Device/ARMCA5/system_ARMCA5.c | 93 +++++++ .../RTE/Device/ARMCA5/system_ARMCA5.h | 65 +++++ .../cmsis_build/RTE/Device/ARMCA7/ARMCA7.ld | 181 ++++++++++++++ .../cmsis_build/RTE/Device/ARMCA7/ARMCA7.sct | 77 ++++++ .../RTE/Device/ARMCA7/mem_ARMCA7.h | 100 ++++++++ .../RTE/Device/ARMCA7/mmu_ARMCA7.c | 232 ++++++++++++++++++ .../RTE/Device/ARMCA7/startup_ARMCA7.c | 136 ++++++++++ .../RTE/Device/ARMCA7/system_ARMCA7.c | 93 +++++++ .../RTE/Device/ARMCA7/system_ARMCA7.h | 65 +++++ .../cmsis_build/RTE/Device/ARMCA9/ARMCA9.ld | 181 ++++++++++++++ .../cmsis_build/RTE/Device/ARMCA9/ARMCA9.sct | 77 ++++++ .../RTE/Device/ARMCA9/mem_ARMCA9.h | 100 ++++++++ .../RTE/Device/ARMCA9/mmu_ARMCA9.c | 232 ++++++++++++++++++ .../RTE/Device/ARMCA9/startup_ARMCA9.c | 136 ++++++++++ .../RTE/Device/ARMCA9/system_ARMCA9.c | 93 +++++++ .../RTE/Device/ARMCA9/system_ARMCA9.h | 65 +++++ .../_test.Release_FVP_A5Neon/RTE_Components.h | 21 ++ .../_test.Release_FVP_A7Neon/RTE_Components.h | 21 ++ .../_test.Release_FVP_A9Neon/RTE_Components.h | 21 ++ Testing/cmsis_build/build.sh | 32 +-- .../cmsis_build/configs/ARMCA5neon_config.txt | 21 ++ .../cmsis_build/configs/ARMCA7neon_config.txt | 22 ++ .../cmsis_build/configs/ARMCA9neon_config.txt | 21 ++ Testing/cmsis_build/runarmds.bat | 11 + Testing/cmsis_build/runkeil.bat | 12 +- .../cmsis_build/test.Release+FVP_A5Neon.cprj | 167 +++++++++++++ .../cmsis_build/test.Release+FVP_A7Neon.cprj | 167 +++++++++++++ .../cmsis_build/test.Release+FVP_A9Neon.cprj | 167 +++++++++++++ Testing/cmsis_build/test.Release+FVP_M55.cprj | 4 +- .../test.Release+VHT-Corstone-300.cprj | 4 +- .../test.Release+VHT-Corstone-310.cprj | 4 +- Testing/cmsis_build/test.Release+VHT_M0P.cprj | 4 +- Testing/cmsis_build/test.Release+VHT_M23.cprj | 4 +- Testing/cmsis_build/test.Release+VHT_M3.cprj | 4 +- Testing/cmsis_build/test.Release+VHT_M33.cprj | 4 +- Testing/cmsis_build/test.Release+VHT_M4.cprj | 4 +- Testing/cmsis_build/test.Release+VHT_M7.cprj | 4 +- Testing/cmsis_build/test.cproject.yml | 37 +++ Testing/cmsis_build/test.csolution_ac6.yml | 53 +++- Testing/cmsis_build/test.csolution_gcc.yml | 50 +++- Testing/processResult.py | 5 +- 46 files changed, 3468 insertions(+), 48 deletions(-) create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA5/ARMCA5.ld create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA5/ARMCA5.sct create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA5/mem_ARMCA5.h create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA5/mmu_ARMCA5.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA5/startup_ARMCA5.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA5/system_ARMCA5.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA5/system_ARMCA5.h create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA7/ARMCA7.ld create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA7/ARMCA7.sct create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA7/mem_ARMCA7.h create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA7/mmu_ARMCA7.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA7/startup_ARMCA7.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA7/system_ARMCA7.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA7/system_ARMCA7.h create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA9/ARMCA9.ld create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA9/ARMCA9.sct create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA9/mem_ARMCA9.h create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA9/mmu_ARMCA9.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA9/startup_ARMCA9.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA9/system_ARMCA9.c create mode 100644 Testing/cmsis_build/RTE/Device/ARMCA9/system_ARMCA9.h create mode 100644 Testing/cmsis_build/RTE/_test.Release_FVP_A5Neon/RTE_Components.h create mode 100644 Testing/cmsis_build/RTE/_test.Release_FVP_A7Neon/RTE_Components.h create mode 100644 Testing/cmsis_build/RTE/_test.Release_FVP_A9Neon/RTE_Components.h create mode 100644 Testing/cmsis_build/configs/ARMCA5neon_config.txt create mode 100644 Testing/cmsis_build/configs/ARMCA7neon_config.txt create mode 100644 Testing/cmsis_build/configs/ARMCA9neon_config.txt create mode 100644 Testing/cmsis_build/runarmds.bat create mode 100644 Testing/cmsis_build/test.Release+FVP_A5Neon.cprj create mode 100644 Testing/cmsis_build/test.Release+FVP_A7Neon.cprj create mode 100644 Testing/cmsis_build/test.Release+FVP_A9Neon.cprj diff --git a/Testing/cmsis_build/RTE/Device/ARMCA5/ARMCA5.ld b/Testing/cmsis_build/RTE/Device/ARMCA5/ARMCA5.ld new file mode 100644 index 00000000..ff1f39ec --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA5/ARMCA5.ld @@ -0,0 +1,181 @@ +#include "mem_ARMCA5.h" + +MEMORY +{ + ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + + Image$$VECTORS$$Base = .; + * (RESET) + KEEP(*(.isr_vector)) + Image$$VECTORS$$Limit = .; + + *(SVC_TABLE) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + Image$$RO_DATA$$Base = .; + *(.rodata*) + Image$$RO_DATA$$Limit = .; + + KEEP(*(.eh_frame*)) + } > ROM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + __copy_table_end__ = .; + } > ROM + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > ROM + + __etext = .; + + .ttb : + { + Image$$TTB$$ZI$$Base = .; + . += __TTB_SIZE; + Image$$TTB$$ZI$$Limit = .; + } > L_TTB + + .data : AT (__etext) + { + Image$$RW_DATA$$Base = .; + __data_start__ = .; + *(vtable) + *(.data*) + Image$$RW_DATA$$Limit = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + + .bss ALIGN(0x400): + { + Image$$ZI_DATA$$Base = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + Image$$ZI_DATA$$Limit = .; + __end__ = .; + end = __end__; + } > RAM + +#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) + .heap (NOLOAD): + { + . = ALIGN(8); + Image$$HEAP$$ZI$$Base = .; + . += __HEAP_SIZE; + Image$$HEAP$$ZI$$Limit = .; + __HeapLimit = .; + } > RAM +#endif + + .stack (NOLOAD): + { + . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; + . = ALIGN(8); + + __StackTop = .; + Image$$SYS_STACK$$ZI$$Base = .; + . += __STACK_SIZE; + Image$$SYS_STACK$$ZI$$Limit = .; + __stack = .; + + Image$$FIQ_STACK$$ZI$$Base = .; + . += __FIQ_STACK_SIZE; + Image$$FIQ_STACK$$ZI$$Limit = .; + + Image$$IRQ_STACK$$ZI$$Base = .; + . += __IRQ_STACK_SIZE; + Image$$IRQ_STACK$$ZI$$Limit = .; + + Image$$SVC_STACK$$ZI$$Base = .; + . += __SVC_STACK_SIZE; + Image$$SVC_STACK$$ZI$$Limit = .; + + Image$$ABT_STACK$$ZI$$Base = .; + . += __ABT_STACK_SIZE; + Image$$ABT_STACK$$ZI$$Limit = .; + + Image$$UND_STACK$$ZI$$Base = .; + . += __UND_STACK_SIZE; + Image$$UND_STACK$$ZI$$Limit = .; + + } > RAM +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA5/ARMCA5.sct b/Testing/cmsis_build/RTE/Device/ARMCA5/ARMCA5.sct new file mode 100644 index 00000000..41e562cb --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA5/ARMCA5.sct @@ -0,0 +1,77 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc +;************************************************** +; Copyright (c) 2017 ARM Ltd. All rights reserved. +;************************************************** + +; Scatter-file for RTX Example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +; This platform has 2GB SDRAM starting at 0x80000000. + +#include "mem_ARMCA5.h" + +SDRAM __ROM_BASE __ROM_SIZE ; load region size_region +{ + VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + * (+RO-DATA) ; Application RO data (.constdata) + } + + RW_DATA __RAM_BASE __RW_DATA_SIZE + { * (+RW) } ; Application RW data (.data) + + ZI_DATA (__RAM_BASE+ + __RW_DATA_SIZE) __ZI_DATA_SIZE + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP (__RAM_BASE + +__RW_DATA_SIZE + +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up + { } + + ARM_LIB_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE + -__ABT_STACK_SIZE + -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down + { } + + UND_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE + -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack + { } + + ABT_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack + { } + + SVC_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack + { } + + IRQ_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack + { } + + FIQ_STACK (__RAM_BASE + +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack + { } + + TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU + { } +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA5/mem_ARMCA5.h b/Testing/cmsis_build/RTE/Device/ARMCA5/mem_ARMCA5.h new file mode 100644 index 00000000..62d97e16 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA5/mem_ARMCA5.h @@ -0,0 +1,100 @@ +/**************************************************************************//** + * @file mem_ARMCA5.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCA5_H +#define __MEM_ARMCA5_H + +/*---------------------------------------------------------------------------- + User Stack & Heap size definition + *----------------------------------------------------------------------------*/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- ROM Configuration ------------------------------------ +// +// ROM Configuration +// For compatibility with MMU config the sections must be multiple of 1MB +// ROM Base Address <0x0-0xFFFFFFFF:0x100000> +// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> +// + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x80000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- RAM Configuration ----------------------------------- +// RAM Configuration +// For compatibility with MMU config the sections must be multiple of 1MB +// RAM Base Address <0x0-0xFFFFFFFF:0x100000> +// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> +// Data Sections +// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> +// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Exceptional Modes +// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +// +// + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x80200000 +#define __RAM_SIZE 0x00300000 + +#define __RW_DATA_SIZE 0x00100000 +#define __ZI_DATA_SIZE 0x000F0000 + +#define __STACK_SIZE 0x00002000 +#define __HEAP_SIZE 0x00100000 + +#define __UND_STACK_SIZE 0x00000100 +#define __ABT_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 + +/*----------------------------------------------------------------------------*/ + +/*--------------------- TTB Configuration ------------------------------------ +// +// TTB Configuration +// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned +// The TLB L2 entries are placed after the L1 in the MMU config +// TTB Base Address <0x0-0xFFFFFFFF:0x4000> +// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __TTB_BASE 0x80500000 +#define __TTB_SIZE 0x00005000 + +#endif /* __MEM_ARMCA5_H */ diff --git a/Testing/cmsis_build/RTE/Device/ARMCA5/mmu_ARMCA5.c b/Testing/cmsis_build/RTE/Device/ARMCA5/mmu_ARMCA5.c new file mode 100644 index 00000000..58a94805 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA5/mmu_ARMCA5.c @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file mmu_ARMCA5.c + * @brief MMU Configuration for ARM Cortex-A5 Device Series + * @version V1.2.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map + + Memory Type +0xffffffff |--------------------------| ------------ + | FLAG SYNC | Device Memory +0xfffff000 |--------------------------| ------------ + | Fault | Fault +0xfff00000 |--------------------------| ------------ + | | Normal + | | + | Daughterboard | + | memory | + | | +0x80505000 |--------------------------| ------------ + |TTB (L2 Sync Flags ) 4k | Normal +0x80504C00 |--------------------------| ------------ + |TTB (L2 Peripherals-B) 16k| Normal +0x80504800 |--------------------------| ------------ + |TTB (L2 Peripherals-A) 16k| Normal +0x80504400 |--------------------------| ------------ + |TTB (L2 Priv Periphs) 4k | Normal +0x80504000 |--------------------------| ------------ + | TTB (L1 Descriptors) | Normal +0x80500000 |--------------------------| ------------ + | Stack | Normal + |--------------------------| ------------ + | Heap | Normal +0x80400000 |--------------------------| ------------ + | ZI Data | Normal +0x80300000 |--------------------------| ------------ + | RW Data | Normal +0x80200000 |--------------------------| ------------ + | RO Data | Normal + |--------------------------| ------------ + | RO Code | USH Normal +0x80000000 |--------------------------| ------------ + | Daughterboard | Fault + | HSB AXI buses | +0x40000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x2c002000 |--------------------------| ------------ + | Private Address | Device Memory +0x2c000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x20000000 |--------------------------| ------------ + | Peripherals | Device Memory RW/RO + | | & Fault +0x00000000 |--------------------------| +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 + +#include "ARMCA5.h" +#include "mem_ARMCA5.h" + +// TTB base address +#define TTB_BASE ((uint32_t*)__TTB_BASE) + +// L2 table pointers +//---------------------------------------- +#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core + // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. + // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. + +#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space +#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF +#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF +#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization + +//--------------------- PERIPHERALS ------------------- +#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) +#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) + +//--------------------- SYNC FLAGS -------------------- +#define FLAG_SYNC 0xFFFFF000 +#define F_SYNC_BASE 0xFFF00000 //1M aligned + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; + + //Create 4GB of faulting entries + MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); + + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Define Image + MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections + MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections + + //--------------------- PERIPHERALS ------------------- + MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR + MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR + MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM + MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM + MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW); + MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE , 16, Sect_Device_RW); + + // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF + MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); + // Define peripheral range 0x1C000000-0x1C00FFFF + MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + + // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF + MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); + // Define peripheral range 0x1C100000-0x1C10FFFF + MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + + // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory + MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); + // Define private address space entry. + MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); + // Define L2CC entry. Uncomment if PL310 is present + // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); + + // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) + MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); + // Define synchronization space entry. + MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x1 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x01 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x0 (Inner WB WA) */ + __set_TTBR0(__TTB_BASE | 0x48); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA5/startup_ARMCA5.c b/Testing/cmsis_build/RTE/Device/ARMCA5/startup_ARMCA5.c new file mode 100644 index 00000000..99f7b63e --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA5/startup_ARMCA5.c @@ -0,0 +1,136 @@ +/****************************************************************************** + * @file startup_ARMCA5.c + * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series + * @version V1.0.1 + * @date 10. January 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +/*---------------------------------------------------------------------------- + Definitions + *----------------------------------------------------------------------------*/ +#define USR_MODE 0x10 // User mode +#define FIQ_MODE 0x11 // Fast Interrupt Request mode +#define IRQ_MODE 0x12 // Interrupt Request mode +#define SVC_MODE 0x13 // Supervisor mode +#define ABT_MODE 0x17 // Abort mode +#define UND_MODE 0x1B // Undefined Instruction mode +#define SYS_MODE 0x1F // System mode + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Vectors (void) __attribute__ ((naked, section("RESET"))); +void Reset_Handler (void) __attribute__ ((naked)); +void Default_Handler(void) __attribute__ ((noreturn)); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ +void Vectors(void) { + __ASM volatile( + "LDR PC, =Reset_Handler \n" + "LDR PC, =Undef_Handler \n" + "LDR PC, =SVC_Handler \n" + "LDR PC, =PAbt_Handler \n" + "LDR PC, =DAbt_Handler \n" + "NOP \n" + "LDR PC, =IRQ_Handler \n" + "LDR PC, =FIQ_Handler \n" + ); +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + __ASM volatile( + + // Mask interrupts + "CPSID if \n" + + // Put any cores other than 0 to sleep + "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR + "ANDS R0, R0, #3 \n" + "goToSleep: \n" + "WFINE \n" + "BNE goToSleep \n" + + // Reset SCTLR Settings + "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register + "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache + "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache + "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU + "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction + "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs + "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register + "ISB \n" + + // Configure ACTLR + "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register + "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) + "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register + + // Set Vector Base Address Register (VBAR) to point to this application's vector table + "LDR R0, =Vectors \n" + "MCR p15, 0, R0, c12, c0, 0 \n" + + // Setup Stack for each exceptional mode + "CPS #0x11 \n" + "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" + "CPS #0x12 \n" + "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" + "CPS #0x13 \n" + "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" + "CPS #0x17 \n" + "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" + "CPS #0x1B \n" + "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" + "CPS #0x1F \n" + "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" + + // Call SystemInit + "BL SystemInit \n" + + // Unmask interrupts + "CPSIE if \n" + + // Call __main + "BL __main \n" + ); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA5/system_ARMCA5.c b/Testing/cmsis_build/RTE/Device/ARMCA5/system_ARMCA5.c new file mode 100644 index 00000000..5f599f63 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA5/system_ARMCA5.c @@ -0,0 +1,93 @@ +/****************************************************************************** + * @file system_ARMCA5.c + * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series + * @version V1.0.1 + * @date 13. February 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "irq_ctrl.h" + +#define SYSTEM_CLOCK 12000000U + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section may be overwritten afterwards. */ + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + // Enable GIC + L2C_Enable(); +#endif + + // IRQ Initialize + IRQ_Initialize(); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA5/system_ARMCA5.h b/Testing/cmsis_build/RTE/Device/ARMCA5/system_ARMCA5.h new file mode 100644 index 00000000..6a2a6dad --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA5/system_ARMCA5.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * @file system_ARMCA5.h + * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series + * @version V1.00 + * @date 10. January 2018 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_ARMCA5_H +#define __SYSTEM_ARMCA5_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_ARMCA5_H */ diff --git a/Testing/cmsis_build/RTE/Device/ARMCA7/ARMCA7.ld b/Testing/cmsis_build/RTE/Device/ARMCA7/ARMCA7.ld new file mode 100644 index 00000000..62c4ba1f --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA7/ARMCA7.ld @@ -0,0 +1,181 @@ +#include "mem_ARMCA7.h" + +MEMORY +{ + ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + + Image$$VECTORS$$Base = .; + * (RESET) + KEEP(*(.isr_vector)) + Image$$VECTORS$$Limit = .; + + *(SVC_TABLE) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + Image$$RO_DATA$$Base = .; + *(.rodata*) + Image$$RO_DATA$$Limit = .; + + KEEP(*(.eh_frame*)) + } > ROM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + __copy_table_end__ = .; + } > ROM + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > ROM + + __etext = .; + + .ttb : + { + Image$$TTB$$ZI$$Base = .; + . += __TTB_SIZE; + Image$$TTB$$ZI$$Limit = .; + } > L_TTB + + .data : AT (__etext) + { + Image$$RW_DATA$$Base = .; + __data_start__ = .; + *(vtable) + *(.data*) + Image$$RW_DATA$$Limit = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + + .bss ALIGN(0x400): + { + Image$$ZI_DATA$$Base = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + Image$$ZI_DATA$$Limit = .; + __end__ = .; + end = __end__; + } > RAM + +#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) + .heap (NOLOAD): + { + . = ALIGN(8); + Image$$HEAP$$ZI$$Base = .; + . += __HEAP_SIZE; + Image$$HEAP$$ZI$$Limit = .; + __HeapLimit = .; + } > RAM +#endif + + .stack (NOLOAD): + { + . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; + . = ALIGN(8); + + __StackTop = .; + Image$$SYS_STACK$$ZI$$Base = .; + . += __STACK_SIZE; + Image$$SYS_STACK$$ZI$$Limit = .; + __stack = .; + + Image$$FIQ_STACK$$ZI$$Base = .; + . += __FIQ_STACK_SIZE; + Image$$FIQ_STACK$$ZI$$Limit = .; + + Image$$IRQ_STACK$$ZI$$Base = .; + . += __IRQ_STACK_SIZE; + Image$$IRQ_STACK$$ZI$$Limit = .; + + Image$$SVC_STACK$$ZI$$Base = .; + . += __SVC_STACK_SIZE; + Image$$SVC_STACK$$ZI$$Limit = .; + + Image$$ABT_STACK$$ZI$$Base = .; + . += __ABT_STACK_SIZE; + Image$$ABT_STACK$$ZI$$Limit = .; + + Image$$UND_STACK$$ZI$$Base = .; + . += __UND_STACK_SIZE; + Image$$UND_STACK$$ZI$$Limit = .; + + } > RAM +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA7/ARMCA7.sct b/Testing/cmsis_build/RTE/Device/ARMCA7/ARMCA7.sct new file mode 100644 index 00000000..d8f37161 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA7/ARMCA7.sct @@ -0,0 +1,77 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc +;************************************************** +; Copyright (c) 2017 ARM Ltd. All rights reserved. +;************************************************** + +; Scatter-file for RTX Example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +; This platform has 2GB SDRAM starting at 0x80000000. + +#include "mem_ARMCA7.h" + +SDRAM __ROM_BASE __ROM_SIZE ; load region size_region +{ + VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + * (+RO-DATA) ; Application RO data (.constdata) + } + + RW_DATA __RAM_BASE __RW_DATA_SIZE + { * (+RW) } ; Application RW data (.data) + + ZI_DATA (__RAM_BASE+ + __RW_DATA_SIZE) __ZI_DATA_SIZE + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP (__RAM_BASE + +__RW_DATA_SIZE + +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up + { } + + ARM_LIB_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE + -__ABT_STACK_SIZE + -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down + { } + + UND_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE + -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack + { } + + ABT_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack + { } + + SVC_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack + { } + + IRQ_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack + { } + + FIQ_STACK (__RAM_BASE + +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack + { } + + TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU + { } +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA7/mem_ARMCA7.h b/Testing/cmsis_build/RTE/Device/ARMCA7/mem_ARMCA7.h new file mode 100644 index 00000000..c88fdb9d --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA7/mem_ARMCA7.h @@ -0,0 +1,100 @@ +/**************************************************************************//** + * @file mem_ARMCA7.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCA7_H +#define __MEM_ARMCA7_H + +/*---------------------------------------------------------------------------- + User Stack & Heap size definition + *----------------------------------------------------------------------------*/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- ROM Configuration ------------------------------------ +// +// ROM Configuration +// For compatibility with MMU config the sections must be multiple of 1MB +// ROM Base Address <0x0-0xFFFFFFFF:0x100000> +// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> +// + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x80000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- RAM Configuration ----------------------------------- +// RAM Configuration +// For compatibility with MMU config the sections must be multiple of 1MB +// RAM Base Address <0x0-0xFFFFFFFF:0x100000> +// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> +// Data Sections +// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> +// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Exceptional Modes +// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +// +// + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x80200000 +#define __RAM_SIZE 0x00300000 + +#define __RW_DATA_SIZE 0x00100000 +#define __ZI_DATA_SIZE 0x000F0000 + +#define __STACK_SIZE 0x00002000 +#define __HEAP_SIZE 0x00100000 + +#define __UND_STACK_SIZE 0x00000100 +#define __ABT_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 + +/*----------------------------------------------------------------------------*/ + +/*--------------------- TTB Configuration ------------------------------------ +// +// TTB Configuration +// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned +// The TLB L2 entries are placed after the L1 in the MMU config +// TTB Base Address <0x0-0xFFFFFFFF:0x4000> +// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __TTB_BASE 0x80500000 +#define __TTB_SIZE 0x00005000 + +#endif /* __MEM_ARMCA7_H */ diff --git a/Testing/cmsis_build/RTE/Device/ARMCA7/mmu_ARMCA7.c b/Testing/cmsis_build/RTE/Device/ARMCA7/mmu_ARMCA7.c new file mode 100644 index 00000000..26431f3b --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA7/mmu_ARMCA7.c @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file mmu_ARMCA7.c + * @brief MMU Configuration for Arm Cortex-A7 Device Series + * @version V1.2.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map + + Memory Type +0xffffffff |--------------------------| ------------ + | FLAG SYNC | Device Memory +0xfffff000 |--------------------------| ------------ + | Fault | Fault +0xfff00000 |--------------------------| ------------ + | | Normal + | | + | Daughterboard | + | memory | + | | +0x80505000 |--------------------------| ------------ + |TTB (L2 Sync Flags ) 4k | Normal +0x80504C00 |--------------------------| ------------ + |TTB (L2 Peripherals-B) 16k| Normal +0x80504800 |--------------------------| ------------ + |TTB (L2 Peripherals-A) 16k| Normal +0x80504400 |--------------------------| ------------ + |TTB (L2 Priv Periphs) 4k | Normal +0x80504000 |--------------------------| ------------ + | TTB (L1 Descriptors) | Normal +0x80500000 |--------------------------| ------------ + | Stack | Normal + |--------------------------| ------------ + | Heap | Normal +0x80400000 |--------------------------| ------------ + | ZI Data | Normal +0x80300000 |--------------------------| ------------ + | RW Data | Normal +0x80200000 |--------------------------| ------------ + | RO Data | Normal + |--------------------------| ------------ + | RO Code | USH Normal +0x80000000 |--------------------------| ------------ + | Daughterboard | Fault + | HSB AXI buses | +0x40000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x2c002000 |--------------------------| ------------ + | Private Address | Device Memory +0x2c000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x20000000 |--------------------------| ------------ + | Peripherals | Device Memory RW/RO + | | & Fault +0x00000000 |--------------------------| +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 + +#include "ARMCA7.h" +#include "mem_ARMCA7.h" + +// TTB base address +#define TTB_BASE ((uint32_t*)__TTB_BASE) + +// L2 table pointers +//---------------------------------------- +#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core + // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. + // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. + +#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space +#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF +#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF +#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization + +//--------------------- PERIPHERALS ------------------- +#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) +#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) + +//--------------------- SYNC FLAGS -------------------- +#define FLAG_SYNC 0xFFFFF000 +#define F_SYNC_BASE 0xFFF00000 //1M aligned + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; + + //Create 4GB of faulting entries + MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); + + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Define Image + MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections + MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections + + //--------------------- PERIPHERALS ------------------- + MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR + MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR + MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM + MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM + MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW); + MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE , 16, Sect_Device_RW); + + // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF + MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); + // Define peripheral range 0x1C000000-0x1C00FFFF + MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + + // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF + MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); + // Define peripheral range 0x1C100000-0x1C10FFFF + MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + + // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory + MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); + // Define private address space entry. + MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); + // Define L2CC entry. Uncomment if PL310 is present + // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); + + // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) + MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); + // Define synchronization space entry. + MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x1 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x01 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x0 (Inner WB WA) */ + __set_TTBR0(__TTB_BASE | 0x48); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA7/startup_ARMCA7.c b/Testing/cmsis_build/RTE/Device/ARMCA7/startup_ARMCA7.c new file mode 100644 index 00000000..da8ae87d --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA7/startup_ARMCA7.c @@ -0,0 +1,136 @@ +/****************************************************************************** + * @file startup_ARMCA7.c + * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series + * @version V1.0.1 + * @date 10. January 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +/*---------------------------------------------------------------------------- + Definitions + *----------------------------------------------------------------------------*/ +#define USR_MODE 0x10 // User mode +#define FIQ_MODE 0x11 // Fast Interrupt Request mode +#define IRQ_MODE 0x12 // Interrupt Request mode +#define SVC_MODE 0x13 // Supervisor mode +#define ABT_MODE 0x17 // Abort mode +#define UND_MODE 0x1B // Undefined Instruction mode +#define SYS_MODE 0x1F // System mode + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Vectors (void) __attribute__ ((naked, section("RESET"))); +void Reset_Handler (void) __attribute__ ((naked)); +void Default_Handler(void) __attribute__ ((noreturn)); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ +void Vectors(void) { + __ASM volatile( + "LDR PC, =Reset_Handler \n" + "LDR PC, =Undef_Handler \n" + "LDR PC, =SVC_Handler \n" + "LDR PC, =PAbt_Handler \n" + "LDR PC, =DAbt_Handler \n" + "NOP \n" + "LDR PC, =IRQ_Handler \n" + "LDR PC, =FIQ_Handler \n" + ); +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + __ASM volatile( + + // Mask interrupts + "CPSID if \n" + + // Put any cores other than 0 to sleep + "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR + "ANDS R0, R0, #3 \n" + "goToSleep: \n" + "WFINE \n" + "BNE goToSleep \n" + + // Reset SCTLR Settings + "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register + "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache + "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache + "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU + "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction + "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs + "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register + "ISB \n" + + // Configure ACTLR + "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register + "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) + "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register + + // Set Vector Base Address Register (VBAR) to point to this application's vector table + "LDR R0, =Vectors \n" + "MCR p15, 0, R0, c12, c0, 0 \n" + + // Setup Stack for each exceptional mode + "CPS #0x11 \n" + "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" + "CPS #0x12 \n" + "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" + "CPS #0x13 \n" + "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" + "CPS #0x17 \n" + "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" + "CPS #0x1B \n" + "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" + "CPS #0x1F \n" + "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" + + // Call SystemInit + "BL SystemInit \n" + + // Unmask interrupts + "CPSIE if \n" + + // Call __main + "BL __main \n" + ); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA7/system_ARMCA7.c b/Testing/cmsis_build/RTE/Device/ARMCA7/system_ARMCA7.c new file mode 100644 index 00000000..803ec490 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA7/system_ARMCA7.c @@ -0,0 +1,93 @@ +/****************************************************************************** + * @file system_ARMCA7.c + * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series + * @version V1.0.1 + * @date 13. February 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "irq_ctrl.h" + +#define SYSTEM_CLOCK 12000000U + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section may be overwritten afterwards. */ + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + // Enable GIC + L2C_Enable(); +#endif + + // IRQ Initialize + IRQ_Initialize(); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA7/system_ARMCA7.h b/Testing/cmsis_build/RTE/Device/ARMCA7/system_ARMCA7.h new file mode 100644 index 00000000..0405aa34 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA7/system_ARMCA7.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * @file system_ARMCA7.h + * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series + * @version V1.00 + * @date 10. January 2018 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_ARMCA7_H +#define __SYSTEM_ARMCA7_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_ARMCA7_H */ diff --git a/Testing/cmsis_build/RTE/Device/ARMCA9/ARMCA9.ld b/Testing/cmsis_build/RTE/Device/ARMCA9/ARMCA9.ld new file mode 100644 index 00000000..ee3d8369 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA9/ARMCA9.ld @@ -0,0 +1,181 @@ +#include "mem_ARMCA9.h" + +MEMORY +{ + ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + + Image$$VECTORS$$Base = .; + * (RESET) + KEEP(*(.isr_vector)) + Image$$VECTORS$$Limit = .; + + *(SVC_TABLE) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + Image$$RO_DATA$$Base = .; + *(.rodata*) + Image$$RO_DATA$$Limit = .; + + KEEP(*(.eh_frame*)) + } > ROM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + __copy_table_end__ = .; + } > ROM + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > ROM + + __etext = .; + + .ttb : + { + Image$$TTB$$ZI$$Base = .; + . += __TTB_SIZE; + Image$$TTB$$ZI$$Limit = .; + } > L_TTB + + .data : AT (__etext) + { + Image$$RW_DATA$$Base = .; + __data_start__ = .; + *(vtable) + *(.data*) + Image$$RW_DATA$$Limit = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + + .bss ALIGN(0x400): + { + Image$$ZI_DATA$$Base = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + Image$$ZI_DATA$$Limit = .; + __end__ = .; + end = __end__; + } > RAM + +#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) + .heap (NOLOAD): + { + . = ALIGN(8); + Image$$HEAP$$ZI$$Base = .; + . += __HEAP_SIZE; + Image$$HEAP$$ZI$$Limit = .; + __HeapLimit = .; + } > RAM +#endif + + .stack (NOLOAD): + { + . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; + . = ALIGN(8); + + __StackTop = .; + Image$$SYS_STACK$$ZI$$Base = .; + . += __STACK_SIZE; + Image$$SYS_STACK$$ZI$$Limit = .; + __stack = .; + + Image$$FIQ_STACK$$ZI$$Base = .; + . += __FIQ_STACK_SIZE; + Image$$FIQ_STACK$$ZI$$Limit = .; + + Image$$IRQ_STACK$$ZI$$Base = .; + . += __IRQ_STACK_SIZE; + Image$$IRQ_STACK$$ZI$$Limit = .; + + Image$$SVC_STACK$$ZI$$Base = .; + . += __SVC_STACK_SIZE; + Image$$SVC_STACK$$ZI$$Limit = .; + + Image$$ABT_STACK$$ZI$$Base = .; + . += __ABT_STACK_SIZE; + Image$$ABT_STACK$$ZI$$Limit = .; + + Image$$UND_STACK$$ZI$$Base = .; + . += __UND_STACK_SIZE; + Image$$UND_STACK$$ZI$$Limit = .; + + } > RAM +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA9/ARMCA9.sct b/Testing/cmsis_build/RTE/Device/ARMCA9/ARMCA9.sct new file mode 100644 index 00000000..3316f936 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA9/ARMCA9.sct @@ -0,0 +1,77 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc +;************************************************** +; Copyright (c) 2017 ARM Ltd. All rights reserved. +;************************************************** + +; Scatter-file for RTX Example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +; This platform has 2GB SDRAM starting at 0x80000000. + +#include "mem_ARMCA9.h" + +SDRAM __ROM_BASE __ROM_SIZE ; load region size_region +{ + VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + * (+RO-DATA) ; Application RO data (.constdata) + } + + RW_DATA __RAM_BASE __RW_DATA_SIZE + { * (+RW) } ; Application RW data (.data) + + ZI_DATA (__RAM_BASE+ + __RW_DATA_SIZE) __ZI_DATA_SIZE + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP (__RAM_BASE + +__RW_DATA_SIZE + +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up + { } + + ARM_LIB_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE + -__ABT_STACK_SIZE + -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down + { } + + UND_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE + -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack + { } + + ABT_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE + -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack + { } + + SVC_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE + -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack + { } + + IRQ_STACK (__RAM_BASE + +__RAM_SIZE + -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack + { } + + FIQ_STACK (__RAM_BASE + +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack + { } + + TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU + { } +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA9/mem_ARMCA9.h b/Testing/cmsis_build/RTE/Device/ARMCA9/mem_ARMCA9.h new file mode 100644 index 00000000..80c90b83 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA9/mem_ARMCA9.h @@ -0,0 +1,100 @@ +/**************************************************************************//** + * @file mem_ARMCA9.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCA9_H +#define __MEM_ARMCA9_H + +/*---------------------------------------------------------------------------- + User Stack & Heap size definition + *----------------------------------------------------------------------------*/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- ROM Configuration ------------------------------------ +// +// ROM Configuration +// For compatibility with MMU config the sections must be multiple of 1MB +// ROM Base Address <0x0-0xFFFFFFFF:0x100000> +// ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> +// + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x80000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- RAM Configuration ----------------------------------- +// RAM Configuration +// For compatibility with MMU config the sections must be multiple of 1MB +// RAM Base Address <0x0-0xFFFFFFFF:0x100000> +// RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> +// Data Sections +// RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> +// ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Exceptional Modes +// UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +// +// + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x80200000 +#define __RAM_SIZE 0x00300000 + +#define __RW_DATA_SIZE 0x00100000 +#define __ZI_DATA_SIZE 0x000F0000 + +#define __STACK_SIZE 0x00002000 +#define __HEAP_SIZE 0x00100000 + +#define __UND_STACK_SIZE 0x00000100 +#define __ABT_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 + +/*----------------------------------------------------------------------------*/ + +/*--------------------- TTB Configuration ------------------------------------ +// +// TTB Configuration +// The TLB L1 contains 4096 32-bit entries and must be 16kB aligned +// The TLB L2 entries are placed after the L1 in the MMU config +// TTB Base Address <0x0-0xFFFFFFFF:0x4000> +// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __TTB_BASE 0x80500000 +#define __TTB_SIZE 0x00005000 + +#endif /* __MEM_ARMCA9_H */ diff --git a/Testing/cmsis_build/RTE/Device/ARMCA9/mmu_ARMCA9.c b/Testing/cmsis_build/RTE/Device/ARMCA9/mmu_ARMCA9.c new file mode 100644 index 00000000..1435eb92 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA9/mmu_ARMCA9.c @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file mmu_ARMCA9.c + * @brief MMU Configuration for Arm Cortex-A9 Device Series + * @version V1.2.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map + + Memory Type +0xffffffff |--------------------------| ------------ + | FLAG SYNC | Device Memory +0xfffff000 |--------------------------| ------------ + | Fault | Fault +0xfff00000 |--------------------------| ------------ + | | Normal + | | + | Daughterboard | + | memory | + | | +0x80505000 |--------------------------| ------------ + |TTB (L2 Sync Flags ) 4k | Normal +0x80504C00 |--------------------------| ------------ + |TTB (L2 Peripherals-B) 16k| Normal +0x80504800 |--------------------------| ------------ + |TTB (L2 Peripherals-A) 16k| Normal +0x80504400 |--------------------------| ------------ + |TTB (L2 Priv Periphs) 4k | Normal +0x80504000 |--------------------------| ------------ + | TTB (L1 Descriptors) | Normal +0x80500000 |--------------------------| ------------ + | Stack | Normal + |--------------------------| ------------ + | Heap | Normal +0x80400000 |--------------------------| ------------ + | ZI Data | Normal +0x80300000 |--------------------------| ------------ + | RW Data | Normal +0x80200000 |--------------------------| ------------ + | RO Data | Normal + |--------------------------| ------------ + | RO Code | USH Normal +0x80000000 |--------------------------| ------------ + | Daughterboard | Fault + | HSB AXI buses | +0x40000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x2c002000 |--------------------------| ------------ + | Private Address | Device Memory +0x2c000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x20000000 |--------------------------| ------------ + | Peripherals | Device Memory RW/RO + | | & Fault +0x00000000 |--------------------------| +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 + +#include "ARMCA9.h" +#include "mem_ARMCA9.h" + +// TTB base address +#define TTB_BASE ((uint32_t*)__TTB_BASE) + +// L2 table pointers +//---------------------------------------- +#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core + // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. + // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. + +#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space +#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF +#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF +#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization + +//--------------------- PERIPHERALS ------------------- +#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) +#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) + +//--------------------- SYNC FLAGS -------------------- +#define FLAG_SYNC 0xFFFFF000 +#define F_SYNC_BASE 0xFFF00000 //1M aligned + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; + + //Create 4GB of faulting entries + MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); + + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Define Image + MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections + MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections + + //--------------------- PERIPHERALS ------------------- + MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR + MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR + MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM + MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM + MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW); + MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE , 16, Sect_Device_RW); + + // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF + MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); + // Define peripheral range 0x1C000000-0x1C00FFFF + MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); + + // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF + MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); + // Define peripheral range 0x1C100000-0x1C10FFFF + MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); + + // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory + MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); + // Define private address space entry. + MMU_TTPage4k (TTB_BASE, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); + // Define L2CC entry. Uncomment if PL310 is present + // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); + + // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) + MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); + // Define synchronization space entry. + MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x1 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x01 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x0 (Inner WB WA) */ + __set_TTBR0(__TTB_BASE | 0x48); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA9/startup_ARMCA9.c b/Testing/cmsis_build/RTE/Device/ARMCA9/startup_ARMCA9.c new file mode 100644 index 00000000..88173fc6 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA9/startup_ARMCA9.c @@ -0,0 +1,136 @@ +/****************************************************************************** + * @file startup_ARMCA9.c + * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series + * @version V1.0.1 + * @date 10. January 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +/*---------------------------------------------------------------------------- + Definitions + *----------------------------------------------------------------------------*/ +#define USR_MODE 0x10 // User mode +#define FIQ_MODE 0x11 // Fast Interrupt Request mode +#define IRQ_MODE 0x12 // Interrupt Request mode +#define SVC_MODE 0x13 // Supervisor mode +#define ABT_MODE 0x17 // Abort mode +#define UND_MODE 0x1B // Undefined Instruction mode +#define SYS_MODE 0x1F // System mode + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Vectors (void) __attribute__ ((naked, section("RESET"))); +void Reset_Handler (void) __attribute__ ((naked)); +void Default_Handler(void) __attribute__ ((noreturn)); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ +void Vectors(void) { + __ASM volatile( + "LDR PC, =Reset_Handler \n" + "LDR PC, =Undef_Handler \n" + "LDR PC, =SVC_Handler \n" + "LDR PC, =PAbt_Handler \n" + "LDR PC, =DAbt_Handler \n" + "NOP \n" + "LDR PC, =IRQ_Handler \n" + "LDR PC, =FIQ_Handler \n" + ); +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + __ASM volatile( + + // Mask interrupts + "CPSID if \n" + + // Put any cores other than 0 to sleep + "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR + "ANDS R0, R0, #3 \n" + "goToSleep: \n" + "WFINE \n" + "BNE goToSleep \n" + + // Reset SCTLR Settings + "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register + "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache + "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache + "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU + "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction + "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs + "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register + "ISB \n" + + // Configure ACTLR + "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register + "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) + "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register + + // Set Vector Base Address Register (VBAR) to point to this application's vector table + "LDR R0, =Vectors \n" + "MCR p15, 0, R0, c12, c0, 0 \n" + + // Setup Stack for each exceptional mode + "CPS #0x11 \n" + "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" + "CPS #0x12 \n" + "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" + "CPS #0x13 \n" + "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" + "CPS #0x17 \n" + "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" + "CPS #0x1B \n" + "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" + "CPS #0x1F \n" + "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" + + // Call SystemInit + "BL SystemInit \n" + + // Unmask interrupts + "CPSIE if \n" + + // Call __main + "BL __main \n" + ); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA9/system_ARMCA9.c b/Testing/cmsis_build/RTE/Device/ARMCA9/system_ARMCA9.c new file mode 100644 index 00000000..cdf9213d --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA9/system_ARMCA9.c @@ -0,0 +1,93 @@ +/****************************************************************************** + * @file system_ARMCA9.c + * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series + * @version V1.0.1 + * @date 13. February 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "irq_ctrl.h" + +#define SYSTEM_CLOCK 12000000U + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section may be overwritten afterwards. */ + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + // Enable GIC + L2C_Enable(); +#endif + + // IRQ Initialize + IRQ_Initialize(); +} diff --git a/Testing/cmsis_build/RTE/Device/ARMCA9/system_ARMCA9.h b/Testing/cmsis_build/RTE/Device/ARMCA9/system_ARMCA9.h new file mode 100644 index 00000000..b60ce5a2 --- /dev/null +++ b/Testing/cmsis_build/RTE/Device/ARMCA9/system_ARMCA9.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * @file system_ARMCA9.h + * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series + * @version V1.00 + * @date 10. January 2018 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_ARMCA9_H +#define __SYSTEM_ARMCA9_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_ARMCA9_H */ diff --git a/Testing/cmsis_build/RTE/_test.Release_FVP_A5Neon/RTE_Components.h b/Testing/cmsis_build/RTE/_test.Release_FVP_A5Neon/RTE_Components.h new file mode 100644 index 00000000..7b516ee2 --- /dev/null +++ b/Testing/cmsis_build/RTE/_test.Release_FVP_A5Neon/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'test.Release+FVP_A5Neon' + * Target: 'test.Release+FVP_A5Neon' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCA5.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Testing/cmsis_build/RTE/_test.Release_FVP_A7Neon/RTE_Components.h b/Testing/cmsis_build/RTE/_test.Release_FVP_A7Neon/RTE_Components.h new file mode 100644 index 00000000..eda3d962 --- /dev/null +++ b/Testing/cmsis_build/RTE/_test.Release_FVP_A7Neon/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'test.Release+FVP_A7Neon' + * Target: 'test.Release+FVP_A7Neon' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCA7.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Testing/cmsis_build/RTE/_test.Release_FVP_A9Neon/RTE_Components.h b/Testing/cmsis_build/RTE/_test.Release_FVP_A9Neon/RTE_Components.h new file mode 100644 index 00000000..e0dcb46e --- /dev/null +++ b/Testing/cmsis_build/RTE/_test.Release_FVP_A9Neon/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'test.Release+FVP_A9Neon' + * Target: 'test.Release+FVP_A9Neon' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCA9.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Testing/cmsis_build/build.sh b/Testing/cmsis_build/build.sh index c5d77e50..438594b3 100644 --- a/Testing/cmsis_build/build.sh +++ b/Testing/cmsis_build/build.sh @@ -1,19 +1,13 @@ - - -cbuild "test.Release+VHT_M0P.cprj" --outdir=Objects --intdir=Tmp - -cbuild "test.Release+VHT_M23.cprj" --outdir=Objects --intdir=Tmp - -cbuild "test.Release+VHT_M3.cprj" --outdir=Objects --intdir=Tmp - -cbuild "test.Release+VHT_M4.cprj" --outdir=Objects --intdir=Tmp - -cbuild "test.Release+VHT_M7.cprj" --outdir=Objects --intdir=Tmp - -cbuild "test.Release+VHT_M33.cprj" --outdir=Objects --intdir=Tmp - -cbuild "test.Release+VHT-Corstone-300.cprj" --outdir=Objects --intdir=Tmp - -cbuild "test.Release+VHT-Corstone-310.cprj" --outdir=Objects --intdir=Tmp - -cbuild "test.Release+FVP_M55.cprj" --outdir=Objects --intdir=Tmp +# cbuild "test.Release+VHT_M0P.cprj" --outdir=Objects --intdir=Tmp +# cbuild "test.Release+VHT_M23.cprj" --outdir=Objects --intdir=Tmp +# cbuild "test.Release+VHT_M3.cprj" --outdir=Objects --intdir=Tmp +# cbuild "test.Release+VHT_M4.cprj" --outdir=Objects --intdir=Tmp +# cbuild "test.Release+VHT_M7.cprj" --outdir=Objects --intdir=Tmp +# cbuild "test.Release+VHT_M33.cprj" --outdir=Objects --intdir=Tmp +#cbuild "test.Release+VHT-Corstone-300.cprj" --outdir=Objects --intdir=Tmp +# cbuild "test.Release+VHT-Corstone-310.cprj" --outdir=Objects --intdir=Tmp +# cbuild "test.Release+FVP_M55.cprj" --outdir=Objects --intdir=Tmp + +cbuild "test.Release+FVP_A5Neon.cprj" --outdir=Objects --intdir=Tmp +#cbuild "test.Release+FVP_A7Neon.cprj" --outdir=Objects --intdir=Tmp +#cbuild "test.Release+FVP_A9Neon.cprj" --outdir=Objects --intdir=Tmp diff --git a/Testing/cmsis_build/configs/ARMCA5neon_config.txt b/Testing/cmsis_build/configs/ARMCA5neon_config.txt new file mode 100644 index 00000000..9a52df0f --- /dev/null +++ b/Testing/cmsis_build/configs/ARMCA5neon_config.txt @@ -0,0 +1,21 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cluster.cpu0.ase-present=1 # (bool , init-time) default = '1' : Set whether model has NEON support +cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false +cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true +cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] +cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] +cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] +cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] +cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls +cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. +cluster.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation +cluster.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation +#---------------------------------------------------------------------------------------------- diff --git a/Testing/cmsis_build/configs/ARMCA7neon_config.txt b/Testing/cmsis_build/configs/ARMCA7neon_config.txt new file mode 100644 index 00000000..fbb6de9e --- /dev/null +++ b/Testing/cmsis_build/configs/ARMCA7neon_config.txt @@ -0,0 +1,22 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether CT model has been built with VFP support +cluster.cpu0.ase-present=1 # (bool , init-time) default = '1' : Set whether CT model has been built with NEON support +cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false +cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true +cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] +cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] +cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] +cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] +cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls +cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. +cluster.l1_icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L1 I-cache has stateful implementation +cluster.l1_dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L1 D-cache has stateful implementation +cluster.l2_cache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L2 cache has stateful implementation +#---------------------------------------------------------------------------------------------- diff --git a/Testing/cmsis_build/configs/ARMCA9neon_config.txt b/Testing/cmsis_build/configs/ARMCA9neon_config.txt new file mode 100644 index 00000000..b1d33d44 --- /dev/null +++ b/Testing/cmsis_build/configs/ARMCA9neon_config.txt @@ -0,0 +1,21 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cluster.cpu0.ase-present=1 # (bool , init-time) default = '1' : Set whether model has NEON support +cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false +cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true +cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] +cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] +cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] +cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] +cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls +cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] +cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. +cluster.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation +cluster.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation +#---------------------------------------------------------------------------------------------- diff --git a/Testing/cmsis_build/runarmds.bat b/Testing/cmsis_build/runarmds.bat new file mode 100644 index 00000000..77c2dceb --- /dev/null +++ b/Testing/cmsis_build/runarmds.bat @@ -0,0 +1,11 @@ +"C:\Program Files\ARM\Development Studio 2022.0\bin\FVP_VE_Cortex-A5x1.exe" ^ + -f configs/ARMCA5neon_config.txt ^ + Objects\test.Release+FVP_A5Neon.axf + +REM "C:\Program Files\ARM\Development Studio 2022.0\bin\FVP_VE_Cortex-A7x1.exe" ^ +REM -f configs/ARMCA7neon_config.txt ^ +REM Objects\test.Release+FVP_A7Neon.axf + +REM "C:\Program Files\ARM\Development Studio 2022.0\bin\FVP_VE_Cortex-A9x1.exe" ^ +REM -f configs/ARMCA9neon_config.txt ^ +REM Objects\test.Release+FVP_A9Neon.axf \ No newline at end of file diff --git a/Testing/cmsis_build/runkeil.bat b/Testing/cmsis_build/runkeil.bat index f8e5d165..e6ea2aba 100644 --- a/Testing/cmsis_build/runkeil.bat +++ b/Testing/cmsis_build/runkeil.bat @@ -31,10 +31,10 @@ REM C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-310.exe ^ REM -f configs/ARM_VHT_Corstone_310_config.txt ^ REM -a cpu0="Objects\test.Release+VHT-Corstone-310.axf" -REM C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ -REM -f configs/ARM_VHT_Corstone_300_config.txt ^ -REM -a cpu0="Objects\test.Release+VHT-Corstone-300.axf" +C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ + -f configs/ARM_VHT_Corstone_300_config.txt ^ + -a cpu0="Objects\test.Release+VHT-Corstone-300.axf" -C:\Keil_v5\ARM\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M55_MDK.exe ^ - -f configs/ARM_VHT_MPS2_M55_config.txt ^ - Objects\test.Release+FVP_M55.axf \ No newline at end of file +REM C:\Keil_v5\ARM\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M55_MDK.exe ^ +REM -f configs/ARM_VHT_MPS2_M55_config.txt ^ +REM Objects\test.Release+FVP_M55.axf \ No newline at end of file diff --git a/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj b/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj new file mode 100644 index 00000000..eb18ac16 --- /dev/null +++ b/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj @@ -0,0 +1,167 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + EMBEDDED;NORMALFVP;CORTEXA + ../FrameworkInclude;../GeneratedInclude;../Include/Tests + + + + + + ARM_MATH_NEON + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj b/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj new file mode 100644 index 00000000..418cc645 --- /dev/null +++ b/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj @@ -0,0 +1,167 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + EMBEDDED;NORMALFVP;CORTEXA + ../FrameworkInclude;../GeneratedInclude;../Include/Tests + + + + + + ARM_MATH_NEON + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Testing/cmsis_build/test.Release+FVP_A9Neon.cprj b/Testing/cmsis_build/test.Release+FVP_A9Neon.cprj new file mode 100644 index 00000000..f6244160 --- /dev/null +++ b/Testing/cmsis_build/test.Release+FVP_A9Neon.cprj @@ -0,0 +1,167 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + EMBEDDED;NORMALFVP;CORTEXA + ../FrameworkInclude;../GeneratedInclude;../Include/Tests + + + + + + ARM_MATH_AUTOVECTORIZE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Testing/cmsis_build/test.Release+FVP_M55.cprj b/Testing/cmsis_build/test.Release+FVP_M55.cprj index a9ddab52..662be67f 100644 --- a/Testing/cmsis_build/test.Release+FVP_M55.cprj +++ b/Testing/cmsis_build/test.Release+FVP_M55.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -21,7 +21,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj b/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj index 4dcb8f20..e8b9f2e9 100644 --- a/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj +++ b/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -22,7 +22,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj b/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj index 61494ef0..b5181e8b 100644 --- a/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj +++ b/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -22,7 +22,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.Release+VHT_M0P.cprj b/Testing/cmsis_build/test.Release+VHT_M0P.cprj index c96e24f4..0287e4db 100644 --- a/Testing/cmsis_build/test.Release+VHT_M0P.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M0P.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -21,7 +21,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.Release+VHT_M23.cprj b/Testing/cmsis_build/test.Release+VHT_M23.cprj index 91841ba0..8b49d769 100644 --- a/Testing/cmsis_build/test.Release+VHT_M23.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M23.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -21,7 +21,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.Release+VHT_M3.cprj b/Testing/cmsis_build/test.Release+VHT_M3.cprj index ef58fefa..28e198eb 100644 --- a/Testing/cmsis_build/test.Release+VHT_M3.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M3.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -21,7 +21,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.Release+VHT_M33.cprj b/Testing/cmsis_build/test.Release+VHT_M33.cprj index afaac719..ed505a52 100644 --- a/Testing/cmsis_build/test.Release+VHT_M33.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M33.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -21,7 +21,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.Release+VHT_M4.cprj b/Testing/cmsis_build/test.Release+VHT_M4.cprj index cabf526d..2a39cda3 100644 --- a/Testing/cmsis_build/test.Release+VHT_M4.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M4.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -21,7 +21,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.Release+VHT_M7.cprj b/Testing/cmsis_build/test.Release+VHT_M7.cprj index 1f8f5148..f5b73c4b 100644 --- a/Testing/cmsis_build/test.Release+VHT_M7.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M7.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -21,7 +21,7 @@ - CORTEXM;EMBEDDED;NORMALFVP + EMBEDDED;NORMALFVP;CORTEXM ../FrameworkInclude;../GeneratedInclude;../Include/Tests diff --git a/Testing/cmsis_build/test.cproject.yml b/Testing/cmsis_build/test.cproject.yml index b2882e80..db73b9c3 100644 --- a/Testing/cmsis_build/test.cproject.yml +++ b/Testing/cmsis_build/test.cproject.yml @@ -123,10 +123,47 @@ project: components: - component: ARM::CMSIS:CORE - component: ARM::CMSIS:DSP&Source@1.10.1 + not-for-type: + - +FVP_A5Neon + - +FVP_A7Neon + - +FVP_A9Neon + # CMSIS-DSP cannot be built with Neon intrinsics for A9 + # because of lack of Fused MAC on A9 + - component: ARM::CMSIS:DSP&Source@1.10.1 + defines: + - ARM_MATH_NEON + for-type: + - +FVP_A5Neon + - +FVP_A7Neon + # On A9, CMSIS-DSP is built with auto-vectorization + # but no use of Neon intrinsics + - component: ARM::CMSIS:DSP&Source@1.10.1 + defines: + - ARM_MATH_AUTOVECTORIZE + for-type: + - +FVP_A9Neon - component: Device:Startup&C Startup not-for-type: - +VHT-Corstone-300 - +VHT-Corstone-310 + - +FVP_A5Neon + - +FVP_A7Neon + - +FVP_A9Neon + - component: Device:Startup + for-type: + - +FVP_A5Neon + - +FVP_A7Neon + - +FVP_A9Neon + - component: Device:IRQ Controller + for-type: + - +FVP_A5Neon + - +FVP_A7Neon + - +FVP_A9Neon + - component: Device:OS Tick + for-type: + - +FVP_A5Neon + - +FVP_A7Neon + - +FVP_A9Neon - component: ARM::Device:Definition for-type: - +VHT-Corstone-300 diff --git a/Testing/cmsis_build/test.csolution_ac6.yml b/Testing/cmsis_build/test.csolution_ac6.yml index b377ad9c..5f0b876c 100644 --- a/Testing/cmsis_build/test.csolution_ac6.yml +++ b/Testing/cmsis_build/test.csolution_ac6.yml @@ -2,9 +2,13 @@ solution: compiler: AC6 misc: - C: - - -std=c11 -Ofast -ffast-math + - -std=c11 + - -Ofast + - -ffast-math - CPP: - - -std=c++11 -Ofast -ffast-math + - -std=c++11 + - -Ofast + - -ffast-math - ASM: - -masm=auto - Link: @@ -19,7 +23,6 @@ solution: - ../GeneratedInclude - ../Include/Tests defines: - - CORTEXM - EMBEDDED - NORMALFVP @@ -33,30 +36,74 @@ solution: target-types: - type: VHT-Corstone-310 device: ARM::SSE-310-MPS3 + defines: + - CORTEXM - type: VHT-Corstone-300 device: ARM::SSE-300-MPS3 + defines: + - CORTEXM - type: FVP_M55 device: ARMCM55 + defines: + - CORTEXM - type: VHT_M33 device: ARMCM33_DSP_FP + defines: + - CORTEXM - type: VHT_M7 device: ARMCM7_DP + defines: + - CORTEXM - type: VHT_M4 device: ARMCM4_FP + defines: + - CORTEXM - type: VHT_M3 device: ARMCM3 + defines: + - CORTEXM - type: VHT_M23 device: ARMCM23 + defines: + - CORTEXM - type: VHT_M0P device: ARMCM0P + defines: + - CORTEXM + +# ARMCA5, ARMCA7 and ARMCA9 are not configured +# with Neon in the pack. +# And the standard .cmake in CMSIS Build tools +# is not supporting Cortex-A yet. +# Since the goal is to run the Neon code of CMSIS-DSP, +# we have added Cortex-A support to the .cmake +# and forced Neon support without taking into account +# the FPU variable from the pack. +# If you want to build those targets, you'll have to add +# Cortex-A support to the .cmake of CMSIS Build tools +# in the same way (forcing Neon) + - type: FVP_A5Neon + device: ARMCA5 + defines: + - CORTEXA + + - type: FVP_A7Neon + device: ARMCA7 + defines: + - CORTEXA + + - type: FVP_A9Neon + device: ARMCA9 + defines: + - CORTEXA build-types: - type: Release diff --git a/Testing/cmsis_build/test.csolution_gcc.yml b/Testing/cmsis_build/test.csolution_gcc.yml index f2ae7ef1..01ee996a 100644 --- a/Testing/cmsis_build/test.csolution_gcc.yml +++ b/Testing/cmsis_build/test.csolution_gcc.yml @@ -17,7 +17,6 @@ solution: - ../GeneratedInclude - ../Include/Tests defines: - - CORTEXM - EMBEDDED - NORMALFVP @@ -29,6 +28,10 @@ solution: - pack: Keil::ARM_Compiler@1.7.2 target-types: +# There is not yet any gcc support in the pack +# for Corstone. +# V2M_MPS3_SSE_300_BSP@1.3.0 +# ARM::V2M_MPS3_SSE_310_BSP@1.0.0 #- type: VHT-Corstone-310 # device: ARM::SSE-310-MPS3 @@ -37,24 +40,69 @@ solution: - type: FVP_M55 device: ARMCM55 + defines: + - CORTEXM - type: VHT_M33 device: ARMCM33_DSP_FP + defines: + - CORTEXM - type: VHT_M7 device: ARMCM7_DP + defines: + - CORTEXM - type: VHT_M4 device: ARMCM4_FP + defines: + - CORTEXM - type: VHT_M3 device: ARMCM3 + defines: + - CORTEXM - type: VHT_M23 device: ARMCM23 + defines: + - CORTEXM - type: VHT_M0P device: ARMCM0P + defines: + - CORTEXM + +# ARMCA5, ARMCA7 and ARMCA9 are not configured +# with Neon in the pack. +# And the standard .cmake in CMSIS Build tools +# is not supporting Cortex-A yet. +# Since the goal is to run the Neon code of CMSIS-DSP, +# we have added Cortex-A support to the .cmake +# and forced Neon support without taking into account +# the FPU variable from the pack. +# If you want to build those targets, you'll have to add +# Cortex-A support to the .cmake of CMSIS Build tools +# in the same way (forcing Neon) +# +# Also, the packs have an issue with the scatter file for gcc +# with is categorized as "Other" instead of "linkerScript". +# So those configurations are disabled for now. +# ARM::CMSIS@5.9.0 + #- type: FVP_A5Neon + # device: ARMCA5 + # defines: + # - CORTEXA + # + #- type: FVP_A7Neon + # device: ARMCA7 + # defines: + # - CORTEXA +# + #- type: FVP_A9Neon + # device: ARMCA9 + # defines: + # - CORTEXA build-types: - type: Release diff --git a/Testing/processResult.py b/Testing/processResult.py index 327ad4f9..40bfe9f5 100644 --- a/Testing/processResult.py +++ b/Testing/processResult.py @@ -102,7 +102,10 @@ class TextFormatter: p=Fore.RED + "FAILED" + Style.RESET_ALL if passed == 1: p= Fore.GREEN + "PASSED" + Style.RESET_ALL - print("%s%s %s(%s - %d)%s : %s (cycles = %d)" % (ident,message,Style.BRIGHT,func,theId,Style.RESET_ALL,p,cycles)) + if cycles > 0: + print("%s%s %s(%s - %d)%s : %s (cycles = %d)" % (ident,message,Style.BRIGHT,func,theId,Style.RESET_ALL,p,cycles)) + else: + print("%s%s %s(%s - %d)%s : %s" % (ident,message,Style.BRIGHT,func,theId,Style.RESET_ALL,p)) if params: print("%s %s" % (ident,params)) if passed != 1: