From bc3b6d0e2fed374ff378ea2e03121074b0f799c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20G=C3=BCnther?= Date: Fri, 16 Dec 2016 11:25:05 +0100 Subject: [PATCH] DSP ARMv8M preparation. --- Include/arm_math.h | 57 +- Projects/ARM/arm_cortexM_math.uvoptx | 1120 +- Projects/ARM/arm_cortexM_math.uvprojx | 12603 ++++++++++++++++- Projects/ARM/arm_cortexM_math_Build.bat | 76 +- Projects/GCC/arm_cortexM_math.uvoptx | 1131 +- Projects/GCC/arm_cortexM_math.uvprojx | 11866 +++++++++++++++- Projects/GCC/arm_cortexM_math_Build.bat | 76 +- Source/TransformFunctions/arm_bitreversal2.S | 6 +- 8 files changed, 26698 insertions(+), 237 deletions(-) diff --git a/Include/arm_math.h b/Include/arm_math.h index 67192708..f1ff02e2 100644 --- a/Include/arm_math.h +++ b/Include/arm_math.h @@ -1,8 +1,8 @@ /* ---------------------------------------------------------------------- * Copyright (C) 2010-2016 ARM Limited. All rights reserved. * -* $Date: 22. October 2016 -* $Revision: V1.4.5 e +* $Date: 28. October 2016 +* $Revision: V1.4.5 f * * Project: CMSIS DSP Library * Title: arm_math.h @@ -300,8 +300,10 @@ #if defined(ARM_MATH_CM7) #include "core_cm7.h" + #define ARM_MATH_DSP #elif defined (ARM_MATH_CM4) #include "core_cm4.h" + #define ARM_MATH_DSP #elif defined (ARM_MATH_CM3) #include "core_cm3.h" #elif defined (ARM_MATH_CM0) @@ -310,8 +312,16 @@ #elif defined (ARM_MATH_CM0PLUS) #include "core_cm0plus.h" #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif #else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" #endif #undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ @@ -331,7 +341,7 @@ extern "C" #define DELTA_Q15 0x5 #define INDEX_MASK 0x0000003F #ifndef PI -#define PI 3.14159265358979f + #define PI 3.14159265358979f #endif /** @@ -458,7 +468,8 @@ extern "C" #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) #define __SIMD64(addr) (*(int64_t **) & (addr)) -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) /** * @brief definition to pack two 16 bit values. */ @@ -467,8 +478,8 @@ extern "C" #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) -#endif - +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ /** * @brief definition to pack four 8 bit values. @@ -713,7 +724,8 @@ extern "C" /* * @brief C custom defined intrinsic function for M3 and M0 processors */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) /* * @brief C custom defined QADD8 for M3 and M0 processors @@ -1042,7 +1054,34 @@ extern "C" return (sum + (int32_t) (((int64_t) x * y) >> 32)); } -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if 0 + /* + * @brief C custom defined PKHBT for unavailable DSP extension + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( + uint32_t x, + uint32_t y, + uint32_t leftshift) + { + return ( ((x ) & 0x0000FFFFUL) | + ((y << leftshift) & 0xFFFF0000UL) ); + } + + /* + * @brief C custom defined PKHTB for unavailable DSP extension + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( + uint32_t x, + uint32_t y, + uint32_t rightshift) + { + return ( ((x ) & 0xFFFF0000UL) | + ((y >> rightshift) & 0x0000FFFFUL) ); + } +#endif + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ /** diff --git a/Projects/ARM/arm_cortexM_math.uvoptx b/Projects/ARM/arm_cortexM_math.uvoptx index 2dd824bf..8e4f8bc5 100644 --- a/Projects/ARM/arm_cortexM_math.uvoptx +++ b/Projects/ARM/arm_cortexM_math.uvoptx @@ -22,7 +22,7 @@ - M0l + cortexM0l 0x4 ARM-ADS @@ -45,7 +45,7 @@ 79 66 8 - .\intermediateFiles\M0l\ + .\IntermediateFiles\cortexM0l\ 1 @@ -100,6 +100,7 @@ 1 0 0 + 1 0 @@ -156,11 +157,13 @@ 0 + 0 + 0 - M0b + cortexM0b 0x4 ARM-ADS @@ -183,7 +186,7 @@ 79 66 8 - .\intermediateFiles\M0b\ + .\IntermediateFiles\cortexM0b\ 1 @@ -238,6 +241,7 @@ 1 0 0 + 1 0 @@ -294,11 +298,13 @@ 0 + 0 + 0 - M3l + cortexM3l 0x4 ARM-ADS @@ -321,7 +327,7 @@ 79 66 8 - .\intermediateFiles\M3l\ + .\IntermediateFiles\cortexM3l\ 1 @@ -376,6 +382,7 @@ 1 0 0 + 1 0 @@ -432,11 +439,13 @@ 0 + 0 + 0 - M3b + cortexM3b 0x4 ARM-ADS @@ -459,7 +468,7 @@ 79 66 8 - .\intermediateFiles\M3b\ + .\IntermediateFiles\cortexM3b\ 1 @@ -514,6 +523,7 @@ 1 0 0 + 1 0 @@ -570,11 +580,13 @@ 0 + 0 + 0 - M4l + cortexM4l 0x4 ARM-ADS @@ -597,7 +609,7 @@ 79 66 8 - .\intermediateFiles\M4l\ + .\IntermediateFiles\cortexM4l\ 1 @@ -652,6 +664,7 @@ 1 0 0 + 1 0 @@ -708,11 +721,13 @@ 0 + 0 + 0 - M4b + cortexM4b 0x4 ARM-ADS @@ -735,7 +750,7 @@ 79 66 8 - .\intermediateFiles\M4b\ + .\IntermediateFiles\cortexM4b\ 1 @@ -790,6 +805,7 @@ 1 0 0 + 1 0 @@ -846,11 +862,13 @@ 0 + 0 + 0 - M4lf + cortexM4lf 0x4 ARM-ADS @@ -873,7 +891,7 @@ 79 66 8 - .\intermediateFiles\M4lf\ + .\IntermediateFiles\cortexM4lf\ 1 @@ -928,6 +946,7 @@ 1 0 0 + 1 0 @@ -984,11 +1003,13 @@ 0 + 0 + 0 - M4bf + cortexM4bf 0x4 ARM-ADS @@ -1011,7 +1032,7 @@ 79 66 8 - .\intermediateFiles\M4bf\ + .\IntermediateFiles\cortexM4bf\ 1 @@ -1066,6 +1087,7 @@ 1 0 0 + 1 0 @@ -1122,11 +1144,13 @@ 0 + 0 + 0 - M7l + cortexM7l 0x4 ARM-ADS @@ -1149,7 +1173,7 @@ 79 66 8 - .\IntermediateFiles\M7l\ + .\IntermediateFiles\cortexM7l\ 1 @@ -1204,6 +1228,7 @@ 1 0 0 + 1 0 @@ -1260,11 +1285,13 @@ 0 + 0 + 0 - M7b + cortexM7b 0x4 ARM-ADS @@ -1287,7 +1314,7 @@ 79 66 8 - .\IntermediateFiles\M7b\ + .\IntermediateFiles\cortexM7b\ 1 @@ -1342,6 +1369,7 @@ 1 0 0 + 1 0 @@ -1398,11 +1426,13 @@ 0 + 0 + 0 - M7lfsp + cortexM7lfsp 0x4 ARM-ADS @@ -1425,7 +1455,7 @@ 79 66 8 - .\IntermediateFiles\M7lfsp\ + .\IntermediateFiles\cortexM7lfsp\ 1 @@ -1480,6 +1510,7 @@ 1 0 0 + 1 0 @@ -1536,11 +1567,13 @@ 0 + 0 + 0 - M7bfsp + cortexM7bfsp 0x4 ARM-ADS @@ -1563,7 +1596,7 @@ 79 66 8 - .\IntermediateFiles\M7bfsp\ + .\IntermediateFiles\cortexM7bfsp\ 1 @@ -1618,6 +1651,7 @@ 1 0 0 + 1 0 @@ -1674,11 +1708,13 @@ 0 + 0 + 0 - M7lfdp + cortexM7lfdp 0x4 ARM-ADS @@ -1701,7 +1737,7 @@ 79 66 8 - .\IntermediateFiles\M7lfdp\ + .\IntermediateFiles\cortexM7lfdp\ 1 @@ -1756,6 +1792,7 @@ 1 0 0 + 1 0 @@ -1812,11 +1849,13 @@ 0 + 0 + 0 - M7bfdp + cortexM7bfdp 0x4 ARM-ADS @@ -1839,7 +1878,7 @@ 79 66 8 - .\IntermediateFiles\M7bfdp\ + .\IntermediateFiles\cortexM7bfdp\ 1 @@ -1894,6 +1933,7 @@ 1 0 0 + 1 0 @@ -1950,6 +1990,1030 @@ 0 + 0 + 0 + + + + + ARMv8MBLl + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 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-FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLlfdp + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\IntermediateFiles\ARMv8MMLlfdp\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLld + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\IntermediateFiles\ARMv8MMLld\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLldfsp + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\IntermediateFiles\ARMv8MMLldfsp\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLldfdp + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\IntermediateFiles\ARMv8MMLldfdp\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 diff --git a/Projects/ARM/arm_cortexM_math.uvprojx b/Projects/ARM/arm_cortexM_math.uvprojx index 9f7d5a22..ee515c6b 100644 --- a/Projects/ARM/arm_cortexM_math.uvprojx +++ b/Projects/ARM/arm_cortexM_math.uvprojx @@ -7,15 +7,15 @@ - M0l + cortexM0l 0x4 ARM-ADS - 5060300::V5.06 update 3 (build 300)::ARMCC + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM0 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE @@ -47,14 +47,14 @@ 0 1 - .\IntermediateFiles\M0l\ + .\IntermediateFiles\cortexM0l\ arm_cortexM0l_math 0 1 0 1 1 - .\intermediateFiles\M0l\ + .\IntermediateFiles\cortexM0l\ 1 0 0 @@ -1789,14 +1789,15 @@ - M0b + cortexM0b 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM0 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE @@ -1828,14 +1829,14 @@ 0 1 - .\IntermediateFiles\M0b\ + .\IntermediateFiles\cortexM0b\ arm_cortexM0b_math 0 1 0 1 1 - .\intermediateFiles\M0b\ + .\IntermediateFiles\cortexM0b\ 1 0 0 @@ -3570,15 +3571,15 @@ - M3l + cortexM3l 0x4 ARM-ADS - 5060020::V5.06 (build 20)::ARMCC + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM3 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE @@ -3610,14 +3611,14 @@ 0 1 - .\IntermediateFiles\M3l\ + .\IntermediateFiles\cortexM3l\ arm_cortexM3l_math 0 1 0 1 1 - .\intermediateFiles\M3l\ + .\IntermediateFiles\cortexM3l\ 1 0 0 @@ -5352,14 +5353,15 @@ - M3b + cortexM3b 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM3 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE @@ -5391,14 +5393,14 @@ 0 1 - .\IntermediateFiles\M3b\ + .\IntermediateFiles\cortexM3b\ arm_cortexM3b_math 0 1 0 1 1 - .\intermediateFiles\M3b\ + .\IntermediateFiles\cortexM3b\ 1 0 0 @@ -7133,14 +7135,15 @@ - M4l + cortexM4l 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM4 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE @@ -7172,14 +7175,14 @@ 0 1 - .\IntermediateFiles\M4l\ + .\IntermediateFiles\cortexM4l\ arm_cortexM4l_math 0 1 0 1 1 - .\intermediateFiles\M4l\ + .\IntermediateFiles\cortexM4l\ 1 0 0 @@ -8914,14 +8917,15 @@ - M4b + cortexM4b 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM4 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE @@ -8953,14 +8957,14 @@ 0 1 - .\IntermediateFiles\M4b\ + .\IntermediateFiles\cortexM4b\ arm_cortexM4b_math 0 1 0 1 1 - .\intermediateFiles\M4b\ + .\IntermediateFiles\cortexM4b\ 1 0 0 @@ -10695,15 +10699,15 @@ - M4lf + cortexM4lf 0x4 ARM-ADS - 5060020::V5.06 (build 20)::ARMCC + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM4_FP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE @@ -10735,14 +10739,14 @@ 0 1 - .\IntermediateFiles\M4lf\ + .\IntermediateFiles\cortexM4lf\ arm_cortexM4lf_math 0 1 0 1 1 - .\intermediateFiles\M4lf\ + .\IntermediateFiles\cortexM4lf\ 1 0 0 @@ -12477,14 +12481,15 @@ - M4bf + cortexM4bf 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM4_FP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE @@ -12516,14 +12521,14 @@ 0 1 - .\IntermediateFiles\M4bf\ + .\IntermediateFiles\cortexM4bf\ arm_cortexM4bf_math 0 1 0 1 1 - .\intermediateFiles\M4bf\ + .\IntermediateFiles\cortexM4bf\ 1 0 0 @@ -14258,14 +14263,15 @@ - M7l + cortexM7l 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM7 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE @@ -14297,14 +14303,14 @@ 0 1 - .\IntermediateFiles\M7l\ + .\IntermediateFiles\cortexM7l\ arm_cortexM7l_math 0 1 0 1 1 - .\IntermediateFiles\M7l\ + .\IntermediateFiles\cortexM7l\ 1 0 0 @@ -16039,14 +16045,15 @@ - M7b + cortexM7b 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM7 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE @@ -16078,14 +16085,14 @@ 0 1 - .\IntermediateFiles\M7b\ + .\IntermediateFiles\cortexM7b\ arm_cortexM7b_math 0 1 0 1 1 - .\IntermediateFiles\M7b\ + .\IntermediateFiles\cortexM7b\ 1 0 0 @@ -17820,14 +17827,15 @@ - M7lfsp + cortexM7lfsp 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM7_SP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE @@ -17859,14 +17867,14 @@ 0 1 - .\IntermediateFiles\M7lfsp\ + .\IntermediateFiles\cortexM7lfsp\ arm_cortexM7lfsp_math 0 1 0 1 1 - .\IntermediateFiles\M7lfsp\ + .\IntermediateFiles\cortexM7lfsp\ 1 0 0 @@ -19601,14 +19609,15 @@ - M7bfsp + cortexM7bfsp 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM7_SP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE @@ -19640,14 +19649,14 @@ 0 1 - .\IntermediateFiles\M7bfsp\ + .\IntermediateFiles\cortexM7bfsp\ arm_cortexM7bfsp_math 0 1 0 1 1 - .\IntermediateFiles\M7bfsp\ + .\IntermediateFiles\cortexM7bfsp\ 1 0 0 @@ -21382,14 +21391,15 @@ - M7lfdp + cortexM7lfdp 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM7_DP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE @@ -21421,14 +21431,14 @@ 0 1 - .\IntermediateFiles\M7lfdp\ + .\IntermediateFiles\cortexM7lfdp\ arm_cortexM7lfdp_math 0 1 0 1 1 - .\IntermediateFiles\M7lfdp\ + .\IntermediateFiles\cortexM7lfdp\ 1 0 0 @@ -23163,14 +23173,15 @@ - M7bfdp + cortexM7bfdp 0x4 ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC ARMCM7_DP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE @@ -23202,14 +23213,14 @@ 0 1 - .\IntermediateFiles\M7bfdp\ + .\IntermediateFiles\cortexM7bfdp\ arm_cortexM7bfdp_math 0 1 0 1 1 - .\IntermediateFiles\M7bfdp\ + .\IntermediateFiles\cortexM7bfdp\ 1 0 0 @@ -24943,6 +24954,12480 @@ + + ARMv8MBLl + 0x4 + ARM-ADS + 6060000::V6.6::.\ARMCLANG + + + ARMv8MBL + ARM + ARM.CMSIS.5.0.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMv8MBL$Device\ARM\ARMv8MBL\Include\ARMv8MBL.h + + + + + + + + + + $$Device:ARMv8MBL$Device\ARM\SVD\ARMv8MBL.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\ARMv8MBLl\ + arm_ARMv8MBLl_math + 0 + 1 + 0 + 1 + 1 + .\IntermediateFiles\ARMv8MBLl\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd.exe /C copy "!L" "..\..\..\Lib\ARM\" + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pV8MBL + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "ARMV8MBL" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_ARMV8MBL, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE + + ..\..\Include;..\..\..\Core\Include;..\..\..\Include + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + ARM_MATH_ARMV8MBL __CC_ARM + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x00000000 + + + + + + + + + + + + + BasicMathFunctions + + + arm_abs_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_abs_f32.c + + + arm_abs_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_abs_q7.c + + + arm_abs_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_abs_q15.c + + + arm_abs_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_abs_q31.c + + + arm_add_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_add_f32.c + + + arm_add_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_add_q7.c + + + arm_add_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_add_q15.c + + + arm_add_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_add_q31.c + + + arm_dot_prod_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_dot_prod_f32.c + + + arm_dot_prod_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_dot_prod_q7.c + + + arm_dot_prod_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_dot_prod_q15.c + + + arm_dot_prod_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_dot_prod_q31.c + + + arm_mult_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_mult_f32.c + + + arm_mult_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_mult_q7.c + + + arm_mult_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_mult_q15.c + + + arm_mult_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_mult_q31.c + + + arm_negate_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_negate_f32.c + + + arm_negate_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_negate_q7.c + + + arm_negate_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_negate_q15.c + + + arm_negate_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_negate_q31.c + + + arm_offset_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_offset_f32.c + + + arm_offset_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_offset_q7.c + + + arm_offset_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_offset_q15.c + + + arm_offset_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_offset_q31.c + + + arm_scale_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_scale_f32.c + + + arm_scale_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_scale_q7.c + + + arm_scale_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_scale_q15.c + + + arm_scale_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_scale_q31.c + + + arm_shift_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_shift_q7.c + + + arm_shift_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_shift_q15.c + + + arm_shift_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_shift_q31.c + + + arm_sub_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_sub_f32.c + + + arm_sub_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_sub_q7.c + + + arm_sub_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_sub_q15.c + + + arm_sub_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_sub_q31.c + + + + + FastMathFunctions + + + arm_cos_f32.c + 1 + ..\..\Source\FastMathFunctions\arm_cos_f32.c + + + arm_cos_q15.c + 1 + ..\..\Source\FastMathFunctions\arm_cos_q15.c + + + arm_cos_q31.c + 1 + ..\..\Source\FastMathFunctions\arm_cos_q31.c + + + arm_sin_f32.c + 1 + ..\..\Source\FastMathFunctions\arm_sin_f32.c + + + arm_sin_q15.c + 1 + ..\..\Source\FastMathFunctions\arm_sin_q15.c + + + arm_sin_q31.c + 1 + ..\..\Source\FastMathFunctions\arm_sin_q31.c + + + arm_sqrt_q15.c + 1 + ..\..\Source\FastMathFunctions\arm_sqrt_q15.c + + + arm_sqrt_q31.c + 1 + ..\..\Source\FastMathFunctions\arm_sqrt_q31.c + + + + + ComplexMathFunctions + + + arm_cmplx_conj_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_conj_f32.c + + + arm_cmplx_conj_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_conj_q15.c + + + arm_cmplx_conj_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_conj_q31.c + + + arm_cmplx_dot_prod_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_dot_prod_f32.c + + + arm_cmplx_dot_prod_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_dot_prod_q15.c + + + arm_cmplx_dot_prod_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_dot_prod_q31.c + + + arm_cmplx_mag_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_f32.c + + + arm_cmplx_mag_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_q15.c + + + arm_cmplx_mag_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_q31.c + + + arm_cmplx_mag_squared_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_squared_f32.c + + + arm_cmplx_mag_squared_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_squared_q15.c + + + arm_cmplx_mag_squared_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_squared_q31.c + + + arm_cmplx_mult_cmplx_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_f32.c + + + arm_cmplx_mult_cmplx_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_q15.c + + + arm_cmplx_mult_cmplx_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_q31.c + + + arm_cmplx_mult_real_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_real_f32.c + + + arm_cmplx_mult_real_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_real_q15.c + + + arm_cmplx_mult_real_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_real_q31.c + + + + + FilteringFunctions + + + arm_biquad_cascade_df1_32x64_init_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_32x64_init_q31.c + + + arm_biquad_cascade_df1_32x64_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_32x64_q31.c + + + arm_biquad_cascade_df1_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_f32.c + + + arm_biquad_cascade_df1_fast_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_fast_q15.c + + + arm_biquad_cascade_df1_fast_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_fast_q31.c + + + arm_biquad_cascade_df1_init_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_init_f32.c + + + arm_biquad_cascade_df1_init_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_init_q15.c + + + arm_biquad_cascade_df1_init_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_init_q31.c + + + arm_biquad_cascade_df1_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_q15.c + + + arm_biquad_cascade_df1_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_q31.c + + + arm_biquad_cascade_df2T_init_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df2T_init_f32.c + + + arm_conv_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_f32.c + + + arm_conv_fast_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_fast_q15.c + + + arm_conv_fast_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_fast_q31.c + + + arm_conv_partial_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_partial_f32.c + + + arm_conv_partial_fast_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_partial_fast_q15.c + + + arm_conv_partial_fast_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_partial_fast_q31.c + + + arm_conv_partial_q7.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_partial_q7.c + + + arm_conv_partial_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_partial_q15.c + + + arm_conv_partial_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_partial_q31.c + + + arm_conv_q7.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_q7.c + + + arm_conv_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_q15.c + + + arm_conv_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_conv_q31.c + + + arm_correlate_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_correlate_f32.c + + + arm_correlate_fast_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_correlate_fast_q15.c + + + arm_correlate_fast_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_correlate_fast_q31.c + + + arm_correlate_q7.c + 1 + ..\..\Source\FilteringFunctions\arm_correlate_q7.c + + + arm_correlate_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_correlate_q15.c + + + arm_correlate_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_correlate_q31.c + + + arm_fir_decimate_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_decimate_f32.c + + + arm_fir_decimate_fast_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_decimate_fast_q15.c + + + arm_fir_decimate_fast_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_decimate_fast_q31.c + + + arm_fir_decimate_init_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_decimate_init_f32.c + + + arm_fir_decimate_init_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_decimate_init_q15.c + + + arm_fir_decimate_init_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_decimate_init_q31.c + + + arm_fir_decimate_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_decimate_q15.c + + + arm_fir_decimate_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_decimate_q31.c + + + arm_fir_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_f32.c + + + arm_fir_fast_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_fast_q15.c + + + arm_fir_fast_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_fast_q31.c + + + arm_fir_init_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_init_f32.c + + + arm_fir_init_q7.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_init_q7.c + + + arm_fir_init_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_init_q15.c + + + arm_fir_init_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_init_q31.c + + + arm_fir_interpolate_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_interpolate_f32.c + + + arm_fir_interpolate_init_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_interpolate_init_f32.c + + + arm_fir_interpolate_init_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_interpolate_init_q15.c + + + arm_fir_interpolate_init_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_interpolate_init_q31.c + + + arm_fir_interpolate_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_interpolate_q15.c + + + arm_fir_interpolate_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_interpolate_q31.c + + + arm_fir_lattice_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_lattice_f32.c + + + arm_fir_lattice_init_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_lattice_init_f32.c + + + arm_fir_lattice_init_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_lattice_init_q15.c + + + arm_fir_lattice_init_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_lattice_init_q31.c + + + arm_fir_lattice_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_lattice_q15.c + + + arm_fir_lattice_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_lattice_q31.c + + + arm_fir_q7.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_q7.c + + + arm_fir_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_fir_q15.c + + + arm_fir_q31.c + 1 + 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..\..\Source\StatisticsFunctions\arm_mean_f32.c + + + arm_mean_q7.c + 1 + ..\..\Source\StatisticsFunctions\arm_mean_q7.c + + + arm_mean_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_mean_q15.c + + + arm_mean_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_mean_q31.c + + + arm_min_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_min_f32.c + + + arm_min_q7.c + 1 + ..\..\Source\StatisticsFunctions\arm_min_q7.c + + + arm_min_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_min_q15.c + + + arm_min_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_min_q31.c + + + arm_power_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_power_f32.c + + + arm_power_q7.c + 1 + ..\..\Source\StatisticsFunctions\arm_power_q7.c + + + arm_power_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_power_q15.c + + + arm_power_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_power_q31.c + + + arm_rms_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_rms_f32.c + + + arm_rms_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_rms_q15.c + + + arm_rms_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_rms_q31.c + + + arm_std_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_std_f32.c + + + arm_std_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_std_q15.c + + + arm_std_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_std_q31.c + + + arm_var_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_var_f32.c + + + arm_var_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_var_q15.c + + + arm_var_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_var_q31.c + + + + + SupportFunctions + + + arm_copy_f32.c + 1 + ..\..\Source\SupportFunctions\arm_copy_f32.c + + + arm_copy_q7.c + 1 + ..\..\Source\SupportFunctions\arm_copy_q7.c + + + arm_copy_q15.c + 1 + ..\..\Source\SupportFunctions\arm_copy_q15.c + + + arm_copy_q31.c + 1 + ..\..\Source\SupportFunctions\arm_copy_q31.c + + + arm_fill_f32.c + 1 + ..\..\Source\SupportFunctions\arm_fill_f32.c + + + arm_fill_q7.c + 1 + ..\..\Source\SupportFunctions\arm_fill_q7.c + + + arm_fill_q15.c + 1 + ..\..\Source\SupportFunctions\arm_fill_q15.c + + + arm_fill_q31.c + 1 + ..\..\Source\SupportFunctions\arm_fill_q31.c + + + arm_float_to_q7.c + 1 + ..\..\Source\SupportFunctions\arm_float_to_q7.c + + + arm_float_to_q15.c + 1 + ..\..\Source\SupportFunctions\arm_float_to_q15.c + + + arm_float_to_q31.c + 1 + ..\..\Source\SupportFunctions\arm_float_to_q31.c + + + arm_q7_to_float.c + 1 + ..\..\Source\SupportFunctions\arm_q7_to_float.c + + + arm_q7_to_q15.c + 1 + ..\..\Source\SupportFunctions\arm_q7_to_q15.c + + + arm_q7_to_q31.c + 1 + ..\..\Source\SupportFunctions\arm_q7_to_q31.c + + + arm_q15_to_float.c + 1 + ..\..\Source\SupportFunctions\arm_q15_to_float.c + + + arm_q15_to_q7.c + 1 + ..\..\Source\SupportFunctions\arm_q15_to_q7.c + + + arm_q15_to_q31.c + 1 + ..\..\Source\SupportFunctions\arm_q15_to_q31.c + + + arm_q31_to_float.c + 1 + ..\..\Source\SupportFunctions\arm_q31_to_float.c + + + arm_q31_to_q7.c + 1 + ..\..\Source\SupportFunctions\arm_q31_to_q7.c + + + arm_q31_to_q15.c + 1 + ..\..\Source\SupportFunctions\arm_q31_to_q15.c + + + + + CommonTables + + + arm_common_tables.c + 1 + ..\..\Source\CommonTables\arm_common_tables.c + + + arm_const_structs.c + 1 + ..\..\Source\CommonTables\arm_const_structs.c + + + + + diff --git a/Projects/ARM/arm_cortexM_math_Build.bat b/Projects/ARM/arm_cortexM_math_Build.bat index 1ec903f5..81d17fc2 100644 --- a/Projects/ARM/arm_cortexM_math_Build.bat +++ b/Projects/ARM/arm_cortexM_math_Build.bat @@ -6,33 +6,69 @@ echo. echo Building DSP Libraries ARM echo. echo Building DSP Library for Cortex-M0 Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M0l" -o "DspLib_M0l_build.log" -echo Building DSP Library for Cortex-M0 Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M0b" -o "DspLib_M0b_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM0l" -o "DspLib_cortexM0l_build.log" + echo Building DSP Library for Cortex-M3 Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M3l" -o "DspLib_M3l_build.log" -echo Building DSP Library for Cortex-M3 Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M3b" -o "DspLib_M3b_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM3l" -o "DspLib_cortexM3l_build.log" + echo Building DSP Library for Cortex-M4 Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M4l" -o "DspLib_M4l_build.log" -echo Building DSP Library for Cortex-M4 Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M4b" -o "DspLib_M4b_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM4l" -o "DspLib_cortexM4l_build.log" + echo Building DSP Library for Cortex-M4 with FPU Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M4lf" -o "DspLib_M4lf_build.log" -echo Building DSP Library for Cortex-M4 with FPU Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M4bf" -o "DspLib_M4bf_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM4lf" -o "DspLib_cortexM4lf_build.log" + echo Building DSP Library for Cortex-M7 Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7l" -o "DspLib_M7l_build.log" -echo Building DSP Library for Cortex-M7 Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7b" -o "DspLib_M7b_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7l" -o "DspLib_cortexM7l_build.log" + echo Building DSP Library for Cortex-M7 with single precision FPU Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7lfsp" -o "DspLib_M7lfsp_build.log" -echo Building DSP Library for Cortex-M7 with single precision FPU Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7bfsp" -o "DspLib_M7bfsp_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7lfsp" -o "DspLib_cortexM7lfsp_build.log" + echo Building DSP Library for Cortex-M7 with double precision FPU Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7lfdp" -o "DspLib_M7lfdp_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7lfdp" -o "DspLib_cortexM7lfdp_build.log" + +echo Building DSP Library for ARMv8-M Baseline Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MBLl" -o "DspLib_ARMv8MBLl_build.log" + +echo Building DSP Library for ARMv8-M Mainline Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLl" -o "DspLib_ARMv8MMLl_build.log" + +echo Building DSP Library for ARMv8-M Mainline with single precision FPU Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLlfsp" -o "DspLib_ARMv8MMLlfsp_build.log" + +echo Building DSP Library for ARMv8-M Mainline with double precision FPU Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLlfdp" -o "DspLib_ARMv8MMLlfdp_build.log" + +echo Building DSP Library for ARMv8-M Mainline with DSP Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLld" -o "DspLib_ARMv8MMLld_build.log" + +echo Building DSP Library for ARMv8-M Mainline with DSP, single precision FPU Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLldfsp" -o "DspLib_ARMv8MMLldfsp_build.log" + +echo Building DSP Library for ARMv8-M Mainline with DSP, double precision FPU Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLldfdp" -o "DspLib_ARMv8MMLldfdp_build.log" + +REM big endian libraries + +echo Building DSP Library for Cortex-M0 Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM0b" -o "DspLib_cortexM0b_build.log" + +echo Building DSP Library for Cortex-M3 Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM3b" -o "DspLib_cortexM3b_build.log" + +echo Building DSP Library for Cortex-M4 Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM4b" -o "DspLib_cortexM4b_build.log" + +echo Building DSP Library for Cortex-M4 with FPU Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM4bf" -o "DspLib_cortexM4bf_build.log" + +echo Building DSP Library for Cortex-M7 Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7b" -o "DspLib_cortexM7b_build.log" + +echo Building DSP Library for Cortex-M7 with single precision FPU Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7bfsp" -o "DspLib_cortexM7bfsp_build.log" + echo Building DSP Library for Cortex-M7 with double precision FPU Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7bfdp" -o "DspLib_M7bfdp_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7bfdp" -o "DspLib_cortexM7bfdp_build.log" echo. ECHO Deleting intermediate files diff --git a/Projects/GCC/arm_cortexM_math.uvoptx b/Projects/GCC/arm_cortexM_math.uvoptx index 0908b444..eb2f5916 100644 --- a/Projects/GCC/arm_cortexM_math.uvoptx +++ b/Projects/GCC/arm_cortexM_math.uvoptx @@ -22,7 +22,7 @@ - M0l + cortexM0l 0x3 ARM-GNU @@ -45,7 +45,7 @@ 120 65 8 - .\IntermediateFiles\M0l\ + .\IntermediateFiles\cortexM0l\ 1 @@ -100,6 +100,7 @@ 1 0 0 + 1 0 @@ -156,11 +157,13 @@ 0 + 0 + 0 - M0b + cortexM0b 0x3 ARM-GNU @@ -183,7 +186,7 @@ 120 65 8 - .\IntermediateFiles\M0b\ + .\IntermediateFiles\cortexM0b\ 1 @@ -238,6 +241,7 @@ 1 0 0 + 1 0 @@ -294,11 +298,13 @@ 0 + 0 + 0 - M3l + cortexM3l 0x3 ARM-GNU @@ -321,7 +327,7 @@ 120 65 8 - .\IntermediateFiles\M3l\ + .\IntermediateFiles\cortexM3l\ 1 @@ -376,6 +382,7 @@ 1 0 0 + 1 0 @@ -432,11 +439,13 @@ 0 + 0 + 0 - M3b + cortexM3b 0x3 ARM-GNU @@ -459,7 +468,7 @@ 120 65 8 - .\IntermediateFiles\M3b\ + .\IntermediateFiles\cortexM3b\ 1 @@ -514,6 +523,7 @@ 1 0 0 + 1 0 @@ -570,11 +580,13 @@ 0 + 0 + 0 - M4l + cortexM4l 0x3 ARM-GNU @@ -597,7 +609,7 @@ 120 65 8 - .\IntermediateFiles\M4l\ + .\IntermediateFiles\cortexM4l\ 1 @@ -652,6 +664,7 @@ 1 0 0 + 1 0 @@ -708,11 +721,13 @@ 0 + 0 + 0 - M4b + cortexM4b 0x3 ARM-GNU @@ -735,7 +750,7 @@ 120 65 8 - .\IntermediateFiles\M4b\ + .\IntermediateFiles\cortexM4b\ 1 @@ -790,6 +805,7 @@ 1 0 0 + 1 0 @@ -846,11 +862,13 @@ 0 + 0 + 0 - M4lf + cortexM4lf 0x3 ARM-GNU @@ -873,7 +891,7 @@ 120 65 8 - .\IntermediateFiles\M4lf\ + .\IntermediateFiles\cortexM4lf\ 1 @@ -928,6 +946,7 @@ 1 0 0 + 1 0 @@ -984,11 +1003,13 @@ 0 + 0 + 0 - M4bf + cortexM4bf 0x3 ARM-GNU @@ -1011,7 +1032,7 @@ 120 65 8 - .\IntermediateFiles\M4bf\ + .\IntermediateFiles\cortexM4bf\ 1 @@ -1066,6 +1087,7 @@ 1 0 0 + 1 0 @@ -1122,11 +1144,13 @@ 0 + 0 + 0 - M7l + cortexM7l 0x3 ARM-GNU @@ -1149,7 +1173,7 @@ 120 65 8 - .\IntermediateFiles\M7l\ + .\IntermediateFiles\cortexM7l\ 1 @@ -1204,6 +1228,7 @@ 1 0 0 + 1 0 @@ -1260,11 +1285,13 @@ 0 + 0 + 0 - M7b + cortexM7b 0x3 ARM-GNU @@ -1287,7 +1314,7 @@ 120 65 8 - .\IntermediateFiles\M7b\ + .\IntermediateFiles\cortexM7b\ 1 @@ -1342,6 +1369,7 @@ 1 0 0 + 1 0 @@ -1398,11 +1426,13 @@ 0 + 0 + 0 - M7lfsp + cortexM7lfsp 0x3 ARM-GNU @@ -1425,7 +1455,7 @@ 120 65 8 - .\IntermediateFiles\M7lfsp\ + .\IntermediateFiles\cortexM7lfsp\ 1 @@ -1480,6 +1510,7 @@ 1 0 0 + 1 0 @@ -1536,11 +1567,13 @@ 0 + 0 + 0 - M7bfsp + cortexM7bfsp 0x3 ARM-GNU @@ -1563,7 +1596,7 @@ 120 65 8 - .\IntermediateFiles\M7bfsp\ + .\IntermediateFiles\cortexM7bfsp\ 1 @@ -1618,6 +1651,7 @@ 1 0 0 + 1 0 @@ -1674,11 +1708,13 @@ 0 + 0 + 0 - M7lfdp + cortexM7lfdp 0x3 ARM-GNU @@ -1701,7 +1737,7 @@ 120 65 8 - .\IntermediateFiles\M7lfdp\ + .\IntermediateFiles\cortexM7lfdp\ 1 @@ -1735,8 +1771,8 @@ 7 - 1 - 0 + 0 + 1 0 0 1 @@ -1756,6 +1792,7 @@ 1 0 0 + 1 0 @@ -1770,10 +1807,15 @@ BIN\UL2CM3.DLL + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 UL2CM3 - -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + -S0 -C0 -P0 ) -FC1000 -FD20000000 @@ -1812,11 +1854,13 @@ 0 + 0 + 0 - M7bfdp + cortexM7bfdp 0x3 ARM-GNU @@ -1839,7 +1883,7 @@ 120 65 8 - .\IntermediateFiles\M7bfdp\ + .\IntermediateFiles\cortexM7bfdp\ 1 @@ -1894,6 +1938,7 @@ 1 0 0 + 1 0 @@ -1950,6 +1995,1030 @@ 0 + 0 + 0 + + + + + ARMv8MBLl + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\IntermediateFiles\ARMv8MBLl\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLl + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\IntermediateFiles\ARMv8MMLl\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLlfsp + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\IntermediateFiles\ARMv8MMLlfsp\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLlfdp + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\IntermediateFiles\ARMv8MMLlfdp\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLld + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\IntermediateFiles\ARMv8MMLld\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLldfsp + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\IntermediateFiles\ARMv8MMLldfsp\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 + + + + + ARMv8MMLldfdp + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\IntermediateFiles\ARMv8MMLldfdp\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + 0 + 0 diff --git a/Projects/GCC/arm_cortexM_math.uvprojx b/Projects/GCC/arm_cortexM_math.uvprojx index 2ff769e4..69f5e6ab 100644 --- a/Projects/GCC/arm_cortexM_math.uvprojx +++ b/Projects/GCC/arm_cortexM_math.uvprojx @@ -7,14 +7,14 @@ - M0l + cortexM0l 0x3 ARM-GNU ARMCM0 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE @@ -46,14 +46,14 @@ 0 1 - .\IntermediateFiles\M0l\ + .\IntermediateFiles\cortexM0l\ arm_cortexM0l_math 0 1 0 1 0 - .\IntermediateFiles\M0l\ + .\IntermediateFiles\cortexM0l\ 1 0 0 @@ -1683,14 +1683,14 @@ - M0b + cortexM0b 0x3 ARM-GNU ARMCM0 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE @@ -1722,14 +1722,14 @@ 0 1 - .\IntermediateFiles\M0b\ + .\IntermediateFiles\cortexM0b\ arm_cortexM0b_math 0 1 0 1 0 - .\IntermediateFiles\M0b\ + .\IntermediateFiles\cortexM0b\ 1 0 0 @@ -3359,14 +3359,14 @@ - M3l + cortexM3l 0x3 ARM-GNU ARMCM3 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE @@ -3398,14 +3398,14 @@ 0 1 - .\IntermediateFiles\M3l\ + .\IntermediateFiles\cortexM3l\ arm_cortexM3l_math 0 1 0 1 0 - .\IntermediateFiles\M3l\ + .\IntermediateFiles\cortexM3l\ 1 0 0 @@ -5035,14 +5035,14 @@ - M3b + cortexM3b 0x3 ARM-GNU ARMCM3 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE @@ -5074,14 +5074,14 @@ 0 1 - .\IntermediateFiles\M3b\ + .\IntermediateFiles\cortexM3b\ arm_cortexM3b_math 0 1 0 1 0 - .\IntermediateFiles\M3b\ + .\IntermediateFiles\cortexM3b\ 1 0 0 @@ -6711,14 +6711,14 @@ - M4l + cortexM4l 0x3 ARM-GNU ARMCM4 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE @@ -6750,14 +6750,14 @@ 0 1 - .\IntermediateFiles\M4l\ + .\IntermediateFiles\cortexM4l\ arm_cortexM4l_math 0 1 0 1 0 - .\IntermediateFiles\M4l\ + .\IntermediateFiles\cortexM4l\ 1 0 0 @@ -8387,14 +8387,14 @@ - M4b + cortexM4b 0x3 ARM-GNU ARMCM4 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE @@ -8426,14 +8426,14 @@ 0 1 - .\IntermediateFiles\M4b\ + .\IntermediateFiles\cortexM4b\ arm_cortexM4b_math 0 1 0 1 0 - .\IntermediateFiles\M4b\ + .\IntermediateFiles\cortexM4b\ 1 0 0 @@ -10063,14 +10063,14 @@ - M4lf + cortexM4lf 0x3 ARM-GNU ARMCM4_FP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE @@ -10102,14 +10102,14 @@ 0 1 - .\IntermediateFiles\M4lf\ + .\IntermediateFiles\cortexM4lf\ arm_cortexM4lf_math 0 1 0 1 0 - .\IntermediateFiles\M4lf\ + .\IntermediateFiles\cortexM4lf\ 1 0 0 @@ -10137,7 +10137,7 @@ 1 0 cmd.exe /C copy "$L\lib@L.a" "..\..\..\Lib\GCC\" - + cmd.exe /C getSizeInfo "$L\lib@L.a" "@L_SizeInfo.txt" 0 0 0 @@ -11739,14 +11739,14 @@ - M4bf + cortexM4bf 0x3 ARM-GNU ARMCM4_FP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE @@ -11778,14 +11778,14 @@ 0 1 - .\IntermediateFiles\M4bf\ + .\IntermediateFiles\cortexM4bf\ arm_cortexM4bf_math 0 1 0 1 0 - .\IntermediateFiles\M4bf\ + .\IntermediateFiles\cortexM4bf\ 1 0 0 @@ -13415,14 +13415,14 @@ - M7l + cortexM7l 0x3 ARM-GNU ARMCM7 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE @@ -13454,14 +13454,14 @@ 0 1 - .\IntermediateFiles\M7l\ + .\IntermediateFiles\cortexM7l\ arm_cortexM7l_math 0 1 0 1 0 - .\IntermediateFiles\M7l\ + .\IntermediateFiles\cortexM7l\ 1 0 0 @@ -15091,14 +15091,14 @@ - M7b + cortexM7b 0x3 ARM-GNU ARMCM7 ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE @@ -15130,14 +15130,14 @@ 0 1 - .\IntermediateFiles\M7b\ + .\IntermediateFiles\cortexM7b\ arm_cortexM7b_math 0 1 0 1 0 - .\IntermediateFiles\M7b\ + .\IntermediateFiles\cortexM7b\ 1 0 0 @@ -16767,14 +16767,14 @@ - M7lfsp + cortexM7lfsp 0x3 ARM-GNU ARMCM7_SP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE @@ -16806,14 +16806,14 @@ 0 1 - .\IntermediateFiles\M7lfsp\ + .\IntermediateFiles\cortexM7lfsp\ arm_cortexM7lfsp_math 0 1 0 1 0 - .\IntermediateFiles\M7lfsp\ + .\IntermediateFiles\cortexM7lfsp\ 1 0 0 @@ -18443,14 +18443,14 @@ - M7bfsp + cortexM7bfsp 0x3 ARM-GNU ARMCM7_SP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE @@ -18482,14 +18482,14 @@ 0 1 - .\IntermediateFiles\M7bfsp\ + .\IntermediateFiles\cortexM7bfsp\ arm_cortexM7bfsp_math 0 1 0 1 0 - .\IntermediateFiles\M7bfsp\ + .\IntermediateFiles\cortexM7bfsp\ 1 0 0 @@ -20119,19 +20119,19 @@ - M7lfdp + cortexM7lfdp 0x3 ARM-GNU ARMCM7_DP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ - IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) 0 $$Device:ARMCM7_DP$Device\ARM\ARMCM7\Include\ARMCM7_DP.h @@ -20158,14 +20158,14 @@ 0 1 - .\IntermediateFiles\M7lfdp\ + .\IntermediateFiles\cortexM7lfdp\ arm_cortexM7lfdp_math 0 1 0 1 0 - .\IntermediateFiles\M7lfdp\ + .\IntermediateFiles\cortexM7lfdp\ 1 0 0 @@ -20242,13 +20242,13 @@ 1 0 0 - 0 + 1 1 4096 1 BIN\UL2CM3.DLL - "" () + @@ -20319,7 +20319,7 @@ 1 0x0 - 0x80000 + 0x40000 0 @@ -20328,13 +20328,13 @@ 0 - 0x0 - 0x0 + 0x20200000 + 0x20000 - 0 - 0x0 - 0x0 + 1 + 0x200000 + 0x200000 @@ -21795,14 +21795,14 @@ - M7bfdp + cortexM7bfdp 0x3 ARM-GNU ARMCM7_DP ARM - ARM.CMSIS.5.0.0-Beta12 + ARM.CMSIS.5.0.0 http://www.keil.com/pack/ IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE @@ -21834,14 +21834,14 @@ 0 1 - .\IntermediateFiles\M7bfdp\ + .\IntermediateFiles\cortexM7bfdp\ arm_cortexM7bfdp_math 0 1 0 1 0 - .\IntermediateFiles\M7bfdp\ + .\IntermediateFiles\cortexM7bfdp\ 1 0 0 @@ -23470,6 +23470,11738 @@ + + ARMv8MBLl + 0x3 + ARM-GNU + + + ARMv8MBL + ARM + ARM.CMSIS.5.0.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMv8MBL$Device\ARM\ARMv8MBL\Include\ARMv8MBL.h + + + + + + + + + + $$Device:ARMv8MBL$Device\ARM\SVD\ARMv8MBL.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\ARMv8MBLl\ + arm_ARMv8MBLl_math + 0 + 1 + 0 + 1 + 0 + .\IntermediateFiles\ARMv8MBLl\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd.exe /C copy "$L\lib@L.a" "..\..\..\Lib\GCC\" + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pV8MBL + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "ARMV8MBL" + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20200000 + 0x20000 + + + 1 + 0x200000 + 0x200000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 5 + 2 + 1 + + -fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.base + ARM_MATH_ARMV8MBL, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE + + ..\..\Include;..\..\..\Core\Include;..\..\..\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + + + + + + -Wl,--gc-sections -march=armv8-m.base + + + + + + + BasicMathFunctions + + + arm_abs_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_abs_f32.c + + + arm_abs_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_abs_q7.c + + + arm_abs_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_abs_q15.c + + + arm_abs_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_abs_q31.c + + + arm_add_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_add_f32.c + + + arm_add_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_add_q7.c + + + arm_add_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_add_q15.c + + + arm_add_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_add_q31.c + + + arm_dot_prod_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_dot_prod_f32.c + + + arm_dot_prod_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_dot_prod_q7.c + + + arm_dot_prod_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_dot_prod_q15.c + + + arm_dot_prod_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_dot_prod_q31.c + + + arm_mult_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_mult_f32.c + + + arm_mult_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_mult_q7.c + + + arm_mult_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_mult_q15.c + + + arm_mult_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_mult_q31.c + + + arm_negate_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_negate_f32.c + + + arm_negate_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_negate_q7.c + + + arm_negate_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_negate_q15.c + + + arm_negate_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_negate_q31.c + + + arm_offset_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_offset_f32.c + + + arm_offset_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_offset_q7.c + + + arm_offset_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_offset_q15.c + + + arm_offset_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_offset_q31.c + + + arm_scale_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_scale_f32.c + + + arm_scale_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_scale_q7.c + + + arm_scale_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_scale_q15.c + + + arm_scale_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_scale_q31.c + + + arm_shift_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_shift_q7.c + + + arm_shift_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_shift_q15.c + + + arm_shift_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_shift_q31.c + + + arm_sub_f32.c + 1 + ..\..\Source\BasicMathFunctions\arm_sub_f32.c + + + arm_sub_q7.c + 1 + ..\..\Source\BasicMathFunctions\arm_sub_q7.c + + + arm_sub_q15.c + 1 + ..\..\Source\BasicMathFunctions\arm_sub_q15.c + + + arm_sub_q31.c + 1 + ..\..\Source\BasicMathFunctions\arm_sub_q31.c + + + + + FastMathFunctions + + + arm_cos_f32.c + 1 + ..\..\Source\FastMathFunctions\arm_cos_f32.c + + + arm_cos_q15.c + 1 + ..\..\Source\FastMathFunctions\arm_cos_q15.c + + + arm_cos_q31.c + 1 + ..\..\Source\FastMathFunctions\arm_cos_q31.c + + + arm_sin_f32.c + 1 + ..\..\Source\FastMathFunctions\arm_sin_f32.c + + + arm_sin_q15.c + 1 + ..\..\Source\FastMathFunctions\arm_sin_q15.c + + + arm_sin_q31.c + 1 + ..\..\Source\FastMathFunctions\arm_sin_q31.c + + + arm_sqrt_q15.c + 1 + ..\..\Source\FastMathFunctions\arm_sqrt_q15.c + + + arm_sqrt_q31.c + 1 + ..\..\Source\FastMathFunctions\arm_sqrt_q31.c + + + + + ComplexMathFunctions + + + arm_cmplx_conj_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_conj_f32.c + + + arm_cmplx_conj_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_conj_q15.c + + + arm_cmplx_conj_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_conj_q31.c + + + arm_cmplx_dot_prod_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_dot_prod_f32.c + + + arm_cmplx_dot_prod_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_dot_prod_q15.c + + + arm_cmplx_dot_prod_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_dot_prod_q31.c + + + arm_cmplx_mag_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_f32.c + + + arm_cmplx_mag_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_q15.c + + + arm_cmplx_mag_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_q31.c + + + arm_cmplx_mag_squared_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_squared_f32.c + + + arm_cmplx_mag_squared_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_squared_q15.c + + + arm_cmplx_mag_squared_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mag_squared_q31.c + + + arm_cmplx_mult_cmplx_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_f32.c + + + arm_cmplx_mult_cmplx_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_q15.c + + + arm_cmplx_mult_cmplx_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_q31.c + + + arm_cmplx_mult_real_f32.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_real_f32.c + + + arm_cmplx_mult_real_q15.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_real_q15.c + + + arm_cmplx_mult_real_q31.c + 1 + ..\..\Source\ComplexMathFunctions\arm_cmplx_mult_real_q31.c + + + + + FilteringFunctions + + + arm_biquad_cascade_df1_32x64_init_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_32x64_init_q31.c + + + arm_biquad_cascade_df1_32x64_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_32x64_q31.c + + + arm_biquad_cascade_df1_f32.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_f32.c + + + arm_biquad_cascade_df1_fast_q15.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_fast_q15.c + + + arm_biquad_cascade_df1_fast_q31.c + 1 + ..\..\Source\FilteringFunctions\arm_biquad_cascade_df1_fast_q31.c + + + arm_biquad_cascade_df1_init_f32.c + 1 + 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arm_cfft_radix2_init_q15.c + 1 + ..\..\Source\TransformFunctions\arm_cfft_radix2_init_q15.c + + + arm_cfft_radix2_init_q31.c + 1 + ..\..\Source\TransformFunctions\arm_cfft_radix2_init_q31.c + + + arm_cfft_radix2_q15.c + 1 + ..\..\Source\TransformFunctions\arm_cfft_radix2_q15.c + + + arm_cfft_radix2_q31.c + 1 + ..\..\Source\TransformFunctions\arm_cfft_radix2_q31.c + + + arm_cfft_f32.c + 1 + ..\..\Source\TransformFunctions\arm_cfft_f32.c + + + arm_cfft_radix8_f32.c + 1 + ..\..\Source\TransformFunctions\arm_cfft_radix8_f32.c + + + arm_bitreversal2.S + 1 + ..\..\Source\TransformFunctions\arm_bitreversal2.S + + + arm_rfft_fast_f32.c + 1 + ..\..\Source\TransformFunctions\arm_rfft_fast_f32.c + + + arm_rfft_fast_init_f32.c + 1 + ..\..\Source\TransformFunctions\arm_rfft_fast_init_f32.c + + + arm_cfft_q31.c + 1 + ..\..\Source\TransformFunctions\arm_cfft_q31.c + + + arm_cfft_q15.c + 1 + ..\..\Source\TransformFunctions\arm_cfft_q15.c + + + + + ControllerFunctions + + + arm_pid_init_f32.c + 1 + ..\..\Source\ControllerFunctions\arm_pid_init_f32.c + + + arm_pid_init_q15.c + 1 + ..\..\Source\ControllerFunctions\arm_pid_init_q15.c + + + arm_pid_init_q31.c + 1 + ..\..\Source\ControllerFunctions\arm_pid_init_q31.c + + + arm_pid_reset_f32.c + 1 + ..\..\Source\ControllerFunctions\arm_pid_reset_f32.c + + + arm_pid_reset_q15.c + 1 + ..\..\Source\ControllerFunctions\arm_pid_reset_q15.c + + + arm_pid_reset_q31.c + 1 + ..\..\Source\ControllerFunctions\arm_pid_reset_q31.c + + + arm_sin_cos_f32.c + 1 + ..\..\Source\ControllerFunctions\arm_sin_cos_f32.c + + + arm_sin_cos_q31.c + 1 + ..\..\Source\ControllerFunctions\arm_sin_cos_q31.c + + + + + StatisticsFunctions + + + arm_max_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_max_f32.c + + + arm_max_q7.c + 1 + ..\..\Source\StatisticsFunctions\arm_max_q7.c + + + arm_max_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_max_q15.c + + + arm_max_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_max_q31.c + + + arm_mean_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_mean_f32.c + + + arm_mean_q7.c + 1 + ..\..\Source\StatisticsFunctions\arm_mean_q7.c + + + arm_mean_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_mean_q15.c + + + arm_mean_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_mean_q31.c + + + arm_min_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_min_f32.c + + + arm_min_q7.c + 1 + ..\..\Source\StatisticsFunctions\arm_min_q7.c + + + arm_min_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_min_q15.c + + + arm_min_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_min_q31.c + + + arm_power_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_power_f32.c + + + arm_power_q7.c + 1 + ..\..\Source\StatisticsFunctions\arm_power_q7.c + + + arm_power_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_power_q15.c + + + arm_power_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_power_q31.c + + + arm_rms_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_rms_f32.c + + + arm_rms_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_rms_q15.c + + + arm_rms_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_rms_q31.c + + + arm_std_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_std_f32.c + + + arm_std_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_std_q15.c + + + arm_std_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_std_q31.c + + + arm_var_f32.c + 1 + ..\..\Source\StatisticsFunctions\arm_var_f32.c + + + arm_var_q15.c + 1 + ..\..\Source\StatisticsFunctions\arm_var_q15.c + + + arm_var_q31.c + 1 + ..\..\Source\StatisticsFunctions\arm_var_q31.c + + + + + SupportFunctions + + + arm_copy_f32.c + 1 + ..\..\Source\SupportFunctions\arm_copy_f32.c + + + arm_copy_q7.c + 1 + ..\..\Source\SupportFunctions\arm_copy_q7.c + + + arm_copy_q15.c + 1 + ..\..\Source\SupportFunctions\arm_copy_q15.c + + + arm_copy_q31.c + 1 + ..\..\Source\SupportFunctions\arm_copy_q31.c + + + arm_fill_f32.c + 1 + ..\..\Source\SupportFunctions\arm_fill_f32.c + + + arm_fill_q7.c + 1 + ..\..\Source\SupportFunctions\arm_fill_q7.c + + + arm_fill_q15.c + 1 + ..\..\Source\SupportFunctions\arm_fill_q15.c + + + arm_fill_q31.c + 1 + ..\..\Source\SupportFunctions\arm_fill_q31.c + + + arm_float_to_q7.c + 1 + ..\..\Source\SupportFunctions\arm_float_to_q7.c + + + arm_float_to_q15.c + 1 + ..\..\Source\SupportFunctions\arm_float_to_q15.c + + + arm_float_to_q31.c + 1 + ..\..\Source\SupportFunctions\arm_float_to_q31.c + + + arm_q7_to_float.c + 1 + ..\..\Source\SupportFunctions\arm_q7_to_float.c + + + arm_q7_to_q15.c + 1 + ..\..\Source\SupportFunctions\arm_q7_to_q15.c + + + arm_q7_to_q31.c + 1 + ..\..\Source\SupportFunctions\arm_q7_to_q31.c + + + arm_q15_to_float.c + 1 + ..\..\Source\SupportFunctions\arm_q15_to_float.c + + + arm_q15_to_q7.c + 1 + ..\..\Source\SupportFunctions\arm_q15_to_q7.c + + + arm_q15_to_q31.c + 1 + ..\..\Source\SupportFunctions\arm_q15_to_q31.c + + + arm_q31_to_float.c + 1 + ..\..\Source\SupportFunctions\arm_q31_to_float.c + + + arm_q31_to_q7.c + 1 + ..\..\Source\SupportFunctions\arm_q31_to_q7.c + + + arm_q31_to_q15.c + 1 + ..\..\Source\SupportFunctions\arm_q31_to_q15.c + + + + + CommonTables + + + arm_common_tables.c + 1 + ..\..\Source\CommonTables\arm_common_tables.c + + + arm_const_structs.c + 1 + ..\..\Source\CommonTables\arm_const_structs.c + + + + + diff --git a/Projects/GCC/arm_cortexM_math_Build.bat b/Projects/GCC/arm_cortexM_math_Build.bat index e5653f17..8cc8a294 100644 --- a/Projects/GCC/arm_cortexM_math_Build.bat +++ b/Projects/GCC/arm_cortexM_math_Build.bat @@ -6,33 +6,69 @@ echo. echo Building DSP Libraries GCC echo. echo Building DSP Library for Cortex-M0 Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M0l" -o "DspLib_M0l_build.log" -echo Building DSP Library for Cortex-M0 Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M0b" -o "DspLib_M0b_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM0l" -o "DspLib_cortexM0l_build.log" + echo Building DSP Library for Cortex-M3 Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M3l" -o "DspLib_M3l_build.log" -echo Building DSP Library for Cortex-M3 Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M3b" -o "DspLib_M3b_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM3l" -o "DspLib_cortexM3l_build.log" + echo Building DSP Library for Cortex-M4 Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M4l" -o "DspLib_M4l_build.log" -echo Building DSP Library for Cortex-M4 Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M4b" -o "DspLib_M4b_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM4l" -o "DspLib_cortexM4l_build.log" + echo Building DSP Library for Cortex-M4 with FPU Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M4lf" -o "DspLib_M4lf_build.log" -echo Building DSP Library for Cortex-M4 with FPU Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M4bf" -o "DspLib_M4bf_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM4lf" -o "DspLib_cortexM4lf_build.log" + echo Building DSP Library for Cortex-M7 Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7l" -o "DspLib_M7l_build.log" -echo Building DSP Library for Cortex-M7 Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7b" -o "DspLib_M7b_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7l" -o "DspLib_cortexM7l_build.log" + echo Building DSP Library for Cortex-M7 with single precision FPU Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7lfsp" -o "DspLib_M7lfsp_build.log" -echo Building DSP Library for Cortex-M7 with single precision FPU Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7bfsp" -o "DspLib_M7bfsp_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7lfsp" -o "DspLib_cortexM7lfsp_build.log" + echo Building DSP Library for Cortex-M7 with double precision FPU Little Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7lfdp" -o "DspLib_M7lfdp_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7lfdp" -o "DspLib_cortexM7lfdp_build.log" + +echo Building DSP Library for ARMv8-M Baseline Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MBLl" -o "DspLib_ARMv8MBLl_build.log" + +echo Building DSP Library for ARMv8-M Mainline Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLl" -o "DspLib_ARMv8MMLl_build.log" + +echo Building DSP Library for ARMv8-M Mainline with single precision FPU Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLlfsp" -o "DspLib_ARMv8MMLlfsp_build.log" + +echo Building DSP Library for ARMv8-M Mainline with double precision FPU Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLlfdp" -o "DspLib_ARMv8MMLlfdp_build.log" + +echo Building DSP Library for ARMv8-M Mainline with DSP Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLld" -o "DspLib_ARMv8MMLld_build.log" + +echo Building DSP Library for ARMv8-M Mainline with DSP, single precision FPU Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLldfsp" -o "DspLib_ARMv8MMLldfsp_build.log" + +echo Building DSP Library for ARMv8-M Mainline with DSP, double precision FPU Little Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "ARMv8MMLldfdp" -o "DspLib_ARMv8MMLldfdp_build.log" + +REM big endian libraries + +echo Building DSP Library for Cortex-M0 Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM0b" -o "DspLib_cortexM0b_build.log" + +echo Building DSP Library for Cortex-M3 Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM3b" -o "DspLib_cortexM3b_build.log" + +echo Building DSP Library for Cortex-M4 Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM4b" -o "DspLib_cortexM4b_build.log" + +echo Building DSP Library for Cortex-M4 with FPU Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM4bf" -o "DspLib_cortexM4bf_build.log" + +echo Building DSP Library for Cortex-M7 Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7b" -o "DspLib_cortexM7b_build.log" + +echo Building DSP Library for Cortex-M7 with single precision FPU Big Endian +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7bfsp" -o "DspLib_cortexM7bfsp_build.log" + echo Building DSP Library for Cortex-M7 with double precision FPU Big Endian -%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "M7bfdp" -o "DspLib_M7bfdp_build.log" +%UVEXE% -rb -j0 arm_cortexM_math.uvprojx -t "cortexM7bfdp" -o "DspLib_cortexM7bfdp_build.log" echo. ECHO Deleting intermediate files diff --git a/Source/TransformFunctions/arm_bitreversal2.S b/Source/TransformFunctions/arm_bitreversal2.S index a8c5e9a2..b9691387 100644 --- a/Source/TransformFunctions/arm_bitreversal2.S +++ b/Source/TransformFunctions/arm_bitreversal2.S @@ -1,8 +1,8 @@ ;/* ---------------------------------------------------------------------- ;* Copyright (C) 2010-2015 ARM Limited. All rights reserved. ;* -;* $Date: 21. December 2015 -;* $Revision: V.1.4.5 a +;* $Date: 02. November 2015 +;* $Revision: V.1.4.5 b ;* ;* Project: CMSIS DSP Library ;* Title: arm_bitreversal2.S @@ -99,7 +99,7 @@ .type arm_bitreversal_32, %function #endif -#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS) +#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS) || defined(ARM_MATH_ARMV8MBL) arm_bitreversal_32 PROC ADDS r3,r1,#1