diff --git a/Platforms/IPSS/ARMCR5/Include/ARMCR5.h b/Platforms/IPSS/ARMCR5/Include/ARMCR5.h new file mode 100755 index 00000000..43cb407f --- /dev/null +++ b/Platforms/IPSS/ARMCR5/Include/ARMCR5.h @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file ARMCM7.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCM7 Device (configured for CM7 without FPU) + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCR8_H +#define ARMCR8_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ------------------- Processor Interrupt Numbers ------------------------------ */ + Interrupt0_IRQn = 0, + Interrupt1_IRQn = 1, + Interrupt2_IRQn = 2, + Interrupt3_IRQn = 3, + Interrupt4_IRQn = 4, + Interrupt5_IRQn = 5, + Interrupt6_IRQn = 6, + Interrupt7_IRQn = 7, + Interrupt8_IRQn = 8, + Interrupt9_IRQn = 9 + /* Interrupts 10 .. 224 are left out */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CR8_REV 0x0000U /* Core revision r0p0 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* no FPU present */ +#define __FPU_DP 1U /* unused */ +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U +#define __DTCM_PRESENT 1U + +#include "core_cr5.h" /* Processor and core peripherals */ +#include "system_ARMCR5.h" /* System Header */ + + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCR5/Include/system_ARMCR5.h b/Platforms/IPSS/ARMCR5/Include/system_ARMCR5.h new file mode 100755 index 00000000..ec831e09 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/Include/system_ARMCR5.h @@ -0,0 +1,55 @@ +/**************************************************************************//** + * @file system_ARMCM7.h + * @brief CMSIS Device System Header File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_ARMCM7_H +#define SYSTEM_ARMCM7_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCR5/LinkScripts/AC6/lnk.sct b/Platforms/IPSS/ARMCR5/LinkScripts/AC6/lnk.sct new file mode 100755 index 00000000..24f886eb --- /dev/null +++ b/Platforms/IPSS/ARMCR5/LinkScripts/AC6/lnk.sct @@ -0,0 +1,35 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +#include "mem_ARMCR5.h" + +LOAD_REGION 0x0 +{ + CODE +0 0x80000 + { + *.o (VECTORS, +First) + * (InRoot$$$Sections) + * (+RO-CODE) + } + + DATA 0x20000000 NOCOMPRESS 0x60000 + { + * (+RO-DATA) + * (+RW,+ZI) + } + + ARM_LIB_STACKHEAP 0x20062000 ALIGN 64 EMPTY 0x000052000 + {} + + +} + + + + + + diff --git a/Platforms/IPSS/ARMCR5/LinkScripts/AC6/mem_ARMCR5.h b/Platforms/IPSS/ARMCR5/LinkScripts/AC6/mem_ARMCR5.h new file mode 100755 index 00000000..026224c0 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/LinkScripts/AC6/mem_ARMCR5.h @@ -0,0 +1,38 @@ +/**************************************************************************//** + * @file mem_ARMCM7.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCR5_H +#define __MEM_ARMCR5_H + + + +#define STACK_SIZE 0x00003000 +#define HEAP_SIZE 0x00100000 + + + +#endif /* __MEM_ARMCR8_H */ diff --git a/Platforms/IPSS/ARMCR5/LinkScripts/GCC/lnk.ld b/Platforms/IPSS/ARMCR5/LinkScripts/GCC/lnk.ld new file mode 100755 index 00000000..6592a441 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/LinkScripts/GCC/lnk.ld @@ -0,0 +1,239 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + * @version V2.0.0 + * @date 21. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mem_ARMCM7.h" + +__STACK_SIZE = 0x2000; +__HEAP_SIZE = 0x50000; + +MEMORY +{ + ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 512K + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + DTCM2 (xrw) : ORIGIN = 0x20020000, LENGTH = 384K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > ITCM + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ITCM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ITCM + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) +*/ + __copy_table_end__ = .; + } > ITCM + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) +*/ + __zero_table_end__ = .; + } > DTCM + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + + .data : + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > ITCM AT > DTCM + + __etext = ADDR(.data); + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > DTCM2 + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > DTCM2 + + .stack (ORIGIN(DTCM2) + LENGTH(DTCM2) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM2 + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds DTCM2 limit */ + ASSERT(__StackLimit >= __HeapLimit, "region DTCM2 overflowed with stack") +} + + + diff --git a/Platforms/IPSS/ARMCR5/LinkScripts/GCC/mem_ARMCR8.h b/Platforms/IPSS/ARMCR5/LinkScripts/GCC/mem_ARMCR8.h new file mode 100755 index 00000000..84a1ff1d --- /dev/null +++ b/Platforms/IPSS/ARMCR5/LinkScripts/GCC/mem_ARMCR8.h @@ -0,0 +1,38 @@ +/**************************************************************************//** + * @file mem_ARMCM7.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCM7_H +#define __MEM_ARMCM7_H + + + +#define STACK_SIZE 0x00003000 +#define HEAP_SIZE 0x00100000 + + + +#endif /* __MEM_ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCR5/Startup/AC5/startup_ARMCR8.s b/Platforms/IPSS/ARMCR5/Startup/AC5/startup_ARMCR8.s new file mode 100755 index 00000000..333d3581 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/Startup/AC5/startup_ARMCR8.s @@ -0,0 +1,168 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.4.0 +; * @date 12. December 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +#include "mem_ARMCM7.h" + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU STACK_SIZE + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU HEAP_SIZE + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + IF :LNOT::DEF:__MICROLIB + IMPORT __use_two_region_memory + ENDIF + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Platforms/IPSS/ARMCR5/Startup/AC6/old_startup.s b/Platforms/IPSS/ARMCR5/Startup/AC6/old_startup.s new file mode 100755 index 00000000..33cb9ee7 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/Startup/AC6/old_startup.s @@ -0,0 +1,369 @@ +/****************************************************************************** + * @file startup_ARMCR5.c + * @brief Unvalidated Startup File for a Cortex-R5 Device + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Region size <256 bytes is unpredictable + +#define Region_256B 0b00111 +#define Region_512B 0b01000 +#define Region_1K 0b01001 +#define Region_2K 0b01010 +#define Region_4K 0b01011 +#define Region_8K 0b01100 +#define Region_16K 0b01101 +#define Region_32K 0b01110 +#define Region_64K 0b01111 +#define Region_128K 0b10000 +#define Region_256K 0b10001 +#define Region_512K 0b10010 +#define Region_1M 0b10011 +#define Region_2M 0b10100 +#define Region_4M 0b10101 +#define Region_8M 0b10110 +#define Region_16M 0b10111 +#define Region_32M 0b11000 +#define Region_64M 0b11001 +#define Region_128M 0b11010 +#define Region_256M 0b11011 +#define Region_512M 0b11100 +#define Region_1G 0b11101 +#define Region_2G 0b11110 +#define Region_4G 0b11111 + +#define Region_Enable 0b1 + +#define Execute_Never 0x1000 // Bit 12 + +#define Normal_nShared 0x03 // Outer and Inner write-back, no write-allocate +#define Device_nShared 0x10 + +#define Full_Access 0b011 +#define Read_Only 0b110 + +//---------------------------------------------------------------- + + .eabi_attribute Tag_ABI_align8_preserved,1 + + .section VECTORS,"ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Start + +Start: + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + B . // Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + + .balign 4 +Reset_Addr: .word Reset_Handler +Undefined_Addr: .word Undefined_Handler +SVC_Addr: .word SVC_Handler +Prefetch_Addr: .word Prefetch_Handler +Abort_Addr: .word Abort_Handler +IRQ_Addr: .word IRQ_Handler +FIQ_Addr: .word FIQ_Handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- + + .global Reset_Handler + .type Reset_Handler, "function" +Reset_Handler: + +//---------------------------------------------------------------- +// Disable MPU and caches +//---------------------------------------------------------------- + +// Disable MPU and cache in case it was left enabled from an earlier run +// This does not need to be done from a cold reset + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #0x05 // Disable MPU (M bit) and data cache (C bit) + BIC r0, r0, #0x800 // Disable branch prediction (Z bit) + BIC r0, r0, #0x1000 // Disable instruction cache (I bit) + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings + + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack using Linker symbol from scatter file. +// Stacks must be 8 byte aligned. +//---------------------------------------------------------------- + + .global Image$$ARM_LIB_STACKHEAP$$ZI$$Limit + LDR SP, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit + + +//---------------------------------------------------------------- +// Cache invalidation +//---------------------------------------------------------------- + + DSB + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 0 // invalidate I cache + MCR p15, 0, r0, c15, c5, 0 // invalidate D cache + +//---------------------------------------------------------------- +// TCM Configuration +//---------------------------------------------------------------- + +// Cortex-R8 optionally provides two Tightly-Coupled Memory (TCM) blocks (ITCM and DTCM) +// for fast access to code or data. +// ITCM typically holds interrupt or exception code that must be accessed at high speed, +// without any potential delay resulting from a cache miss. +// DTCM typically holds a block of data for intensive processing, such as audio or video data. + +// The following illustrates basic TCM configuration, as the basis for exploration by the user + +#if TCM + .global Image$$CODE$$Base + .global Image$$DATA$$Base + + MRC p15, 0, r0, c0, c0, 2 // Read TCM Type Register + // r0 now contains ITCM & DTCM availability + + MRC p15, 0, r0, c9, c1, 1 // Read ITCM Region Register + // r0 now contains ITCM size in bits [5:2] + + LDR r0, =Image$$CODE$$Base // Set ITCM base address + ORR r0, r0, #1 // Enable it + MCR p15, 0, r0, c9, c1, 1 // Write ITCM Region Register + + MRC p15, 0, r0, c9, c1, 0 // Read DTCM Region Register + // r0 now contains DTCM size in bits [5:2] + + LDR r0, =Image$$DATA$$Base // Set DTCM base address + ORR r0, r0, #1 // Enable it + MCR p15, 0, r0, c9, c1, 0 // Write DTCM Region Register + +#endif + + MRC p15, 0, r0, c1, c0, 1 + TST r0, #(1 << 6) // SMP bit + ORREQ r0, r0, #(1 << 6) // Set SMP bit in aux control register + MCREQ p15, 0, r0, c1, c0, 1 // write Aux Control Register (ACTLR) + +//---------------------------------------------------------------- +// MPU Configuration +//---------------------------------------------------------------- + +// Notes: +// * Regions apply to both instruction and data accesses. +// * Each region base address must be a multiple of its size +// * Any address range not covered by an enabled region will abort +// * The region at 0x0 over the Vector table is needed to support semihosting + +// Region 0: Code Base = 0x0000 Size = 32KB Normal Non-shared Read-only Executable +// Region 1: Data Base = 0x40000 Size = 128KB Normal Non-shared Full access Not Executable +// Region 2: Stack/Heap Base = 0x100000 Size = 64KB Normal Non-shared Full access Not Executable +// Region 3: Vectors Base = 0x0000 Size = 1KB Normal Non-shared Full access Executable +// Region 4: Peripherals Base = 0xB0000000 Limit = 0xBFFFFFC0 Device Full access Not Executable + + // Import linker symbols to get region base addresses + .global Image$$CODE$$Base + .global Image$$DATA$$Base + .global Image$$ARM_LIB_STACKHEAP$$Base + + // Region 0 - Code + MOV r1, #0 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$CODE$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_32K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 1 - Data + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$DATA$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_128K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 2 - Stack/Heap + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$ARM_LIB_STACKHEAP$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_64K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 3 - Vectors + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =0 + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_1K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 4 - Peripherals + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =0xB0000000 + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_1K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Device_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Disable all higher priority regions (assumes unified regions, which is always true for Cortex-R8) + MRC p15, 0, r0, c0, c0, 4 // Read MPU Type register (MPUIR) + LSR r0, r0, #8 + AND r0, r0, #0xff // r0 = Number of MPU regions (12, 16, 20, or 24 for Cortex-R8) + MOV r2, #0 // Value to write to disable region +region_loop: + ADD r1, r1, #1 + CMP r0, r1 + BLS regions_done + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register (RGNR) + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register (DRSR) + B region_loop +regions_done: + + +#ifdef __ARM_FP +//---------------------------------------------------------------- +// Enable access to VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + + // + // SMP initialization + // ------------------- + MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register + ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field + BNE secondaryCPUsInit + +//---------------------------------------------------------------- +// Enable MPU and branch to C library init +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #0x01 // Set M bit to enable MPU + ORR r0, r0, #0x800 // Set Z bit to enable branch prediction + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings + + .global __main + B __main + + .size Reset_Handler, . - Reset_Handler + + + +// ------------------------------------------------------------ +// Initialization for SECONDARY CPUs +// ------------------------------------------------------------ + + .global secondaryCPUsInit + .type secondaryCPUsInit, "function" +secondaryCPUsInit: + wfi + + +//---------------------------------------------------------------- +// Global Enable for Instruction and Data Caching +//---------------------------------------------------------------- + + .global enable_caches + .type enable_caches, "function" + .cfi_startproc +enable_caches: + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // enable I Cache + ORR r0, r0, #(0x1 << 2) // enable D Cache + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + .cfi_endproc + + .size enable_caches, . - enable_caches diff --git a/Platforms/IPSS/ARMCR5/Startup/AC6/startup.s b/Platforms/IPSS/ARMCR5/Startup/AC6/startup.s new file mode 100755 index 00000000..0278e7e3 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/Startup/AC6/startup.s @@ -0,0 +1,398 @@ +/****************************************************************************** + * @file startup_ARMCR5.c + * @brief Unvalidated Startup File for a Cortex-R5 Device + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Region size <256 bytes is unpredictable + +#define Region_256B 0b00111 +#define Region_512B 0b01000 +#define Region_1K 0b01001 +#define Region_2K 0b01010 +#define Region_4K 0b01011 +#define Region_8K 0b01100 +#define Region_16K 0b01101 +#define Region_32K 0b01110 +#define Region_64K 0b01111 +#define Region_128K 0b10000 +#define Region_256K 0b10001 +#define Region_512K 0b10010 +#define Region_1M 0b10011 +#define Region_2M 0b10100 +#define Region_4M 0b10101 +#define Region_8M 0b10110 +#define Region_16M 0b10111 +#define Region_32M 0b11000 +#define Region_64M 0b11001 +#define Region_128M 0b11010 +#define Region_256M 0b11011 +#define Region_512M 0b11100 +#define Region_1G 0b11101 +#define Region_2G 0b11110 +#define Region_4G 0b11111 + +#define Region_Enable 0b1 + +#define Execute_Never 0x1000 // Bit 12 + +#define Normal_nShared 0x03 // Outer and Inner write-back, no write-allocate +#define Device_nShared 0x10 + +#define Full_Access 0b011 +#define Read_Only 0b110 + + +//---------------------------------------------------------------- + + .eabi_attribute Tag_ABI_align8_preserved,1 + + .section VECTORS,"ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Start + +Start: + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + B . // Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + + .balign 4 +Reset_Addr: .word Reset_Handler +Undefined_Addr: .word Undefined_Handler +SVC_Addr: .word SVC_Handler +Prefetch_Addr: .word Prefetch_Handler +Abort_Addr: .word Abort_Handler +IRQ_Addr: .word IRQ_Handler +FIQ_Addr: .word FIQ_Handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- + + .global Reset_Handler + .type Reset_Handler, "function" +Reset_Handler: + mrc p15, 0, r0, c1, c0, 0 // read CP15 register 1 into r0 (SCTLR) + orr r0, r0, #(0x1 <<12) // enable I Cache + orr r0, r0, #(0x1 <<2) // enable D Cache + + mcr p15, 0, r0, c1, c0, 0 // write CP15 register 1 + + mrc p15, 0, r0, c1, c0, 0 // read CP15 register 1 into r0 (SCTLR) + orr r0, r0, #(0x1 <<11) // Enable all forms of branch prediction + mcr p15, 0, r0, c1, c0, 0 // write CP15 register 1 + +//---------------------------------------------------------------- +// Disable MPU and caches +//---------------------------------------------------------------- + +// Disable MPU and cache in case it was left enabled from an earlier run +// This does not need to be done from a cold reset + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #0x01 // Disable MPU (M bit) and data cache (C bit) + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings + + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack using Linker symbol from scatter file. +// Stacks must be 8 byte aligned. +//---------------------------------------------------------------- + + .global Image$$ARM_LIB_STACKHEAP$$ZI$$Limit + LDR SP, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit + + +//---------------------------------------------------------------- +// Cache invalidation +//---------------------------------------------------------------- + + //DSB + //MOV r0, #0 + //MCR p15, 0, r0, c7, c5, 0 // invalidate I cache + //MCR p15, 0, r0, c15, c5, 0 // invalidate D cache + +//---------------------------------------------------------------- +// TCM Configuration +//---------------------------------------------------------------- + +// Cortex-R8 optionally provides two Tightly-Coupled Memory (TCM) blocks (ITCM and DTCM) +// for fast access to code or data. +// ITCM typically holds interrupt or exception code that must be accessed at high speed, +// without any potential delay resulting from a cache miss. +// DTCM typically holds a block of data for intensive processing, such as audio or video data. + +// The following illustrates basic TCM configuration, as the basis for exploration by the user + + + +// .global Image$$CODE$$Base +// .global Image$$DATA$$Base +// +// MRC p15, 0, r0, c0, c0, 2 // Read TCM Type Register +// // r0 now contains ITCM & DTCM availability +// +// MRC p15, 0, r0, c9, c1, 1 // Read ITCM Region Register +// // r0 now contains ITCM size in bits [5:2] +// +// LDR r0, =Image$$CODE$$Base // Set ITCM base address +// ORR r0, r0, #1 // Enable it +// MCR p15, 0, r0, c9, c1, 1 // Write ITCM Region Register +// +// MRC p15, 0, r0, c9, c1, 0 // Read DTCM Region Register +// // r0 now contains DTCM size in bits [5:2] +// +// LDR r0, =Image$$DATA$$Base // Set DTCM base address +// ORR r0, r0, #1 // Enable it +// MCR p15, 0, r0, c9, c1, 0 // Write DTCM Region Register + + +//---------------------------------------------------------------- +// MPU Configuration +//---------------------------------------------------------------- + +// Notes: +// * Regions apply to both instruction and data accesses. +// * Each region base address must be a multiple of its size +// * Any address range not covered by an enabled region will abort +// * The region at 0x0 over the Vector table is needed to support semihosting + +// Region 0: Code Base = 0x0000 Size = 32KB Normal Non-shared Read-only Executable +// Region 1: Data Base = 0x40000 Size = 128KB Normal Non-shared Full access Not Executable +// Region 2: Stack/Heap Base = 0x100000 Size = 64KB Normal Non-shared Full access Not Executable +// Region 3: Vectors Base = 0x0000 Size = 1KB Normal Non-shared Full access Executable +// Region 4: Peripherals Base = 0xB0000000 Limit = 0xBFFFFFC0 Device Full access Not Executable + + // Import linker symbols to get region base addresses + .global Image$$CODE$$Base + .global Image$$DATA$$Base + .global Image$$ARM_LIB_STACKHEAP$$Base + + // Region 0 - Code + MOV r1, #0 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$CODE$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x1 | (Region_1M << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared + BIC r2, r2, #Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 1 - Data + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$DATA$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x1 | (Region_1M << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 2 - Stack/Heap + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$ARM_LIB_STACKHEAP$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x1 | (Region_1M << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 3 - Vectors + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =0 + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x1 | (Region_1K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 4 - Peripherals + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =0xB0000000 + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x1 | (Region_1K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Device_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Disable all higher priority regions (assumes unified regions, which is always true for Cortex-R8) + MRC p15, 0, r0, c0, c0, 4 // Read MPU Type register (MPUIR) + LSR r0, r0, #8 + AND r0, r0, #0xff // r0 = Number of MPU regions (12, 16, 20, or 24 for Cortex-R8) + MOV r2, #0 // Value to write to disable region +region_loop: + ADD r1, r1, #1 + CMP r0, r1 + BLS regions_done + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register (RGNR) + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register (DRSR) + B region_loop +regions_done: + + +#ifdef __ARM_FP +//---------------------------------------------------------------- +// Enable access to VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + + + + // + // SMP initialization + // ------------------- + MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register + ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field + BNE secondaryCPUsInit + + +//---------------------------------------------------------------- +// Enable MPU and branch to C library init +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #0x01 // Set M bit to enable MPU + //ORR r0, r0, #(0x1 <<11) // Set Z bit to enable branch prediction + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings + + //MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + //ORR r0, r0, #(0x1 << 12) // enable I Cache + //ORR r0, r0, #(0x1 << 2) // enable D Cache + //MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + //ISB + + ldr r0, =0xB0000000 + ldr r1, =49 + strb r1, [r0] + ldr r1, =10 + strb r1, [r0] + + ldr r0, =0xB0000000 + ldr r1, =50 + strb r1, [r0] + ldr r1, =10 + strb r1, [r0] + + + .global __main + B __main + + .size Reset_Handler, . - Reset_Handler + + +// ------------------------------------------------------------ +// Initialization for SECONDARY CPUs +// ------------------------------------------------------------ + + .global secondaryCPUsInit + .type secondaryCPUsInit, "function" +secondaryCPUsInit: cpsie a + wfi + + +//---------------------------------------------------------------- +// Global Enable for Instruction and Data Caching +//---------------------------------------------------------------- + + .global enable_caches + .type enable_caches, "function" + .cfi_startproc +enable_caches: + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // enable I Cache + ORR r0, r0, #(0x1 << 2) // enable D Cache + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + .cfi_endproc + + .size enable_caches, . - enable_caches + +message1: .asciz "Test1\n" +message2: .asciz "Test2\n" + diff --git a/Platforms/IPSS/ARMCR5/Startup/AC6/startup_ARMCR5.c b/Platforms/IPSS/ARMCR5/Startup/AC6/startup_ARMCR5.c new file mode 100755 index 00000000..2053cbd1 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/Startup/AC6/startup_ARMCR5.c @@ -0,0 +1,156 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCR5) + #include "ARMCR5.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[240]; + const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Platforms/IPSS/ARMCR5/Startup/GCC/startup_ARMCR8.c b/Platforms/IPSS/ARMCR5/Startup/GCC/startup_ARMCR8.c new file mode 100755 index 00000000..8b99812c --- /dev/null +++ b/Platforms/IPSS/ARMCR5/Startup/GCC/startup_ARMCR8.c @@ -0,0 +1,165 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[240]; + const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#define SERIAL_BASE_ADDRESS (0xA8000000ul) + +#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS) + + + + + + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + + + __PROGRAM_START(); +} + + + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + + diff --git a/Platforms/IPSS/ARMCR5/Startup/GCC/support.c b/Platforms/IPSS/ARMCR5/Startup/GCC/support.c new file mode 100755 index 00000000..6a6d4f44 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/Startup/GCC/support.c @@ -0,0 +1,36 @@ + +#ifdef __cplusplus +extern "C" +{ +#endif + +char * _sbrk(int incr); + +void __malloc_lock() ; +void __malloc_unlock(); + +char __end__, __HeapLimit; // make sure to define these symbols in linker command file +#ifdef __cplusplus +} +#endif + +static int totalBytesProvidedBySBRK = 0; + +//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file). +char * sbrk(int incr) { + static char *currentHeapEnd = &__end__; + char *previousHeapEnd = currentHeapEnd; + if (currentHeapEnd + incr > &__HeapLimit) { + return (char *)-1; // the malloc-family routine that called sbrk will return 0 + } + currentHeapEnd += incr; + + totalBytesProvidedBySBRK += incr; + + return (char *) previousHeapEnd; +} +//! Synonym for sbrk. +char * _sbrk(int incr) { return sbrk(incr); }; + +void __malloc_lock() { }; +void __malloc_unlock() { }; \ No newline at end of file diff --git a/Platforms/IPSS/ARMCR5/mmu_ARMCR5.c b/Platforms/IPSS/ARMCR5/mmu_ARMCR5.c new file mode 100755 index 00000000..fa4a6252 --- /dev/null +++ b/Platforms/IPSS/ARMCR5/mmu_ARMCR5.c @@ -0,0 +1,198 @@ +/**************************************************************************//** + * @file mmu_ARMCA32.c + * @brief MMU Configuration for Arm Cortex-A32 Device Series + * @version V1.2.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map + + Memory Type +0xffffffff |--------------------------| ------------ + | FLAG SYNC | Device Memory +0xfffff000 |--------------------------| ------------ + | Fault | Fault +0xfff00000 |--------------------------| ------------ + | | Normal + | | + | Daughterboard | + | memory | + | | +0x80505000 |--------------------------| ------------ + |TTB (L2 Sync Flags ) 4k | Normal +0x80504C00 |--------------------------| ------------ + |TTB (L2 Peripherals-B) 16k| Normal +0x80504800 |--------------------------| ------------ + |TTB (L2 Peripherals-A) 16k| Normal +0x80504400 |--------------------------| ------------ + |TTB (L2 Priv Periphs) 4k | Normal +0x80504000 |--------------------------| ------------ + | TTB (L1 Descriptors) | Normal +0x80500000 |--------------------------| ------------ + | Stack | Normal + |--------------------------| ------------ + | Heap | Normal +0x80400000 |--------------------------| ------------ + | ZI Data | Normal +0x80300000 |--------------------------| ------------ + | RW Data | Normal +0x80200000 |--------------------------| ------------ + | RO Data | Normal + |--------------------------| ------------ + | RO Code | USH Normal +0x80000000 |--------------------------| ------------ + | Daughterboard | Fault + | HSB AXI buses | +0x40000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x2c002000 |--------------------------| ------------ + | Private Address | Device Memory +0x2c000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x20000000 |--------------------------| ------------ + | Peripherals | Device Memory RW/RO + | | & Fault +0x00000000 |--------------------------| +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 + +#include "ARMCR5.h" +#include "mem_ARMCR5.h" + +#if 0 + +// TTB base address +#define TTB_BASE ((uint32_t*)__TTB_BASE) + +// L2 table pointers +//---------------------------------------- +#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core + // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. + // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. + +#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space +#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF +#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF +#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization + +//--------------------- PERIPHERALS ------------------- +#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) +#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) + +//--------------------- SYNC FLAGS -------------------- +#define FLAG_SYNC 0xFFFFF000 +#define F_SYNC_BASE 0xFFF00000 //1M aligned + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; + + //Create 4GB of faulting entries + MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); + + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Define Image + MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections + MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections + + //--------------------- PERIPHERALS ------------------- + MMU_TTSection (TTB_BASE, VE_A32_PERIPH , 64, Sect_Device_RW); // 64MB NOR + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x1 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x01 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x0 (Inner WB WA) */ + __set_TTBR0(__TTB_BASE | 0x48); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} + +#endif \ No newline at end of file diff --git a/Platforms/IPSS/ARMCR5/system_ARMCR5.c b/Platforms/IPSS/ARMCR5/system_ARMCR5.c new file mode 100755 index 00000000..afcb0afb --- /dev/null +++ b/Platforms/IPSS/ARMCR5/system_ARMCR5.c @@ -0,0 +1,573 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) +#include +#else +#define GCCCOMPILER +struct __FILE {int handle;}; +FILE __stdout; +FILE __stdin; +FILE __stderr; +#endif + + +#if defined (ARMCR5) + #include "ARMCR5.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +//#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +// extern uint32_t __VECTOR_TABLE; +//#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define SERIAL_BASE_ADDRESS (0xb0000000ul) + +#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS) + +#define SOFTWARE_MARK *((volatile unsigned *) (SERIAL_BASE_ADDRESS+4)) + +void start_ipss_measurement() +{ + SOFTWARE_MARK = 1; +} + +void stop_ipss_measurement() +{ + SOFTWARE_MARK = 0; +} + + + +int stdout_putchar(char txchar) +{ + SERIAL_DATA = txchar; + return(txchar); +} + +int stderr_putchar(char txchar) +{ + return stdout_putchar(txchar); +} + +void ttywrch (int ch) +{ + stdout_putchar(ch); +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if 0 +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; + #endif +} + +#if __IS_COMPILER_ARM_COMPILER_6__ +__asm(".global __use_no_semihosting\n\t"); +# ifndef __MICROLIB +__asm(".global __ARM_use_no_argv\n\t"); +# endif +#endif + +/** + Writes the character specified by c (converted to an unsigned char) to + the output stream pointed to by stream, at the position indicated by the + associated file position indicator (if defined), and advances the + indicator appropriately. If the file position indicator is not defined, + the character is appended to the output stream. + + \param[in] c Character + \param[in] stream Stream handle + + \return The character written. If a write error occurs, the error + indicator is set and fputc returns EOF. +*/ +__attribute__((weak)) +int fputc (int c, FILE * stream) +{ + if (stream == &__stdout) { + return (stdout_putchar(c)); + } + + if (stream == &__stderr) { + return (stderr_putchar(c)); + } + + return (-1); +} + +#ifndef GCCCOMPILER +/* IO device file handles. */ +#define FH_STDIN 0x8001 +#define FH_STDOUT 0x8002 +#define FH_STDERR 0x8003 + +const char __stdin_name[] = ":STDIN"; +const char __stdout_name[] = ":STDOUT"; +const char __stderr_name[] = ":STDERR"; + +#define RETARGET_SYS 1 +#define RTE_Compiler_IO_STDOUT 1 +#define RTE_Compiler_IO_STDERR 1 +/** + Defined in rt_sys.h, this function opens a file. + + The _sys_open() function is required by fopen() and freopen(). These + functions in turn are required if any file input/output function is to + be used. + The openmode parameter is a bitmap whose bits mostly correspond directly to + the ISO mode specification. Target-dependent extensions are possible, but + freopen() must also be extended. + + \param[in] name File name + \param[in] openmode Mode specification bitmap + + \return The return value is ?1 if an error occurs. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +FILEHANDLE _sys_open (const char *name, int openmode) { +#if (!defined(RTE_Compiler_IO_File)) + (void)openmode; +#endif + + if (name == NULL) { + return (-1); + } + + if (name[0] == ':') { + if (strcmp(name, ":STDIN") == 0) { + return (FH_STDIN); + } + if (strcmp(name, ":STDOUT") == 0) { + return (FH_STDOUT); + } + if (strcmp(name, ":STDERR") == 0) { + return (FH_STDERR); + } + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_open(name, openmode)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function closes a file previously opened + with _sys_open(). + + This function must be defined if any input/output function is to be used. + + \param[in] fh File handle + + \return The return value is 0 if successful. A nonzero value indicates + an error. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_close (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (0); + case FH_STDOUT: + return (0); + case FH_STDERR: + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_close(fh)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function writes the contents of a buffer to a file + previously opened with _sys_open(). + + \note The mode parameter is here for historical reasons. It contains + nothing useful and must be ignored. + + \param[in] fh File handle + \param[in] buf Data buffer + \param[in] len Data length + \param[in] mode Ignore this parameter + + \return The return value is either: + - a positive number representing the number of characters not + written (so any nonzero return value denotes a failure of + some sort) + - a negative number indicating an error. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) { +#if (defined(RTE_Compiler_IO_STDOUT) || defined(RTE_Compiler_IO_STDERR)) + int ch; +#elif (!defined(RTE_Compiler_IO_File)) + (void)buf; + (void)len; +#endif + (void)mode; + + switch (fh) { + case FH_STDIN: + return (-1); + case FH_STDOUT: +#ifdef RTE_Compiler_IO_STDOUT + for (; len; len--) { + ch = *buf++; + + stdout_putchar(ch); + } +#endif + return (0); + case FH_STDERR: +#ifdef RTE_Compiler_IO_STDERR + for (; len; len--) { + ch = *buf++; + + stderr_putchar(ch); + } +#endif + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_write(fh, buf, len)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function reads the contents of a file into a buffer. + + Reading up to and including the last byte of data does not turn on the EOF + indicator. The EOF indicator is only reached when an attempt is made to read + beyond the last byte of data. The target-independent code is capable of + handling: + - the EOF indicator being returned in the same read as the remaining bytes + of data that precede the EOF + - the EOF indicator being returned on its own after the remaining bytes of + data have been returned in a previous read. + + \note The mode parameter is here for historical reasons. It contains + nothing useful and must be ignored. + + \param[in] fh File handle + \param[in] buf Data buffer + \param[in] len Data length + \param[in] mode Ignore this parameter + + \return The return value is one of the following: + - The number of bytes not read (that is, len - result number of + bytes were read). + - An error indication. + - An EOF indicator. The EOF indication involves the setting of + 0x80000000 in the normal result. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) { +#ifdef RTE_Compiler_IO_STDIN + int ch; +#elif (!defined(RTE_Compiler_IO_File)) + (void)buf; + (void)len; +#endif + (void)mode; + + switch (fh) { + case FH_STDIN: +#ifdef RTE_Compiler_IO_STDIN + ch = stdin_getchar(); + if (ch < 0) { + return ((int)(len | 0x80000000U)); + } + *buf++ = (uint8_t)ch; +#if (STDIN_ECHO != 0) + stdout_putchar(ch); +#endif + len--; + return ((int)(len)); +#else + return ((int)(len | 0x80000000U)); +#endif + case FH_STDOUT: + return (-1); + case FH_STDERR: + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_read(fh, buf, len)); +#endif +#else + return (-1); +#endif +} +#endif + + + + + +/** + Defined in rt_sys.h, this function determines if a file handle identifies + a terminal. + + When a file is connected to a terminal device, this function is used to + provide unbuffered behavior by default (in the absence of a call to + set(v)buf) and to prohibit seeking. + + \param[in] fh File handle + + \return The return value is one of the following values: + - 0: There is no interactive device. + - 1: There is an interactive device. + - other: An error occurred. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_istty (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (1); + case FH_STDOUT: + return (1); + case FH_STDERR: + return (1); + } + + return (0); +} +#endif + + +/** + Defined in rt_sys.h, this function puts the file pointer at offset pos from + the beginning of the file. + + This function sets the current read or write position to the new location pos + relative to the start of the current file fh. + + \param[in] fh File handle + \param[in] pos File pointer offset + + \return The result is: + - non-negative if no error occurs + - negative if an error occurs +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_seek (FILEHANDLE fh, long pos) { +#if (!defined(RTE_Compiler_IO_File)) + (void)pos; +#endif + + switch (fh) { + case FH_STDIN: + return (-1); + case FH_STDOUT: + return (-1); + case FH_STDERR: + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_seek(fh, (uint32_t)pos)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function returns the current length of a file. + + This function is used by _sys_seek() to convert an offset relative to the + end of a file into an offset relative to the beginning of the file. + You do not have to define _sys_flen() if you do not intend to use fseek(). + If you retarget at system _sys_*() level, you must supply _sys_flen(), + even if the underlying system directly supports seeking relative to the + end of a file. + + \param[in] fh File handle + + \return This function returns the current length of the file fh, + or a negative error indicator. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +long _sys_flen (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (0); + case FH_STDOUT: + return (0); + case FH_STDERR: + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_flen(fh)); +#endif +#else + return (0); +#endif +} +#endif + +#else /* gcc compiler */ +int _write(int file, + char *ptr, + int len) +{ + int i; + (void)file; + + for(i=0; i < len;i++) + { + stdout_putchar(*ptr++); + } + return len; +} + +#endif + +#define log_str(...) \ + do { \ + const char *pchSrc = __VA_ARGS__; \ + uint_fast16_t hwSize = sizeof(__VA_ARGS__); \ + do { \ + stdout_putchar(*pchSrc++); \ + } while(--hwSize); \ + } while(0) + +#ifdef GCCCOMPILER +void _exit(int return_code) +{ + (void)return_code; + log_str("\n"); + log_str("_[TEST COMPLETE]_________________________________________________\n"); + log_str("\n\n"); + stdout_putchar(4); + while(1); +} +#else +void _sys_exit(int n) +{ + (void)n; + log_str("\n"); + log_str("_[TEST COMPLETE]_________________________________________________\n"); + log_str("\n\n"); + stdout_putchar(4); + while(1); +} +#endif + +extern void ttywrch (int ch); +__attribute__((weak)) +void _ttywrch (int ch) +{ + ttywrch(ch); +} diff --git a/Platforms/IPSS/ARMCR8/Include/ARMCR8.h b/Platforms/IPSS/ARMCR8/Include/ARMCR8.h new file mode 100755 index 00000000..559424f5 --- /dev/null +++ b/Platforms/IPSS/ARMCR8/Include/ARMCR8.h @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file ARMCM7.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCM7 Device (configured for CM7 without FPU) + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCR8_H +#define ARMCR8_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ------------------- Processor Interrupt Numbers ------------------------------ */ + Interrupt0_IRQn = 0, + Interrupt1_IRQn = 1, + Interrupt2_IRQn = 2, + Interrupt3_IRQn = 3, + Interrupt4_IRQn = 4, + Interrupt5_IRQn = 5, + Interrupt6_IRQn = 6, + Interrupt7_IRQn = 7, + Interrupt8_IRQn = 8, + Interrupt9_IRQn = 9 + /* Interrupts 10 .. 224 are left out */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CR8_REV 0x0000U /* Core revision r0p0 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* no FPU present */ +#define __FPU_DP 1U /* unused */ +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U +#define __DTCM_PRESENT 1U + +#include "core_cr8.h" /* Processor and core peripherals */ +#include "system_ARMCR8.h" /* System Header */ + + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCR8/Include/system_ARMCR8.h b/Platforms/IPSS/ARMCR8/Include/system_ARMCR8.h new file mode 100755 index 00000000..ec831e09 --- /dev/null +++ b/Platforms/IPSS/ARMCR8/Include/system_ARMCR8.h @@ -0,0 +1,55 @@ +/**************************************************************************//** + * @file system_ARMCM7.h + * @brief CMSIS Device System Header File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_ARMCM7_H +#define SYSTEM_ARMCM7_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCR8/LinkScripts/AC6/lnk.sct b/Platforms/IPSS/ARMCR8/LinkScripts/AC6/lnk.sct new file mode 100755 index 00000000..cad81da2 --- /dev/null +++ b/Platforms/IPSS/ARMCR8/LinkScripts/AC6/lnk.sct @@ -0,0 +1,35 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +#include "mem_ARMCR8.h" + +LOAD_REGION 0x0 +{ + CODE +0 0x80000 + { + *.o (VECTORS, +First) + * (InRoot$$$Sections) + * (+RO-CODE) + } + + DATA 0x20000000 NOCOMPRESS 0x60000 + { + * (+RO-DATA) + * (+RW,+ZI) + } + + ARM_LIB_STACKHEAP 0x20062000 ALIGN 64 EMPTY 0x000052000 + {} + + +} + + + + + + diff --git a/Platforms/IPSS/ARMCR8/LinkScripts/AC6/mem_ARMCR8.h b/Platforms/IPSS/ARMCR8/LinkScripts/AC6/mem_ARMCR8.h new file mode 100755 index 00000000..8d110d1d --- /dev/null +++ b/Platforms/IPSS/ARMCR8/LinkScripts/AC6/mem_ARMCR8.h @@ -0,0 +1,38 @@ +/**************************************************************************//** + * @file mem_ARMCM7.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCR8_H +#define __MEM_ARMCR8_H + + + +#define STACK_SIZE 0x00003000 +#define HEAP_SIZE 0x00100000 + + + +#endif /* __MEM_ARMCR8_H */ diff --git a/Platforms/IPSS/ARMCR8/LinkScripts/GCC/lnk.ld b/Platforms/IPSS/ARMCR8/LinkScripts/GCC/lnk.ld new file mode 100755 index 00000000..6592a441 --- /dev/null +++ b/Platforms/IPSS/ARMCR8/LinkScripts/GCC/lnk.ld @@ -0,0 +1,239 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + * @version V2.0.0 + * @date 21. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mem_ARMCM7.h" + +__STACK_SIZE = 0x2000; +__HEAP_SIZE = 0x50000; + +MEMORY +{ + ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 512K + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + DTCM2 (xrw) : ORIGIN = 0x20020000, LENGTH = 384K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > ITCM + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ITCM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ITCM + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) +*/ + __copy_table_end__ = .; + } > ITCM + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) +*/ + __zero_table_end__ = .; + } > DTCM + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + + .data : + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > ITCM AT > DTCM + + __etext = ADDR(.data); + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > DTCM2 + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > DTCM2 + + .stack (ORIGIN(DTCM2) + LENGTH(DTCM2) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM2 + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds DTCM2 limit */ + ASSERT(__StackLimit >= __HeapLimit, "region DTCM2 overflowed with stack") +} + + + diff --git a/Platforms/IPSS/ARMCR8/LinkScripts/GCC/mem_ARMCR8.h b/Platforms/IPSS/ARMCR8/LinkScripts/GCC/mem_ARMCR8.h new file mode 100755 index 00000000..84a1ff1d --- /dev/null +++ b/Platforms/IPSS/ARMCR8/LinkScripts/GCC/mem_ARMCR8.h @@ -0,0 +1,38 @@ +/**************************************************************************//** + * @file mem_ARMCM7.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.1.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_ARMCM7_H +#define __MEM_ARMCM7_H + + + +#define STACK_SIZE 0x00003000 +#define HEAP_SIZE 0x00100000 + + + +#endif /* __MEM_ARMCM7_H */ diff --git a/Platforms/IPSS/ARMCR8/Startup/AC5/startup_ARMCR8.s b/Platforms/IPSS/ARMCR8/Startup/AC5/startup_ARMCR8.s new file mode 100755 index 00000000..333d3581 --- /dev/null +++ b/Platforms/IPSS/ARMCR8/Startup/AC5/startup_ARMCR8.s @@ -0,0 +1,168 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.4.0 +; * @date 12. December 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +#include "mem_ARMCM7.h" + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU STACK_SIZE + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU HEAP_SIZE + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + IF :LNOT::DEF:__MICROLIB + IMPORT __use_two_region_memory + ENDIF + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Platforms/IPSS/ARMCR8/Startup/AC6/startup.s b/Platforms/IPSS/ARMCR8/Startup/AC6/startup.s new file mode 100755 index 00000000..8b40cfc7 --- /dev/null +++ b/Platforms/IPSS/ARMCR8/Startup/AC6/startup.s @@ -0,0 +1,369 @@ +/****************************************************************************** + * @file startup_ARMCR8.c + * @brief Unvalidated Startup File for a Cortex-R8 Device + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +// Region size <256 bytes is unpredictable + +#define Region_256B 0b00111 +#define Region_512B 0b01000 +#define Region_1K 0b01001 +#define Region_2K 0b01010 +#define Region_4K 0b01011 +#define Region_8K 0b01100 +#define Region_16K 0b01101 +#define Region_32K 0b01110 +#define Region_64K 0b01111 +#define Region_128K 0b10000 +#define Region_256K 0b10001 +#define Region_512K 0b10010 +#define Region_1M 0b10011 +#define Region_2M 0b10100 +#define Region_4M 0b10101 +#define Region_8M 0b10110 +#define Region_16M 0b10111 +#define Region_32M 0b11000 +#define Region_64M 0b11001 +#define Region_128M 0b11010 +#define Region_256M 0b11011 +#define Region_512M 0b11100 +#define Region_1G 0b11101 +#define Region_2G 0b11110 +#define Region_4G 0b11111 + +#define Region_Enable 0b1 + +#define Execute_Never 0x1000 // Bit 12 + +#define Normal_nShared 0x03 // Outer and Inner write-back, no write-allocate +#define Device_nShared 0x10 + +#define Full_Access 0b011 +#define Read_Only 0b110 + +//---------------------------------------------------------------- + + .eabi_attribute Tag_ABI_align8_preserved,1 + + .section VECTORS,"ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Start + +Start: + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + B . // Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + + .balign 4 +Reset_Addr: .word Reset_Handler +Undefined_Addr: .word Undefined_Handler +SVC_Addr: .word SVC_Handler +Prefetch_Addr: .word Prefetch_Handler +Abort_Addr: .word Abort_Handler +IRQ_Addr: .word IRQ_Handler +FIQ_Addr: .word FIQ_Handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- + + .global Reset_Handler + .type Reset_Handler, "function" +Reset_Handler: + +//---------------------------------------------------------------- +// Disable MPU and caches +//---------------------------------------------------------------- + +// Disable MPU and cache in case it was left enabled from an earlier run +// This does not need to be done from a cold reset + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #0x05 // Disable MPU (M bit) and data cache (C bit) + BIC r0, r0, #0x800 // Disable branch prediction (Z bit) + BIC r0, r0, #0x1000 // Disable instruction cache (I bit) + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings + + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack using Linker symbol from scatter file. +// Stacks must be 8 byte aligned. +//---------------------------------------------------------------- + + .global Image$$ARM_LIB_STACKHEAP$$ZI$$Limit + LDR SP, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit + + +//---------------------------------------------------------------- +// Cache invalidation +//---------------------------------------------------------------- + + DSB + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 0 // invalidate I cache + MCR p15, 0, r0, c15, c5, 0 // invalidate D cache + +//---------------------------------------------------------------- +// TCM Configuration +//---------------------------------------------------------------- + +// Cortex-R8 optionally provides two Tightly-Coupled Memory (TCM) blocks (ITCM and DTCM) +// for fast access to code or data. +// ITCM typically holds interrupt or exception code that must be accessed at high speed, +// without any potential delay resulting from a cache miss. +// DTCM typically holds a block of data for intensive processing, such as audio or video data. + +// The following illustrates basic TCM configuration, as the basis for exploration by the user + + + .global Image$$CODE$$Base + .global Image$$DATA$$Base + + MRC p15, 0, r0, c0, c0, 2 // Read TCM Type Register + // r0 now contains ITCM & DTCM availability + + MRC p15, 0, r0, c9, c1, 1 // Read ITCM Region Register + // r0 now contains ITCM size in bits [5:2] + + LDR r0, =Image$$CODE$$Base // Set ITCM base address + ORR r0, r0, #1 // Enable it + MCR p15, 0, r0, c9, c1, 1 // Write ITCM Region Register + + MRC p15, 0, r0, c9, c1, 0 // Read DTCM Region Register + // r0 now contains DTCM size in bits [5:2] + + LDR r0, =Image$$DATA$$Base // Set DTCM base address + ORR r0, r0, #1 // Enable it + MCR p15, 0, r0, c9, c1, 0 // Write DTCM Region Register + + + + MRC p15, 0, r0, c1, c0, 1 + TST r0, #(1 << 6) // SMP bit + ORREQ r0, r0, #(1 << 6) // Set SMP bit in aux control register + MCREQ p15, 0, r0, c1, c0, 1 // write Aux Control Register (ACTLR) + +//---------------------------------------------------------------- +// MPU Configuration +//---------------------------------------------------------------- + +// Notes: +// * Regions apply to both instruction and data accesses. +// * Each region base address must be a multiple of its size +// * Any address range not covered by an enabled region will abort +// * The region at 0x0 over the Vector table is needed to support semihosting + +// Region 0: Code Base = 0x0000 Size = 32KB Normal Non-shared Read-only Executable +// Region 1: Data Base = 0x40000 Size = 128KB Normal Non-shared Full access Not Executable +// Region 2: Stack/Heap Base = 0x100000 Size = 64KB Normal Non-shared Full access Not Executable +// Region 3: Vectors Base = 0x0000 Size = 1KB Normal Non-shared Full access Executable +// Region 4: Peripherals Base = 0xB0000000 Limit = 0xBFFFFFC0 Device Full access Not Executable + + // Import linker symbols to get region base addresses + .global Image$$CODE$$Base + .global Image$$DATA$$Base + .global Image$$ARM_LIB_STACKHEAP$$Base + + // Region 0 - Code + MOV r1, #0 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$CODE$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_1M << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 1 - Data + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$DATA$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_1M << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 2 - Stack/Heap + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$ARM_LIB_STACKHEAP$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_1M << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 3 - Vectors + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =0 + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_1K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 4 - Peripherals + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =0xB0000000 + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_1K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Device_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Disable all higher priority regions (assumes unified regions, which is always true for Cortex-R8) + MRC p15, 0, r0, c0, c0, 4 // Read MPU Type register (MPUIR) + LSR r0, r0, #8 + AND r0, r0, #0xff // r0 = Number of MPU regions (12, 16, 20, or 24 for Cortex-R8) + MOV r2, #0 // Value to write to disable region +region_loop: + ADD r1, r1, #1 + CMP r0, r1 + BLS regions_done + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register (RGNR) + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register (DRSR) + B region_loop +regions_done: + + +#ifdef __ARM_FP +//---------------------------------------------------------------- +// Enable access to VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + + // + // SMP initialization + // ------------------- + MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register + ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field + BNE secondaryCPUsInit + +//---------------------------------------------------------------- +// Enable MPU and branch to C library init +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #0x01 // Set M bit to enable MPU + ORR r0, r0, #0x800 // Set Z bit to enable branch prediction + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings + + .global __main + B __main + + .size Reset_Handler, . - Reset_Handler + + +// ------------------------------------------------------------ +// Initialization for SECONDARY CPUs +// ------------------------------------------------------------ + + .global secondaryCPUsInit + .type secondaryCPUsInit, "function" +secondaryCPUsInit: + wfi + + +//---------------------------------------------------------------- +// Global Enable for Instruction and Data Caching +//---------------------------------------------------------------- + + .global enable_caches + .type enable_caches, "function" + .cfi_startproc +enable_caches: + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // enable I Cache + ORR r0, r0, #(0x1 << 2) // enable D Cache + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + .cfi_endproc + + .size enable_caches, . - enable_caches diff --git a/Platforms/IPSS/ARMCR8/Startup/AC6/startup_ARMCR8.c b/Platforms/IPSS/ARMCR8/Startup/AC6/startup_ARMCR8.c new file mode 100755 index 00000000..415c23ef --- /dev/null +++ b/Platforms/IPSS/ARMCR8/Startup/AC6/startup_ARMCR8.c @@ -0,0 +1,155 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCR8) + #include "ARMCR8.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[240]; + const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Platforms/IPSS/ARMCR8/Startup/GCC/startup_ARMCR8.c b/Platforms/IPSS/ARMCR8/Startup/GCC/startup_ARMCR8.c new file mode 100755 index 00000000..8b99812c --- /dev/null +++ b/Platforms/IPSS/ARMCR8/Startup/GCC/startup_ARMCR8.c @@ -0,0 +1,165 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[240]; + const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#define SERIAL_BASE_ADDRESS (0xA8000000ul) + +#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS) + + + + + + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + + + __PROGRAM_START(); +} + + + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + + diff --git a/Platforms/IPSS/ARMCR8/Startup/GCC/support.c b/Platforms/IPSS/ARMCR8/Startup/GCC/support.c new file mode 100755 index 00000000..6a6d4f44 --- /dev/null +++ b/Platforms/IPSS/ARMCR8/Startup/GCC/support.c @@ -0,0 +1,36 @@ + +#ifdef __cplusplus +extern "C" +{ +#endif + +char * _sbrk(int incr); + +void __malloc_lock() ; +void __malloc_unlock(); + +char __end__, __HeapLimit; // make sure to define these symbols in linker command file +#ifdef __cplusplus +} +#endif + +static int totalBytesProvidedBySBRK = 0; + +//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file). +char * sbrk(int incr) { + static char *currentHeapEnd = &__end__; + char *previousHeapEnd = currentHeapEnd; + if (currentHeapEnd + incr > &__HeapLimit) { + return (char *)-1; // the malloc-family routine that called sbrk will return 0 + } + currentHeapEnd += incr; + + totalBytesProvidedBySBRK += incr; + + return (char *) previousHeapEnd; +} +//! Synonym for sbrk. +char * _sbrk(int incr) { return sbrk(incr); }; + +void __malloc_lock() { }; +void __malloc_unlock() { }; \ No newline at end of file diff --git a/Platforms/IPSS/ARMCR8/mmu_ARMCR8.c b/Platforms/IPSS/ARMCR8/mmu_ARMCR8.c new file mode 100755 index 00000000..b4ced0b0 --- /dev/null +++ b/Platforms/IPSS/ARMCR8/mmu_ARMCR8.c @@ -0,0 +1,198 @@ +/**************************************************************************//** + * @file mmu_ARMCA32.c + * @brief MMU Configuration for Arm Cortex-A32 Device Series + * @version V1.2.0 + * @date 15. May 2019 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map + + Memory Type +0xffffffff |--------------------------| ------------ + | FLAG SYNC | Device Memory +0xfffff000 |--------------------------| ------------ + | Fault | Fault +0xfff00000 |--------------------------| ------------ + | | Normal + | | + | Daughterboard | + | memory | + | | +0x80505000 |--------------------------| ------------ + |TTB (L2 Sync Flags ) 4k | Normal +0x80504C00 |--------------------------| ------------ + |TTB (L2 Peripherals-B) 16k| Normal +0x80504800 |--------------------------| ------------ + |TTB (L2 Peripherals-A) 16k| Normal +0x80504400 |--------------------------| ------------ + |TTB (L2 Priv Periphs) 4k | Normal +0x80504000 |--------------------------| ------------ + | TTB (L1 Descriptors) | Normal +0x80500000 |--------------------------| ------------ + | Stack | Normal + |--------------------------| ------------ + | Heap | Normal +0x80400000 |--------------------------| ------------ + | ZI Data | Normal +0x80300000 |--------------------------| ------------ + | RW Data | Normal +0x80200000 |--------------------------| ------------ + | RO Data | Normal + |--------------------------| ------------ + | RO Code | USH Normal +0x80000000 |--------------------------| ------------ + | Daughterboard | Fault + | HSB AXI buses | +0x40000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x2c002000 |--------------------------| ------------ + | Private Address | Device Memory +0x2c000000 |--------------------------| ------------ + | Daughterboard | Fault + | test chips peripherals | +0x20000000 |--------------------------| ------------ + | Peripherals | Device Memory RW/RO + | | & Fault +0x00000000 |--------------------------| +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 + +#include "ARMCR8.h" +#include "mem_ARMCR8.h" + +#if 0 + +// TTB base address +#define TTB_BASE ((uint32_t*)__TTB_BASE) + +// L2 table pointers +//---------------------------------------- +#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core + // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. + // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. + +#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space +#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF +#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF +#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization + +//--------------------- PERIPHERALS ------------------- +#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) +#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) + +//--------------------- SYNC FLAGS -------------------- +#define FLAG_SYNC 0xFFFFF000 +#define F_SYNC_BASE 0xFFF00000 //1M aligned + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; + + //Create 4GB of faulting entries + MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); + + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Define Image + MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections + MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections + + //--------------------- PERIPHERALS ------------------- + MMU_TTSection (TTB_BASE, VE_A32_PERIPH , 64, Sect_Device_RW); // 64MB NOR + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x1 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x01 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x0 (Inner WB WA) */ + __set_TTBR0(__TTB_BASE | 0x48); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} + +#endif \ No newline at end of file diff --git a/Platforms/IPSS/ARMCR8/system_ARMCR8.c b/Platforms/IPSS/ARMCR8/system_ARMCR8.c new file mode 100755 index 00000000..7eaabb0d --- /dev/null +++ b/Platforms/IPSS/ARMCR8/system_ARMCR8.c @@ -0,0 +1,573 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include +#include + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) +#include +#else +#define GCCCOMPILER +struct __FILE {int handle;}; +FILE __stdout; +FILE __stdin; +FILE __stderr; +#endif + + +#if defined (ARMCR8) + #include "ARMCR8.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +//#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +// extern uint32_t __VECTOR_TABLE; +//#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define SERIAL_BASE_ADDRESS (0xb0000000ul) + +#define SERIAL_DATA *((volatile unsigned *) SERIAL_BASE_ADDRESS) + +#define SOFTWARE_MARK *((volatile unsigned *) (SERIAL_BASE_ADDRESS+4)) + +void start_ipss_measurement() +{ + SOFTWARE_MARK = 1; +} + +void stop_ipss_measurement() +{ + SOFTWARE_MARK = 0; +} + + + +int stdout_putchar(char txchar) +{ + SERIAL_DATA = txchar; + return(txchar); +} + +int stderr_putchar(char txchar) +{ + return stdout_putchar(txchar); +} + +void ttywrch (int ch) +{ + stdout_putchar(ch); +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if 0 +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; + #endif +} + +#if __IS_COMPILER_ARM_COMPILER_6__ +__asm(".global __use_no_semihosting\n\t"); +# ifndef __MICROLIB +__asm(".global __ARM_use_no_argv\n\t"); +# endif +#endif + +/** + Writes the character specified by c (converted to an unsigned char) to + the output stream pointed to by stream, at the position indicated by the + associated file position indicator (if defined), and advances the + indicator appropriately. If the file position indicator is not defined, + the character is appended to the output stream. + + \param[in] c Character + \param[in] stream Stream handle + + \return The character written. If a write error occurs, the error + indicator is set and fputc returns EOF. +*/ +__attribute__((weak)) +int fputc (int c, FILE * stream) +{ + if (stream == &__stdout) { + return (stdout_putchar(c)); + } + + if (stream == &__stderr) { + return (stderr_putchar(c)); + } + + return (-1); +} + +#ifndef GCCCOMPILER +/* IO device file handles. */ +#define FH_STDIN 0x8001 +#define FH_STDOUT 0x8002 +#define FH_STDERR 0x8003 + +const char __stdin_name[] = ":STDIN"; +const char __stdout_name[] = ":STDOUT"; +const char __stderr_name[] = ":STDERR"; + +#define RETARGET_SYS 1 +#define RTE_Compiler_IO_STDOUT 1 +#define RTE_Compiler_IO_STDERR 1 +/** + Defined in rt_sys.h, this function opens a file. + + The _sys_open() function is required by fopen() and freopen(). These + functions in turn are required if any file input/output function is to + be used. + The openmode parameter is a bitmap whose bits mostly correspond directly to + the ISO mode specification. Target-dependent extensions are possible, but + freopen() must also be extended. + + \param[in] name File name + \param[in] openmode Mode specification bitmap + + \return The return value is ?1 if an error occurs. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +FILEHANDLE _sys_open (const char *name, int openmode) { +#if (!defined(RTE_Compiler_IO_File)) + (void)openmode; +#endif + + if (name == NULL) { + return (-1); + } + + if (name[0] == ':') { + if (strcmp(name, ":STDIN") == 0) { + return (FH_STDIN); + } + if (strcmp(name, ":STDOUT") == 0) { + return (FH_STDOUT); + } + if (strcmp(name, ":STDERR") == 0) { + return (FH_STDERR); + } + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_open(name, openmode)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function closes a file previously opened + with _sys_open(). + + This function must be defined if any input/output function is to be used. + + \param[in] fh File handle + + \return The return value is 0 if successful. A nonzero value indicates + an error. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_close (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (0); + case FH_STDOUT: + return (0); + case FH_STDERR: + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_close(fh)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function writes the contents of a buffer to a file + previously opened with _sys_open(). + + \note The mode parameter is here for historical reasons. It contains + nothing useful and must be ignored. + + \param[in] fh File handle + \param[in] buf Data buffer + \param[in] len Data length + \param[in] mode Ignore this parameter + + \return The return value is either: + - a positive number representing the number of characters not + written (so any nonzero return value denotes a failure of + some sort) + - a negative number indicating an error. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) { +#if (defined(RTE_Compiler_IO_STDOUT) || defined(RTE_Compiler_IO_STDERR)) + int ch; +#elif (!defined(RTE_Compiler_IO_File)) + (void)buf; + (void)len; +#endif + (void)mode; + + switch (fh) { + case FH_STDIN: + return (-1); + case FH_STDOUT: +#ifdef RTE_Compiler_IO_STDOUT + for (; len; len--) { + ch = *buf++; + + stdout_putchar(ch); + } +#endif + return (0); + case FH_STDERR: +#ifdef RTE_Compiler_IO_STDERR + for (; len; len--) { + ch = *buf++; + + stderr_putchar(ch); + } +#endif + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_write(fh, buf, len)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function reads the contents of a file into a buffer. + + Reading up to and including the last byte of data does not turn on the EOF + indicator. The EOF indicator is only reached when an attempt is made to read + beyond the last byte of data. The target-independent code is capable of + handling: + - the EOF indicator being returned in the same read as the remaining bytes + of data that precede the EOF + - the EOF indicator being returned on its own after the remaining bytes of + data have been returned in a previous read. + + \note The mode parameter is here for historical reasons. It contains + nothing useful and must be ignored. + + \param[in] fh File handle + \param[in] buf Data buffer + \param[in] len Data length + \param[in] mode Ignore this parameter + + \return The return value is one of the following: + - The number of bytes not read (that is, len - result number of + bytes were read). + - An error indication. + - An EOF indicator. The EOF indication involves the setting of + 0x80000000 in the normal result. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) { +#ifdef RTE_Compiler_IO_STDIN + int ch; +#elif (!defined(RTE_Compiler_IO_File)) + (void)buf; + (void)len; +#endif + (void)mode; + + switch (fh) { + case FH_STDIN: +#ifdef RTE_Compiler_IO_STDIN + ch = stdin_getchar(); + if (ch < 0) { + return ((int)(len | 0x80000000U)); + } + *buf++ = (uint8_t)ch; +#if (STDIN_ECHO != 0) + stdout_putchar(ch); +#endif + len--; + return ((int)(len)); +#else + return ((int)(len | 0x80000000U)); +#endif + case FH_STDOUT: + return (-1); + case FH_STDERR: + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_read(fh, buf, len)); +#endif +#else + return (-1); +#endif +} +#endif + + + + + +/** + Defined in rt_sys.h, this function determines if a file handle identifies + a terminal. + + When a file is connected to a terminal device, this function is used to + provide unbuffered behavior by default (in the absence of a call to + set(v)buf) and to prohibit seeking. + + \param[in] fh File handle + + \return The return value is one of the following values: + - 0: There is no interactive device. + - 1: There is an interactive device. + - other: An error occurred. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_istty (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (1); + case FH_STDOUT: + return (1); + case FH_STDERR: + return (1); + } + + return (0); +} +#endif + + +/** + Defined in rt_sys.h, this function puts the file pointer at offset pos from + the beginning of the file. + + This function sets the current read or write position to the new location pos + relative to the start of the current file fh. + + \param[in] fh File handle + \param[in] pos File pointer offset + + \return The result is: + - non-negative if no error occurs + - negative if an error occurs +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +int _sys_seek (FILEHANDLE fh, long pos) { +#if (!defined(RTE_Compiler_IO_File)) + (void)pos; +#endif + + switch (fh) { + case FH_STDIN: + return (-1); + case FH_STDOUT: + return (-1); + case FH_STDERR: + return (-1); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_seek(fh, (uint32_t)pos)); +#endif +#else + return (-1); +#endif +} +#endif + + +/** + Defined in rt_sys.h, this function returns the current length of a file. + + This function is used by _sys_seek() to convert an offset relative to the + end of a file into an offset relative to the beginning of the file. + You do not have to define _sys_flen() if you do not intend to use fseek(). + If you retarget at system _sys_*() level, you must supply _sys_flen(), + even if the underlying system directly supports seeking relative to the + end of a file. + + \param[in] fh File handle + + \return This function returns the current length of the file fh, + or a negative error indicator. +*/ +#ifdef RETARGET_SYS +__attribute__((weak)) +long _sys_flen (FILEHANDLE fh) { + + switch (fh) { + case FH_STDIN: + return (0); + case FH_STDOUT: + return (0); + case FH_STDERR: + return (0); + } + +#ifdef RTE_Compiler_IO_File +#ifdef RTE_Compiler_IO_File_FS + return (__sys_flen(fh)); +#endif +#else + return (0); +#endif +} +#endif + +#else /* gcc compiler */ +int _write(int file, + char *ptr, + int len) +{ + int i; + (void)file; + + for(i=0; i < len;i++) + { + stdout_putchar(*ptr++); + } + return len; +} + +#endif + +#define log_str(...) \ + do { \ + const char *pchSrc = __VA_ARGS__; \ + uint_fast16_t hwSize = sizeof(__VA_ARGS__); \ + do { \ + stdout_putchar(*pchSrc++); \ + } while(--hwSize); \ + } while(0) + +#ifdef GCCCOMPILER +void _exit(int return_code) +{ + (void)return_code; + log_str("\n"); + log_str("_[TEST COMPLETE]_________________________________________________\n"); + log_str("\n\n"); + stdout_putchar(4); + while(1); +} +#else +void _sys_exit(int n) +{ + (void)n; + log_str("\n"); + log_str("_[TEST COMPLETE]_________________________________________________\n"); + log_str("\n\n"); + stdout_putchar(4); + while(1); +} +#endif + +extern void ttywrch (int ch); +__attribute__((weak)) +void _ttywrch (int ch) +{ + ttywrch(ch); +} diff --git a/Testing/FrameworkSource/Timing.cpp b/Testing/FrameworkSource/Timing.cpp index b7c2b591..fe14cd10 100644 --- a/Testing/FrameworkSource/Timing.cpp +++ b/Testing/FrameworkSource/Timing.cpp @@ -52,9 +52,9 @@ static uint32_t startCycles=0; #else #warning "no appropriate header file found!" #endif -#endif +#endif /* CORTEXM*/ -#ifdef CORTEXA +#if defined(CORTEXA) || defined(CORTEXR) #include "cmsis_cp15.h" unsigned int startCycles; @@ -74,7 +74,7 @@ void initCycleMeasurement() SysTick->CTRL = 0; #endif -#ifdef CORTEXA +#if defined(CORTEXA) || defined(CORTEXR) // in general enable all counters (including cycle counter) int32_t value = 1; @@ -123,7 +123,7 @@ void cycleMeasurementStart() #endif -#ifdef CORTEXA +#if defined(CORTEXA) || defined(CORTEXR) unsigned int value; // Read CCNT Register __get_CP(15, 0, value, 9, 13, 0); @@ -159,7 +159,7 @@ Testing::cycles_t getCycles() return(result); #endif -#ifdef CORTEXA +#if defined(CORTEXA) || defined(CORTEXR) unsigned int value; // Read CCNT Register __get_CP(15, 0, value, 9, 13, 0); diff --git a/Testing/createDb.sql b/Testing/createDb.sql index 293a0c78..1c74cc1e 100755 --- a/Testing/createDb.sql +++ b/Testing/createDb.sql @@ -111,6 +111,9 @@ INSERT INTO CORE VALUES(17,"m33","M33"); INSERT INTO CORE VALUES(18,"m4","M4"); INSERT INTO CORE VALUES(19,"m55 mve","M55"); INSERT INTO CORE VALUES(20,"m55 scalar","M55SCALAR"); +INSERT INTO CORE VALUES(21,"r8","ARMCR8"); +INSERT INTO CORE VALUES(22,"r5","ARMCR5"); +INSERT INTO CORE VALUES(23,"a32","ARMCA32"); .quit diff --git a/Testing/extractDb.py b/Testing/extractDb.py index 2f0a47ec..b256808c 100755 --- a/Testing/extractDb.py +++ b/Testing/extractDb.py @@ -17,6 +17,15 @@ lastID="""SELECT runid FROM RUN ORDER BY runid DESC LIMIT 1 lastIDAndDate="""SELECT date FROM RUN WHERE runid=? """ +def joinit(iterable, delimiter): + # Intersperse a delimiter between element of a list + it = iter(iterable) + yield next(it) + for x in it: + yield delimiter + yield x + + def getLastRunID(): r=c.execute(lastID) return(int(r.fetchone()[0])) @@ -45,8 +54,14 @@ c = sqlite3.connect(args.b) if args.others: if len(args.others) == 1: - runid=int(args.others[0]) - runidval = (runid,) + if re.search(r'[,]',args.others[0]): + runidval=tuple([int(x) for x in args.others[0].split(",")]) + runidCMD=["runid == ?" for x in runidval] + runidCMD = "".join(joinit(runidCMD," OR ")) + runidCMD = "(" + runidCMD + ")" + else: + runid=int(args.others[0]) + runidval = (runid,) else: runidCMD = "runid >= ? AND runid <= ?" runid=int(args.others[1]) diff --git a/Toolchain/AC5.cmake b/Toolchain/AC5.cmake index 5110b068..a5f37da9 100755 --- a/Toolchain/AC5.cmake +++ b/Toolchain/AC5.cmake @@ -95,14 +95,38 @@ function(toolchainSpecificLinkForCortexA PROJECTNAME ROOT CORE PLATFORMFOLDER) endfunction() +function(toolchainSpecificLinkForCortexR PROJECTNAME ROOT CORE PLATFORMFOLDER) + target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/AC5/startup_${CORE}.c) + + + # RTE Components.h + target_include_directories(${PROJECTNAME} PRIVATE ${ROOT}/CMSIS/DSP/Testing) + + set(SCATTERFILE "${PLATFORMFOLDER}/${CORE}/LinkScripts/AC5/lnk.sct") + + set_target_properties(${PROJECTNAME} PROPERTIES LINK_DEPENDS "${SCATTERFILE};${PLATFORMFOLDER}/${CORE}/LinkScripts/AC5/mem_${CORE}.h") + + target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/LinkScripts/AC5) + + #target_link_options(${PROJECTNAME} PRIVATE "--info=sizes") + target_link_options(${PROJECTNAME} PRIVATE "--entry=Vectors;--scatter=${SCATTERFILE}") + +endfunction() + function(compilerSpecificPlatformConfigLibForM PROJECTNAME ROOT) endfunction() function(compilerSpecificPlatformConfigLibForA PROJECTNAME ROOT) endfunction() +function(compilerSpecificPlatformConfigLibForR PROJECTNAME ROOT) +endfunction() + function(compilerSpecificPlatformConfigAppForM PROJECTNAME ROOT) endfunction() function(compilerSpecificPlatformConfigAppForA PROJECTNAME ROOT) +endfunction() + +function(compilerSpecificPlatformConfigAppForR PROJECTNAME ROOT) endfunction() \ No newline at end of file diff --git a/Toolchain/AC6.cmake b/Toolchain/AC6.cmake index fef87429..94af8802 100644 --- a/Toolchain/AC6.cmake +++ b/Toolchain/AC6.cmake @@ -80,6 +80,14 @@ function(compilerSpecificCompileOptions PROJECTNAME ROOT) endif() endif() + if (ARM_CPU STREQUAL "cortex-r8" ) + target_compile_options(${PROJECTNAME} PUBLIC "-mfpu=vfpv3-d16-fp16") + endif() + + if (ARM_CPU STREQUAL "cortex-r5" ) + target_compile_options(${PROJECTNAME} PUBLIC "-mfpu=vfpv3") + endif() + if(EXPERIMENTAL) experimentalCompilerSpecificCompileOptions(${PROJECTNAME} ${ROOT}) @@ -125,14 +133,39 @@ function(toolchainSpecificLinkForCortexA PROJECTNAME ROOT CORE PLATFORMFOLDER) endfunction() +function(toolchainSpecificLinkForCortexR PROJECTNAME ROOT CORE PLATFORMFOLDER) + #target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/AC6/startup_${CORE}.c) + target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/AC6/startup.s) + + + # RTE Components.h + target_include_directories(${PROJECTNAME} PRIVATE ${ROOT}/CMSIS/DSP/Testing) + + set(SCATTERFILE "${PLATFORMFOLDER}/${CORE}/LinkScripts/AC6/lnk.sct") + + set_target_properties(${PROJECTNAME} PROPERTIES LINK_DEPENDS "${SCATTERFILE};${PLATFORMFOLDER}/${CORE}/LinkScripts/AC6/mem_${CORE}.h") + + target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/LinkScripts/AC6) + + #target_link_options(${PROJECTNAME} PRIVATE "--info=sizes") + target_link_options(${PROJECTNAME} PRIVATE "--entry=Reset_Handler;--scatter=${SCATTERFILE}") + +endfunction() + function(compilerSpecificPlatformConfigLibForM PROJECTNAME ROOT) endfunction() function(compilerSpecificPlatformConfigLibForA PROJECTNAME ROOT) endfunction() +function(compilerSpecificPlatformConfigLibForR PROJECTNAME ROOT) +endfunction() + function(compilerSpecificPlatformConfigAppForM PROJECTNAME ROOT) endfunction() function(compilerSpecificPlatformConfigAppForA PROJECTNAME ROOT) +endfunction() + +function(compilerSpecificPlatformConfigAppForR PROJECTNAME ROOT) endfunction() \ No newline at end of file diff --git a/Toolchain/GCC.cmake b/Toolchain/GCC.cmake index e6d679ab..818f92a2 100644 --- a/Toolchain/GCC.cmake +++ b/Toolchain/GCC.cmake @@ -158,6 +158,24 @@ function(toolchainSpecificLinkForCortexA PROJECTNAME ROOT CORE PLATFORMFOLDER) target_link_options(${PROJECTNAME} PRIVATE "--entry=Reset_Handler;-T${SCATTERFILE}") endfunction() +function(toolchainSpecificLinkForCortexR PROJECTNAME ROOT CORE PLATFORMFOLDER) + target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/GCC/startup_${CORE}.c) + target_sources(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Startup/GCC/support.c) + + # RTE Components + target_include_directories(${PROJECTNAME} PRIVATE ${ROOT}/CMSIS/DSP/Testing) + target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/LinkScripts/GCC) + + file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/tempLink) + set(SCATTERFILE ${CMAKE_CURRENT_BINARY_DIR}/tempLink/lnk.ld) + preprocessScatter(${CORE} ${PLATFORMFOLDER} ${SCATTERFILE}) + + + set_target_properties(${PROJECTNAME} PROPERTIES LINK_DEPENDS "${SCATTERFILE}") + + target_link_options(${PROJECTNAME} PRIVATE "--entry=Reset_Handler;-T${SCATTERFILE}") +endfunction() + function(compilerSpecificPlatformConfigLibForM PROJECTNAME ROOT) if (SEMIHOSTING) target_link_options(${PROJECTNAME} PRIVATE "--specs=rdimon.specs") @@ -178,6 +196,16 @@ function(compilerSpecificPlatformConfigLibForA PROJECTNAME ROOT) endif() endfunction() +function(compilerSpecificPlatformConfigLibForR PROJECTNAME ROOT) + if (SEMIHOSTING) + target_link_options(${PROJECTNAME} PRIVATE "--specs=rdimon.specs") + target_compile_options(${PROJECTNAME} PRIVATE "--specs=rdimon.specs") + else() + target_link_options(${PROJECTNAME} PRIVATE "--specs=nosys.specs") + target_compile_options(${PROJECTNAME} PRIVATE "--specs=nosys.specs") + endif() +endfunction() + function(compilerSpecificPlatformConfigAppForM PROJECTNAME ROOT) if (SEMIHOSTING) target_link_options(${PROJECTNAME} PRIVATE "--specs=rdimon.specs") @@ -200,5 +228,15 @@ function(compilerSpecificPlatformConfigAppForA PROJECTNAME ROOT) target_compile_options(${PROJECTNAME} PRIVATE "--specs=nosys.specs") endif() - endfunction() + +function(compilerSpecificPlatformConfigAppForR PROJECTNAME ROOT) + if (SEMIHOSTING) + target_link_options(${PROJECTNAME} PRIVATE "--specs=rdimon.specs") + target_compile_options(${PROJECTNAME} PRIVATE "--specs=rdimon.specs") + else() + target_link_options(${PROJECTNAME} PRIVATE "--specs=nosys.specs") + target_compile_options(${PROJECTNAME} PRIVATE "--specs=nosys.specs") + endif() + +endfunction() \ No newline at end of file diff --git a/configBoot.cmake b/configBoot.cmake index bb0cd890..0c869004 100755 --- a/configBoot.cmake +++ b/configBoot.cmake @@ -37,6 +37,22 @@ function(cortexa CORE PROJECT_NAME ROOT PLATFORMFOLDER) SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE) endfunction() +function(cortexr CORE PROJECT_NAME ROOT PLATFORMFOLDER) + target_include_directories(${PROJECT_NAME} PRIVATE ${CORER}/Include) + + #target_sources(${PROJECT_NAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/irq_ctrl_gic.c) + target_sources(${PROJECT_NAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/mmu_${CORE}.c) + target_sources(${PROJECT_NAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/system_${CORE}.c) + + + target_compile_definitions(${PROJECT_NAME} PRIVATE -DCMSIS_device_header="${CORE}.h") + + toolchainSpecificLinkForCortexR(${PROJECT_NAME} ${ROOT} ${CORE} ${PLATFORMFOLDER}) + + configplatformForApp(${PROJECT_NAME} ${ROOT} ${CORE} ${PLATFORMFOLDER}) + SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE) +endfunction() + function(configboot PROJECT_NAME ROOT PLATFORMFOLDER) target_include_directories(${PROJECT_NAME} PRIVATE ${ROOT}/CMSIS/DSP/Include) @@ -74,6 +90,15 @@ function(configboot PROJECT_NAME ROOT PLATFORMFOLDER) endif() + ################### + # + # Cortex cortex-r + # + if (ARM_CPU MATCHES "^[cC]ortex-[rR].*") + cortexr(${CORE} ${PROJECT_NAME} ${ROOT} ${PLATFORMFOLDER}) + + endif() + SET(PLATFORMID ${PLATFORMID} PARENT_SCOPE) endfunction() diff --git a/configCore.cmake b/configCore.cmake index 88bb2f91..137aef85 100644 --- a/configCore.cmake +++ b/configCore.cmake @@ -3,6 +3,8 @@ cmake_policy(SET CMP0077 NEW) # Config core SET(CORTEXM ON) +SET(CORTEXA OFF) +SET(CORTEXR OFF) option(HARDFP "Hard floating point" ON) option(LITTLEENDIAN "Little endian" ON) @@ -34,6 +36,8 @@ function(configcore PROJECTNAME ROOT) if (ARM_CPU MATCHES "^[cC]ortex-[aA]32([^0-9].*)?$" ) target_include_directories(${PROJECTNAME} PUBLIC "${ROOT}/CMSIS/Core_A/Include") SET(CORTEXM OFF) + SET(CORTEXA ON) + SET(CORTEXR OFF) target_compile_definitions(${PROJECTNAME} PRIVATE ARMv8A) target_compile_definitions(${PROJECTNAME} PUBLIC CORTEXA) @@ -46,6 +50,8 @@ function(configcore PROJECTNAME ROOT) if (ARM_CPU MATCHES "^[cC]ortex-[aA]15([^0-9].*)?$" ) target_include_directories(${PROJECTNAME} PUBLIC "${ROOT}/CMSIS/Core_A/Include") SET(CORTEXM OFF) + SET(CORTEXA ON) + SET(CORTEXR OFF) target_compile_definitions(${PROJECTNAME} PRIVATE ARMv7A) target_compile_definitions(${PROJECTNAME} PUBLIC CORTEXA) @@ -58,6 +64,8 @@ function(configcore PROJECTNAME ROOT) if (ARM_CPU MATCHES "^[cC]ortex-[aA]9([^0-9].*)?$" ) target_include_directories(${PROJECTNAME} PUBLIC "${ROOT}/CMSIS/Core_A/Include") SET(CORTEXM OFF) + SET(CORTEXA ON) + SET(CORTEXR OFF) target_compile_definitions(${PROJECTNAME} PRIVATE ARMv7A) target_compile_definitions(${PROJECTNAME} PUBLIC CORTEXA) @@ -71,6 +79,8 @@ function(configcore PROJECTNAME ROOT) if (ARM_CPU MATCHES "^[cC]ortex-[aA]7([^0-9].*)?$" ) target_include_directories(${PROJECTNAME} PUBLIC "${ROOT}/CMSIS/Core_A/Include") SET(CORTEXM OFF) + SET(CORTEXA ON) + SET(CORTEXR OFF) target_compile_definitions(${PROJECTNAME} PUBLIC CORTEXA) target_compile_definitions(${PROJECTNAME} PRIVATE ARMv7A) @@ -85,6 +95,8 @@ function(configcore PROJECTNAME ROOT) if (ARM_CPU MATCHES "^[cC]ortex-[aA]5([^0-9].*)?$" ) target_include_directories(${PROJECTNAME} PUBLIC "${ROOT}/CMSIS/Core_A/Include") SET(CORTEXM OFF) + SET(CORTEXA ON) + SET(CORTEXR OFF) target_compile_definitions(${PROJECTNAME} PUBLIC CORTEXA) target_compile_definitions(${PROJECTNAME} PRIVATE ARMv7A) @@ -94,6 +106,43 @@ function(configcore PROJECTNAME ROOT) SET(COREID ARMCA5 PARENT_SCOPE) endif() + ################### + # + # CORTEX-R + # + + # CORTEX-R8 + if (ARM_CPU MATCHES "^[cC]ortex-[rR]8([^0-9].*)?$" ) + target_include_directories(${PROJECTNAME} PUBLIC "${CORER}/Include") + target_compile_definitions(${PROJECTNAME} PRIVATE ARMCR8) + + SET(CORTEXM OFF) + SET(CORTEXA OFF) + SET(CORTEXR ON) + target_compile_definitions(${PROJECTNAME} PRIVATE ARMv7R) + + target_compile_definitions(${PROJECTNAME} PUBLIC CORTEXR) + SET(HARDFP ON) + SET(LITTLEENDIAN ON) + SET(COREID ARMCR8 PARENT_SCOPE) + endif() + + # CORTEX-R5 + if (ARM_CPU MATCHES "^[cC]ortex-[rR]5([^0-9].*)?$" ) + target_include_directories(${PROJECTNAME} PUBLIC "${CORER}/Include") + target_compile_definitions(${PROJECTNAME} PRIVATE ARMCR5) + + SET(CORTEXM OFF) + SET(CORTEXA OFF) + SET(CORTEXR ON) + target_compile_definitions(${PROJECTNAME} PRIVATE ARMv7R) + + target_compile_definitions(${PROJECTNAME} PUBLIC CORTEXR) + SET(HARDFP ON) + SET(LITTLEENDIAN ON) + SET(COREID ARMCR5 PARENT_SCOPE) + endif() + ################### # diff --git a/configPlatform.cmake b/configPlatform.cmake index 2897b6ad..66cbbfb6 100644 --- a/configPlatform.cmake +++ b/configPlatform.cmake @@ -148,11 +148,31 @@ function(set_platform_core) if (ARM_CPU MATCHES "^[cC]ortex-[aA]15([^0-9].*)?$") SET(CORE ARMCA15 PARENT_SCOPE) endif() + + ################### + # + # Cortex cortex-r5 + # + if (ARM_CPU MATCHES "^[cC]ortex-[rR]5([^0-9].*)?$") + SET(CORE ARMCR5 PARENT_SCOPE) + endif() + + ################### + # + # Cortex cortex-r8 + # + if (ARM_CPU MATCHES "^[cC]ortex-[rR]8([^0-9].*)?$") + SET(CORE ARMCR8 PARENT_SCOPE) + endif() endfunction() function(core_includes PROJECTNAME) - target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include) + if (CORTEXR) + target_include_directories(${PROJECTNAME} PRIVATE ${CORER}/Include) + else() + target_include_directories(${PROJECTNAME} PRIVATE ${PLATFORMFOLDER}/${CORE}/Include) #target_compile_options(${PROJECTNAME} PRIVATE ${PLATFORMOPT}) + endif() endfunction() function (configplatformForLib PROJECTNAME ROOT) @@ -161,8 +181,10 @@ function (configplatformForLib PROJECTNAME ROOT) endif() if (CORTEXM) compilerSpecificPlatformConfigLibForM(${PROJECTNAME} ${ROOT} ) - else() + elseif(CORTEXA) compilerSpecificPlatformConfigLibForA(${PROJECTNAME} ${ROOT} ) + else() + compilerSpecificPlatformConfigLibForR(${PROJECTNAME} ${ROOT} ) endif() endfunction() @@ -177,8 +199,10 @@ function (configplatformForApp PROJECTNAME ROOT CORE PLATFORMFOLDER) if (CORTEXM) compilerSpecificPlatformConfigAppForM(${PROJECTNAME} ${ROOT} ) - else() + elseif(CORTEXA) compilerSpecificPlatformConfigAppForA(${PROJECTNAME} ${ROOT} ) + else() + compilerSpecificPlatformConfigAppForR(${PROJECTNAME} ${ROOT} ) endif() endfunction()