Added documentation for CMSIS-DSP nodes, cyclo-static scheduling, memory optimizations

Updated copyright years on Compute graph files
pull/94/head
Christophe Favergeon 3 years ago
parent 981917584c
commit e7f9ab01ac

@ -29,7 +29,7 @@ For instance, if you need an alignment on a multiple of `16` bytes with a buffer
If you can't choose freely the values of `NR` and `NW` then you may need to do a copy inside your component to align the buffer (of course only if the overhead due to the lack of alignment is bigger than doing a copy.)
## Memory sharing
## Memory sharing example
When the `memoryOptimization` is enabled, the memory may be reused for different FIFOs to minimize the memory usage. But the scheduling algorithm is not trying to optimize this. So depending on how the graph was scheduled, the level of sharing may be different.

@ -20,9 +20,11 @@
7. ### Extensions
1. #### [Cyclo-static scheduling](CycloStatic.md)
1. #### [Memory optimizations](documentation/Memory.md)
2. #### [Dynamic / Asynchronous mode](Async.md)
2. #### [Cyclo-static scheduling](CycloStatic.md)
3. #### [Dynamic / Asynchronous mode](Async.md)
8. ### [Maths principles](MATHS.md)

@ -3,13 +3,11 @@
* Title: CFFT.h
* Description: Node for CMSIS-DSP cfft
*
* $Date: 30 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: ICFFT.h
* Description: Node for CMSIS-DSP icfft
*
* $Date: 30 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: InterleavedStereoToMono.h
* Description: Interleaved Stereo to mono stream in Q15
*
* $Date: 06 August 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: MFCC.h
* Description: Node for CMSIS-DSP MFCC
*
* $Date: 06 October 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: NullSink.h
* Description: Sink doing nothing for debug
*
* $Date: 08 August 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: OverlapAndAdd.h
* Description: Overlap And Add
*
* $Date: 25 October 2022
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: SlidingBuffer.h
* Description: Sliding buffer
*
* $Date: 25 October 2022
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: ToComplex.h
* Description: Node to convert real to complex
*
* $Date: 30 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: ToReal.h
* Description: Node to convert complex to reals
*
* $Date: 30 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: Unzip.h
* Description: Node to unzip a stream of pair
*
* $Date: 30 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: Zip.h
* Description: Node to zip a pair of stream
*
* $Date: 06 August 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: FileSink.h
* Description: Node for creating File sinks
*
* $Date: 30 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: FileSource.h
* Description: Node for creating File sources
*
* $Date: 30 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: GenericNodes.h
* Description: C++ support templates for the compute graph with static scheduler
*
* $Date: 29 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -1,3 +1,29 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: cg_status.h
* Description: Error code for the Compute Graph
*
*
* Target Processor: Cortex-M and Cortex-A cores
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _CG_STATUS_H_

@ -0,0 +1,79 @@
# Memory optimizations
## Buffers
Sometimes, a FIFO is in fact a buffer. In below graph, the source is writing 5 samples and the sink is reading 5 samples.
![buffer](buffer.png)
The scheduling will obviously be something like:
`Source, Sink, Source, Sink ...`
In this case, the FIFO is used as a simple buffer. The read and the write are always taking place from the start of the buffer.
The schedule generator will detect FIFOs that are used as buffer and the FIFO implementation will be replaced by buffers : the third argument of the template (`isArray`) is set to one:
```C++
FIFO<float32_t,FIFOSIZE0,1,0> fifo0(buf1);
```
## Buffer sharing
When several FIFOs are used as buffers then it may be possible to share the underlying memory for all of those buffers. This optimization is enabled by setting `memoryOptimization` to `true` in the configuration object:
```python
conf.memoryOptimization=True
```
The optimization depends on how the graph has been scheduled.
With the following graph there is a possibility for buffer sharing:
![memory](memory.png)
Without `memoryOptimization`, the FIFO are consuming 60 bytes (4*5 * 3 FIFOs). With `memoryOptimization`, only 40 bytes are needed.
You cannot share memory for the input / output of a node since a node needs both to read and write for its execution. This imposes some constraints on the graph.
The constraints are internally represented by a different graph that represents when buffers are live at the same time : the interference graph. The input / output buffers of a node are live at the same time. Graph coloring is used to identify, from this graph of interferences, when memory for buffers can be shared.
The interference graph is highly depend on how the compute graph is scheduled : a buffer is live when a write has taken place but no read has yet read the full content.
For the above compute graph and its computed schedule, the interference graph would be:
![inter](inter.png)
Adjacent vertices in the graph should use different colors. A coloring of this graph is equivalent to assigning memory areas. Graph coloring of the previous interference graph is giving the following buffer sharing:
![fifos](fifos.png)
The dimension of the buffer is the maximum for all the edges using this buffers.
In the C++ code it is represented as:
```C++
#define BUFFERSIZE0 20
CG_BEFORE_BUFFER
uint8_t buf0[BUFFERSIZE0]={0};
```
`uint8_t` is used (instead of the `float32_t` of this example) because different edges of the graph may use different datatypes.
It is really important that you use the macro `CG_BEFORE_BUFFER` to align this buffer so that the alignment is coherent with the datatype used on all the FIFOs.
### Shared buffer sizing
Let's look at a more complex example to see how the size of the shared buffer is computed:
![shared_complex](shared_complex.png)
The source is generating 10 samples instead of 5. The FIFOs are using 80 bytes without buffer sharing.
With buffer sharing, 60 bytes are used. The buffer sharing is:
![shared_complex_buffer](shared_complex_buffer.png)
Buffer 1 is used by first and last edge in the graph. The dimension of this buffer is 40 bytes : big enough to be usable by edge 0 and edge 3 in the graph.

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@ -1,15 +1,12 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: AppNodes.h
* Description: Application nodes for Example 1
*
* $Date: 29 July 2021
* $Revision: V1.10.0
* Description: Application nodes for Example cyclo
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,10 @@
* Title: AppNodes.h
* Description: Application nodes for Example 1
*
* $Date: 29 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -1,15 +1,12 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: AppNodes.h
* Description: Application nodes for Example 1
*
* $Date: 29 July 2021
* $Revision: V1.10.0
* Description: Application nodes for Example 10
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
* Title: AppNodes.h
* Description: Application nodes for Example 2
*
* $Date: 29 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,10 @@
* Title: AppNodes.h
* Description: Application nodes for Example 3
*
* $Date: 29 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
# Title: appnodes.py
# Description: Application nodes for Example 4
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -1,15 +1,12 @@
###########################################
# Project: CMSIS DSP Library
# Title: appnodes.py
# Description: Application nodes for Example 4
#
# $Date: 29 July 2021
# $Revision: V1.10.0
# Description: Application nodes for Example 5
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,10 @@
* Title: AppNodes.h
* Description: Application nodes for Example 6
*
* $Date: 29 July 2021
* $Revision: V1.10.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -1,15 +1,12 @@
###########################################
# Project: CMSIS DSP Library
# Title: appnodes.py
# Description: Application nodes for Example 4
#
# $Date: 29 July 2021
# $Revision: V1.10.0
# Description: Application nodes for Example 7
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -1,14 +1,11 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: AppNodes.h
* Description: Application nodes for Example 1
*
* $Date: 29 July 2021
* $Revision: V1.10.0
* Description: Application nodes for Example 8
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* --------------------------------------------------------------------
*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0

@ -1,15 +1,13 @@
###########################################
# Project: CMSIS DSP Library
# Title: appnodes.py
# Description: Application nodes for Example 4
# Description: Application nodes for Example 8
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -1,15 +1,12 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: AppNodes.h
* Description: Application nodes for Example 1
*
* $Date: 29 July 2021
* $Revision: V1.10.0
* Description: Application nodes for Example 9
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -1,15 +1,12 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: AppNodes.h
* Description: Application nodes for Example 1
*
* $Date: 29 July 2021
* $Revision: V1.10.0
* Description: Application nodes for Example simple
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -1,15 +1,12 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: AppNodes.h
* Description: Application nodes for Example 1
*
* $Date: 29 July 2021
* $Revision: V1.10.0
* Description: Application nodes for Example simpledsp
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
* --------------------------------------------------------------------
*
* Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

@ -3,13 +3,11 @@
# Title: CFFTF.py
# Description: Node for CMSIS-DSP cfft
#
# $Date: 30 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,12 +3,11 @@
# Title: Duplicate.py
# Description: Duplicate nodes
#
# $Date: 08 September 2022
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: ICFFT.py
# Description: Node for CMSIS-DSP icfft f32
#
# $Date: 30 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: InterleavedStereoToMono.py
# Description: Interleaved Stereo to mono in Q15
#
# $Date: 06 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: MFCC.py
# Description: Node for CMSIS-DSP MFCC
#
# $Date: 30 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: NullSink.py
# Description: Null sink doing nothing for debug
#
# $Date: 06 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: ToComplex.py
# Description: Node to convert real to complex
#
# $Date: 30 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: ToReal.py
# Description: Node to convert complex to real
#
# $Date: 30 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: Unzip.py
# Description: Unzip streams
#
# $Date: 06 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: Zip.py
# Description: Zip two streams
#
# $Date: 06 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: __init__.py
# Description: CG default nodes
#
# $Date: 30 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: FileSink.py
# Description: Node for creating file sinks
#
# $Date: 30 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: FileSource.py
# Description: Node for creating file source
#
# $Date: 30 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: NumpySink.py
# Description: Sink node for displaying a buffer in scipy
#
# $Date: 06 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: WavSink.py
# Description: Sink node for creating a wav
#
# $Date: 06 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: WavSource.py
# Description: Source node for reading wave files
#
# $Date: 06 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -1,5 +1,5 @@
# --------------------------------------------------------------------------
# Copyright (c) 2020-2022 Arm Limited (or its affiliates). All rights reserved.
# Copyright (c) 2021-2023 Arm Limited (or its affiliates). All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: simu.py
# Description: Support Python classes for the Python static scheduler
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: config.py
# Description: Configuration of the code generator
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: description.py
# Description: Schedule generation
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2023 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: graphviz.py
# Description: Graphviz generation for the CG Static scheduler
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: node.py
# Description: Node class for description of dataflow graph
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: pythoncode.py
# Description: Generation of Python code for the static scheduler
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: standard.py
# Description: Standard nodes to describe a network
#
# $Date: 02 August 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

@ -3,13 +3,11 @@
# Title: types.py
# Description: Description of the basic CMSIS-DSP types
#
# $Date: 29 July 2021
# $Revision: V1.10.0
#
# Target Processor: Cortex-M and Cortex-A cores
# -------------------------------------------------------------------- */
#
# Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
# Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

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