diff --git a/Source/FilteringFunctions/arm_correlate_q7.c b/Source/FilteringFunctions/arm_correlate_q7.c index f7c29d58..897e9112 100644 --- a/Source/FilteringFunctions/arm_correlate_q7.c +++ b/Source/FilteringFunctions/arm_correlate_q7.c @@ -56,7 +56,12 @@ @remark Refer to \ref arm_correlate_opt_q7() for a faster implementation of this function. */ -#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_correlate_q7 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) #include "arm_helium_utils.h" #include "arm_vec_filtering.h" diff --git a/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c b/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c index 8d0fbdf9..68480b36 100755 --- a/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c +++ b/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c @@ -45,6 +45,7 @@ @return none */ + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) #include diff --git a/Source/StatisticsFunctions/arm_absmax_q7.c b/Source/StatisticsFunctions/arm_absmax_q7.c index f8ed4519..f2082475 100755 --- a/Source/StatisticsFunctions/arm_absmax_q7.c +++ b/Source/StatisticsFunctions/arm_absmax_q7.c @@ -46,7 +46,12 @@ @return none */ -#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_absmax_q7 built. Helium version has build issues with gcc." +#endif + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) #include #include "arm_helium_utils.h" diff --git a/Source/SupportFunctions/arm_f16_to_q15.c b/Source/SupportFunctions/arm_f16_to_q15.c index bb425d13..4f32ca5f 100755 --- a/Source/SupportFunctions/arm_f16_to_q15.c +++ b/Source/SupportFunctions/arm_f16_to_q15.c @@ -124,8 +124,8 @@ void arm_f16_to_q15( * convert from float to Q31 and then store the results in the destination buffer */ in = *pIn++; - in = (in * 32768.0); - in += in > 0.0 ? 0.5 : -0.5; + in = ((_Float16)in * (_Float16)32768.0f16); + in += (_Float16)in > 0.0f16 ? 0.5f16 : -0.5f16; *pDst++ = clip_q31_to_q15((q31_t) (in)); #else diff --git a/Testing/Source/Tests/StatsTestsF16.cpp b/Testing/Source/Tests/StatsTestsF16.cpp index 012360db..d593daea 100755 --- a/Testing/Source/Tests/StatsTestsF16.cpp +++ b/Testing/Source/Tests/StatsTestsF16.cpp @@ -16,7 +16,7 @@ a double precision computation. #define REL_ERROR_ACCUMULATE (7.0e-3) #define REL_KULLBACK_ERROR (5.0e-3) -#define ABS_KULLBACK_ERROR (5.0e-3) +#define ABS_KULLBACK_ERROR (1.0e-2) void StatsTestsF16::test_max_f16() { @@ -820,7 +820,7 @@ a double precision computation. case StatsTestsF16::TEST_MAX_NO_IDX_F16_27: { - inputA.reload(StatsTestsF16::INPUT1_F16_ID,mgr,8); + inputA.reload(StatsTestsF16::INPUT1_F16_ID,mgr,16); ref.reload(StatsTestsF16::MAXVALS_F16_ID,mgr); @@ -832,7 +832,7 @@ a double precision computation. case StatsTestsF16::TEST_MAX_NO_IDX_F16_28: { - inputA.reload(StatsTestsF16::INPUT1_F16_ID,mgr,11); + inputA.reload(StatsTestsF16::INPUT1_F16_ID,mgr,23); ref.reload(StatsTestsF16::MAXVALS_F16_ID,mgr); diff --git a/Testing/Source/Tests/UnaryTestsF32.cpp b/Testing/Source/Tests/UnaryTestsF32.cpp index 1d901cf9..5938dd3f 100755 --- a/Testing/Source/Tests/UnaryTestsF32.cpp +++ b/Testing/Source/Tests/UnaryTestsF32.cpp @@ -42,7 +42,7 @@ But big matrix needed for checking the vectorized code */ #define SNR_THRESHOLD_INV 99 #define REL_ERROR_INV (3.0e-5) -#define ABS_ERROR_INV (1.0e-5) +#define ABS_ERROR_INV (2.0e-5) /* diff --git a/Testing/cmsis_build/RTE/_test.Release_VHT_M55/RTE_Components.h b/Testing/cmsis_build/RTE/_test.Release_VHT_M55/RTE_Components.h new file mode 100644 index 00000000..f02c8945 --- /dev/null +++ b/Testing/cmsis_build/RTE/_test.Release_VHT_M55/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'test.Release+VHT_M55' + * Target: 'test.Release+VHT_M55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM55.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Testing/cmsis_build/configs/ARM_VHT_Corstone_310_config.txt b/Testing/cmsis_build/configs/ARM_VHT_Corstone_310_config.txt index 6a260049..a9d40ead 100644 --- a/Testing/cmsis_build/configs/ARM_VHT_Corstone_310_config.txt +++ b/Testing/cmsis_build/configs/ARM_VHT_Corstone_310_config.txt @@ -8,25 +8,24 @@ mps3_board.visualisation.disable-visualisation=1 cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] -cpu0.INITSVTOR=0x70000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.INITNSVTOR=0x70000000 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] -cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +#cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] +#cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls +#cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] +#cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] +#cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] +#cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] +#cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. +#cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +#cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +#cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +#cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +#cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +#idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +#cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +#cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +#cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +#cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +#cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included mps3_board.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +mps3_board.sse300.iotss3_systemcontrol.INITSVTOR_RST=0x70000000 #---------------------------------------------------------------------------------------------- diff --git a/Testing/cmsis_build/quicktest.bat b/Testing/cmsis_build/quicktest.bat index 0a62a120..1c114786 100644 --- a/Testing/cmsis_build/quicktest.bat +++ b/Testing/cmsis_build/quicktest.bat @@ -1,24 +1,45 @@ ECHO OFF ECHO "Gen Test" cd .. -python processTests.py -f Output.pickle -e StatsTests +python processTests.py -f Output.pickle -e UnaryTestsF32 cd cmsis_build -ECHO "Build" -cbuild "test.Release+VHT-Corstone-300.cprj" -ECHO "Run" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe -f configs/ARM_VHT_Corstone_300_config.txt -a cpu0="out\test\VHT-Corstone-300\Release\test.Release+VHT-Corstone-300.axf" > results_cs300_u55.txt -python ..\processResult.py -f ..\Output.pickle -e -r results_cs300_u55.txt +REM ECHO "Build" +REM cbuild "test.Release+VHT-Corstone-300.cprj" +REM ECHO "Run" +REM C:\Keil_v5\ARM\VHT_11.18.29\VHT_Corstone_SSE-300_Ethos-U55.exe -f configs/ARM_VHT_Corstone_300_config.txt -a cpu0="out\test\VHT-Corstone-300\Release\test.Release+VHT-Corstone-300.axf" > results_cs300_u55.txt +REM set MyError=%errorlevel% +REM python ..\processResult.py -f ..\Output.pickle -e -r results_cs300_u55.txt +REM if %MyError% neq 0 goto :error +REM goto :EOF REM ECHO "Build" REM cbuild "test.Release+VHT_M7_UNROLLED.cprj" REM ECHO "Run" -REM C:\Keil_v5\ARM\VHT\VHT_MPS2_Cortex-M7.exe -f configs/ARM_VHT_MPS2_M7DP_config.txt out\test\VHT_M7_UNROLLED\Release\test.Release+VHT_M7_UNROLLED.axf > results_m7_unrolled.txt +REM C:\Keil_v5\ARM\VHT_11.18.29\VHT_MPS2_Cortex-M7.exe -f configs/ARM_VHT_MPS2_M7DP_config.txt out\test\VHT_M7_UNROLLED\Release\test.Release+VHT_M7_UNROLLED.axf > results_m7_unrolled.txt +REM set MyError=%errorlevel% REM python ..\processResult.py -f ..\Output.pickle -e -r results_m7_unrolled.txt +REM if %MyError% neq 0 goto :error +REM goto :EOF + +ECHO "Build" +cbuild "test.Release+VHT_M0P.cprj" +ECHO "Run" +C:\Keil_v5\ARM\VHT_11.18.29\VHT_MPS2_Cortex-M0plus.exe -f configs/ARM_VHT_MPS2_M0plus_config.txt out\test\VHT_M0P\Release\test.Release+VHT_M0P.axf > results_m0p.txt +set MyError=%errorlevel% +python ..\processResult.py -f ..\Output.pickle -e -r results_m0p.txt +if %MyError% neq 0 goto :error +goto :EOF REM ECHO "Build" -REM cbuild "test.Release+FVP_M55.cprj" +REM cbuild "test.Release+VHT_M55.cprj" REM ECHO "Run" -REM C:\Keil_v5\ARM\VHT\VHT_MPS2_Cortex-M55.exe -f configs/REM ARM_VHT_MPS2_M55_config.txt -a cpu0="REM out\test\FVP_M55\Release\test.Release+FVP_M55.elf" REM > results_m55.txt -REM python ..\processResult.py -f ..\Output.pickle -e -r REM results_m55.txt -REM \ No newline at end of file +REM C:\Keil_v5\ARM\VHT_11.18.29\VHT_MPS2_Cortex-M55.exe -f configs/ARM_VHT_MPS2_M55_config.txt -a cpu0="out\test\VHT_M55\Release\test.Release+VHT_M55.elf" > results_m55.txt +REM set MyError=%errorlevel% +REM python ..\processResult.py -f ..\Output.pickle -e -r results_m55.txt +REM if %MyError% neq 0 goto :error +REM goto :EOF + +:error +echo Failed running all tests with error %MyError%. +exit /b %errorlevel% diff --git a/Testing/cmsis_build/runall.py b/Testing/cmsis_build/runall.py new file mode 100644 index 00000000..dd36de66 --- /dev/null +++ b/Testing/cmsis_build/runall.py @@ -0,0 +1,266 @@ +import argparse +import pickle +import sys +import subprocess +import os +import colorama +from colorama import init,Fore, Back, Style + +parser = argparse.ArgumentParser(description='Parse test description') +parser.add_argument('-avh', nargs='?',type = str, default="C:/Keil_v5/ARM/VHT_11.18.29", help="AVH folder") +args = parser.parse_args() + + +init() + +sys.path.append("..") + +from TestScripts.Parser import TreeElem + +ERROR_OCCURED = False + +def printTitle(s): + print("\n" + Fore.GREEN + Style.BRIGHT + s + Style.RESET_ALL) + +def printSubTitle(s): + print("\n" + Fore.YELLOW + Style.BRIGHT + s + Style.RESET_ALL) + +def printError(s): + print("\n" + Fore.RED + Style.BRIGHT + s + Style.RESET_ALL) + +# Load Output.pickle files for the test description +def loadRoot(f): + root = None + with open(f,"rb") as inf: + root=pickle.load(inf) + return(root) + +# Get test suites from the test descriptions +def getSuites(node,filterList,currentList=[]): + if node.kind==TreeElem.SUITE: + currentList.append(node.data["class"]) + if node.kind==TreeElem.GROUP: + if not node.data["class"] in filterList: + for c in node.children: + getSuites(c,filterList,currentList) + +class Result: + def __init__(self,msg,error=False): + self._error = error + self._msg = msg + + @property + def error(self): + return self._error + + @property + def msg(self): + return self._msg + + + +# Run a command and get error or result +# For the test report we don't need the stderr +# in case of error since the test report is giving +# all the details. So, there is an option to +# disable the dump of stderr +def run(*args,mustPrint=False,dumpStdErr=True): + global ERROR_OCCURED + try: + result=subprocess.run(args,text=True,capture_output=True,timeout=600) + if result.returncode !=0 : + ERROR_OCCURED = True + if dumpStdErr: + return(Result(result.stderr + "\n\nSTDOUT:\n\n" + result.stdout,error=True)) + else: + return(Result(result.stdout,error=True)) + + if mustPrint: + print(result.stdout) + return(Result(result.stdout)) + except Exception as e: + ERROR_OCCURED = True + return(Result(str(e),error=True)) + + + + + +# Configuration file for AVH core +configFiles={ + "CS310":"ARM_VHT_Corstone_310_config.txt", + "CS300":"ARM_VHT_Corstone_300_config.txt", + "M55":"ARM_VHT_MPS2_M55_config.txt", + "M33_DSP_FP":"ARM_VHT_MPS2_M33_DSP_FP_config.txt", + "M7DP":"ARM_VHT_MPS2_M7DP_config.txt", + "M4FP":"ARM_VHT_MPS2_M4FP_config.txt", + "M3":"ARM_VHT_MPS2_M3_config.txt", + "M23":"ARM_VHT_MPS2_M23_config.txt", + "M0plus":"ARM_VHT_MPS2_M0plus_config.txt", +} + +# Windows executable +# (At some point this script will also support +# unix) +avhExe={ + "CS310":"VHT_Corstone_SSE-310.exe", + "CS300":"VHT_Corstone_SSE-300_Ethos-U55.exe", + "M55":"VHT_MPS2_Cortex-M55.exe", + "M33_DSP_FP":"VHT_MPS2_Cortex-M33.exe", + "M7DP":"VHT_MPS2_Cortex-M7.exe", + "M4FP":"VHT_MPS2_Cortex-M4.exe", + "M3":"VHT_MPS2_Cortex-M3.exe", + "M23":"VHT_MPS2_Cortex-M23.exe", + "M0plus":"VHT_MPS2_Cortex-M0plus.exe", +} + +AVHROOT = args.avh + +# Run AVH +def runAVH(build,core): + axf="out/test/%s/Release/test.Release+%s.axf" % (build,build) + elf="out/test/%s/Release/test.Release+%s.elf" % (build,build) + app = axf + if os.path.exists(axf): + app = axf + if os.path.exists(elf): + app = elf + config = os.path.join("configs",configFiles[core]) + avh = os.path.join(AVHROOT,avhExe[core]) + res=run(avh,"-f",config,app) + return(res) + +#################### + +# Test descriptions to use +tests=["../Output.pickle","../Output_f16.pickle"] +# Test group to avoid +filterList=["NNTests","ExampleTests"] +allSuites=[] + +# Load all the test suite to run +for t in tests: + root=loadRoot(t) + suites=[] + getSuites(root,filterList,suites) + allSuites += [(x,t) for x in suites ] + +# Test suite and output pickle needed to decode the result +#print(allSuites) + +#allSuites=[("BasicTestsF32","../Output.pickle"), +#("BasicTestsQ31","../Output.pickle")] + +#allSuites=[("StatsTestsQ7","../Output.pickle")] + +# Solution and build file for all +# the tests +# It is a pair : csolution target type and AVH identification +# AVH identification is used to find the executable +# and the configuration file +solutions={ + 'testac6.csolution.yml':[ + ("VHT-Corstone-310","CS310"), + ("VHT-Corstone-300","CS300"), + #("VHT_M33","M33_DSP_FP"), + ("VHT_M7","M7DP"), + ("VHT_M7_UNROLLED","M7DP"), + #("VHT_M4","M4FP"), + #("VHT_M3","M3"), + #("VHT_M23","M23"), + ("VHT_M0P","M0plus") + ], + 'testgcc.csolution.yml':[ + ("VHT_M55","M55"), + #("VHT_M33","M33_DSP_FP"), + ("VHT_M7","M7DP"), + ("VHT_M7_UNROLLED","M7DP"), + #("VHT_M4","M4FP"), + #("VHT_M3","M3"), + #("VHT_M23","M23"), + ("VHT_M0P","M0plus") + ] +} + +HTMLHEADER=""" +
+CMSIS-DSP Test summary +
+ +""" + +HTMLFOOTER=""" + +""" + +# Run the tests and log the result +# in a summary.html file +with open("summary.html","w") as f: + print(HTMLHEADER,file=f) + for s in solutions: + printTitle("Process solution %s" % s) + run("csolution","convert","-s",s) + print("

Solution %s

" % s,file=f) + maxNbBuilds=len(solutions[s]) + buildNb=0 + for build,core in solutions[s]: + buildNb = buildNb + 1 + print("

Core %s

" % build,file=f) + printTitle("Process core %s (%d/%d)" % (build,buildNb,maxNbBuilds)) + buildFile="test.Release+%s.cprj" % build + nb = 0 + maxNb = len(allSuites) + for s,pickle in allSuites: + nb = nb + 1 + printSubTitle("Process suite %s (%d/%d)" % (s,nb,maxNb)) + res=run(sys.executable,"../processTests.py","-gen","..","-p","../Patterns","-d","../Parameters","-f",pickle,"-e",s,mustPrint=True) + if res.error: + printError("Error processTests") + print("

Error generating %s

" % s,file=f)
+                    print(res.msg,file=f)
+                    print("
",file=f) + continue + if nb==1: + # -r is needed for first + # build when we switch + # between different solutions + # (Like one using AC6 and the other + # using gcc) + res=run("cbuild","-r",buildFile) + else: + res=run("cbuild",buildFile) + if res.error: + printError("Error cbuild") + print("

Error building %s

" % s,file=f)
+                    print(res.msg,file=f)
+                    print("
",file=f) + continue + printSubTitle("Run AVH") + res=runAVH(build,core) + if res.error: + printError("Error running AVH") + print("

Error running %s

" % s,file=f)
+                    print(res.msg,file=f)
+                    print("
",file=f) + continue + else: + with open("results.txt","w") as o: + print(res.msg,file=o) + res=run(sys.executable,"../processResult.py","-f",pickle,"-e","-ahtml","-r","results.txt",dumpStdErr=False) + if res.error: + printError("Error processResult") + print("

Error processing %s result

" % s,file=f)
+                    print(res.msg,file=f)
+                    print("
",file=f) + continue + else: + pass + # When no error the section is not + # included in final file + #print(res.msg,file=f) + print(HTMLFOOTER,file=f) + +if ERROR_OCCURED: + sys.exit("Error occurred") +else: + sys.exit(0) \ No newline at end of file diff --git a/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj b/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj index a9277dba..d06c123f 100644 --- a/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj +++ b/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXA ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -31,8 +31,8 @@ - - + + diff --git a/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj b/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj index 484fe875..2ce051c0 100644 --- a/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj +++ b/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXA ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -31,8 +31,8 @@ - - + + diff --git a/Testing/cmsis_build/test.Release+FVP_A9Neon.cprj b/Testing/cmsis_build/test.Release+FVP_A9Neon.cprj index ec0aa84b..49aa4d74 100644 --- a/Testing/cmsis_build/test.Release+FVP_A9Neon.cprj +++ b/Testing/cmsis_build/test.Release+FVP_A9Neon.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXA ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -31,8 +31,8 @@ - - + + diff --git a/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj b/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj index e9381ec6..55a828ba 100644 --- a/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj +++ b/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj @@ -1,6 +1,6 @@ - + Automatically generated project diff --git a/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj b/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj index 28683bbc..064ebe12 100644 --- a/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj +++ b/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj @@ -1,6 +1,6 @@ - + Automatically generated project diff --git a/Testing/cmsis_build/test.Release+VHT_M0P.cprj b/Testing/cmsis_build/test.Release+VHT_M0P.cprj index 72cd0129..5eb829e5 100644 --- a/Testing/cmsis_build/test.Release+VHT_M0P.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M0P.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXM ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -27,7 +27,7 @@ - + diff --git a/Testing/cmsis_build/test.Release+VHT_M23.cprj b/Testing/cmsis_build/test.Release+VHT_M23.cprj index 8d753928..20ad1e70 100644 --- a/Testing/cmsis_build/test.Release+VHT_M23.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M23.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXM ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -27,7 +27,7 @@ - + diff --git a/Testing/cmsis_build/test.Release+VHT_M3.cprj b/Testing/cmsis_build/test.Release+VHT_M3.cprj index c420c5fb..d054ed97 100644 --- a/Testing/cmsis_build/test.Release+VHT_M3.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M3.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXM ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -27,7 +27,7 @@ - + diff --git a/Testing/cmsis_build/test.Release+VHT_M33.cprj b/Testing/cmsis_build/test.Release+VHT_M33.cprj index 1f3e1fae..668caa96 100644 --- a/Testing/cmsis_build/test.Release+VHT_M33.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M33.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXM ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -27,7 +27,7 @@ - + diff --git a/Testing/cmsis_build/test.Release+VHT_M4.cprj b/Testing/cmsis_build/test.Release+VHT_M4.cprj index f16020aa..73981678 100644 --- a/Testing/cmsis_build/test.Release+VHT_M4.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M4.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXM ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -27,7 +27,7 @@ - + diff --git a/Testing/cmsis_build/test.Release+FVP_M55.cprj b/Testing/cmsis_build/test.Release+VHT_M55.cprj similarity index 93% rename from Testing/cmsis_build/test.Release+FVP_M55.cprj rename to Testing/cmsis_build/test.Release+VHT_M55.cprj index 8c73223a..c450081f 100644 --- a/Testing/cmsis_build/test.Release+FVP_M55.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M55.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - - + + + + + EMBEDDED;NORMALFVP;CORTEXM ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -27,7 +27,7 @@ - + diff --git a/Testing/cmsis_build/test.Release+VHT_M7.cprj b/Testing/cmsis_build/test.Release+VHT_M7.cprj index 67f400e8..0f6509ee 100644 --- a/Testing/cmsis_build/test.Release+VHT_M7.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M7.cprj @@ -1,6 +1,6 @@ - + Automatically generated project @@ -11,15 +11,15 @@ - + - - - - + + + + EMBEDDED;NORMALFVP;CORTEXM ../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests @@ -27,7 +27,7 @@ - + diff --git a/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj b/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj index 01d45c6e..aad06424 100644 --- a/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj +++ b/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj @@ -1,6 +1,6 @@ - + Automatically generated project diff --git a/Testing/cmsis_build/testac6.csolution.yml b/Testing/cmsis_build/testac6.csolution.yml index c533feb7..3a185f4b 100644 --- a/Testing/cmsis_build/testac6.csolution.yml +++ b/Testing/cmsis_build/testac6.csolution.yml @@ -53,7 +53,7 @@ solution: defines: - CORTEXM - - type: FVP_M55 + - type: VHT_M55 device: ARMCM55 defines: - CORTEXM @@ -94,32 +94,6 @@ solution: defines: - CORTEXM -# ARMCA5, ARMCA7 and ARMCA9 are not configured -# with Neon in the pack. -# And the standard .cmake in CMSIS Build tools -# is not supporting Cortex-A yet. -# Since the goal is to run the Neon code of CMSIS-DSP, -# we have added Cortex-A support to the .cmake -# and forced Neon support without taking into account -# the FPU variable from the pack. -# If you want to build those targets, you'll have to add -# Cortex-A support to the .cmake of CMSIS Build tools -# in the same way (forcing Neon) - - type: FVP_A5Neon - device: ARMCA5 - defines: - - CORTEXA - - - type: FVP_A7Neon - device: ARMCA7 - defines: - - CORTEXA - - - type: FVP_A9Neon - device: ARMCA9 - defines: - - CORTEXA - build-types: - type: Release optimize: max diff --git a/Testing/cmsis_build/testgcc.csolution.yml b/Testing/cmsis_build/testgcc.csolution.yml index 85dd7cd8..a7e767b9 100644 --- a/Testing/cmsis_build/testgcc.csolution.yml +++ b/Testing/cmsis_build/testgcc.csolution.yml @@ -2,9 +2,22 @@ solution: compiler: GCC misc: - C: - - -ffunction-sections -mfp16-format=ieee -fdata-sections -std=c11 -Ofast -ffast-math -flax-vector-conversions + - -ffunction-sections + - -mfp16-format=ieee + - -fdata-sections + - -std=c11 + - -Ofast + - -ffast-math + - -flax-vector-conversions - CPP: - - -ffunction-sections -mfp16-format=ieee -fdata-sections -std=c++11 -Ofast -ffast-math -flax-vector-conversions -Wno-unused-parameter + - -ffunction-sections + - -mfp16-format=ieee + - -fdata-sections + - -std=c++11 + - -Ofast + - -ffast-math + - -flax-vector-conversions + - -Wno-unused-parameter - ASM: - -masm=auto - Link: @@ -35,7 +48,7 @@ solution: #- type: VHT-Corstone-310 # device: ARM::SSE-310-MPS3 - - type: FVP_M55 + - type: VHT_M55 device: ARMCM55 defines: - CORTEXM @@ -70,38 +83,6 @@ solution: defines: - CORTEXM -# ARMCA5, ARMCA7 and ARMCA9 are not configured -# with Neon in the pack. -# And the standard .cmake in CMSIS Build tools -# is not supporting Cortex-A yet. -# Since the goal is to run the Neon code of CMSIS-DSP, -# we have added Cortex-A support to the .cmake -# and forced Neon support without taking into account -# the FPU variable from the pack. -# If you want to build those targets, you'll have to add -# Cortex-A support to the .cmake of CMSIS Build tools -# in the same way (forcing Neon) -# -# Also, the packs have an issue with the scatter file for gcc -# with is categorized as "Other" instead of "linkerScript" -# in CMSIS 5.9.0 -# You'll need a more recent version where the problem -# is solved - - type: FVP_A5Neon - device: ARMCA5 - defines: - - CORTEXA - - - type: FVP_A7Neon - device: ARMCA7 - defines: - - CORTEXA - - - type: FVP_A9Neon - device: ARMCA9 - defines: - - CORTEXA - build-types: - type: Release optimize: max diff --git a/Testing/processResult.py b/Testing/processResult.py index 8e8ef0bd..baecc088 100644 --- a/Testing/processResult.py +++ b/Testing/processResult.py @@ -121,12 +121,14 @@ class TextFormatter: # Return test result as a text tree class HTMLFormatter: - def __init__(self): + def __init__(self,append=False): self.nb=1 self.suite=False + self.append = append def start(self): - print("Test Results") + if not self.append: + print("Test Results") def printGroup(self,elem,theId): if elem is None: @@ -138,9 +140,13 @@ class HTMLFormatter: if elem.kind == TestScripts.Parser.TreeElem.GROUP: kind = "Group" if kind == "Group": - print(" %s (%d) " % (self.nb,message,theId,self.nb)) + if not self.append: + print(" %s (%d) " % (self.nb,message,theId,self.nb)) else: - print(" %s (%d) " % (self.nb,message,theId,self.nb)) + if not self.append: + print(" %s (%d) " % (self.nb,message,theId,self.nb)) + else: + print(" %s (%d) " % (3,message,theId,self.nb)) self.suite=True print("") print("") @@ -160,19 +166,23 @@ class HTMLFormatter: p="FAILED" if passed == 1: p= "PASSED" - print("") - print("" % (message,)) - print("" % theId) - print("" % p) - if params: - print("\n" % (params)) - else: - print("\n") - if (cycles > 0): - print("" % cycles) - else: - print("") - print("") + # Green status is not displayed when + # generating the full summary in append mode + # In summary mode, only errors are displayed + if passed != 1 or not self.append: + print("") + print("" % (message,)) + print("" % theId) + print("" % p) + if params: + print("\n" % (params)) + else: + print("\n") + if (cycles > 0): + print("" % cycles) + else: + print("") + print("") if passed != 1: @@ -187,7 +197,8 @@ class HTMLFormatter: self.suite=False def end(self): - print("") + if not self.append: + print("") # Return test result as a CSV class CSVFormatter: @@ -539,6 +550,8 @@ def analyze(root,results,args,trace): analyseResult(resultPath,root,results,args.e,args.b,trace,CSVFormatter()) elif args.html: analyseResult(resultPath,root,results,args.e,args.b,trace,HTMLFormatter()) + elif args.ahtml: + analyseResult(resultPath,root,results,args.e,args.b,trace,HTMLFormatter(append=True)) elif args.m: analyseResult(resultPath,root,results,args.e,args.b,trace,MathematicaFormatter()) else: @@ -556,6 +569,8 @@ parser.add_argument('-f', nargs='?',type = str, default="Output.pickle", help="T parser.add_argument('-r', nargs='?',type = str, default=None, help="Result file path") parser.add_argument('-c', action='store_true', help="CSV output") parser.add_argument('-html', action='store_true', help="HTML output") +parser.add_argument('-ahtml', action='store_true', help="Partial HTML output") + parser.add_argument('-e', action='store_true', help="Embedded test") # -o needed when -e is true to know where to extract the output files parser.add_argument('-o', nargs='?',type = str, default="Output", help="Output dir path") 
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