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85 lines
3.9 KiB
C
85 lines
3.9 KiB
C
/*
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* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __RTE_DEVICE_H
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#define __RTE_DEVICE_H
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// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
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// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
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#define RTE_USART0 1
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// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
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// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
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#define RTE_USART1 1
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// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
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// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
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#define RTE_ISRAM0_MPC 0
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// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
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// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
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#define RTE_ISRAM1_MPC 0
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// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
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// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
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#define RTE_SRAM_MPC 0
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// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
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// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
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#define RTE_QSPI_MPC 0
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// <q> PPC (Peripheral Protection Controller) [PPC_CORSTONE310_MAIN0]
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// <i> Configuration settings for Driver_PPC_CORSTONE310_MAIN0 in component ::Drivers:PPC
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#define RTE_PPC_CORSTONE310_MAIN0 0
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// <q> PPC (Peripheral Protection Controller) [PPC_CORSTONE310_MAIN_EXP0]
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// <i> Configuration settings for Driver_PPC_CORSTONE310_MAIN_EXP0 in component ::Drivers:PPC
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#define RTE_PPC_CORSTONE310_MAIN_EXP0 0
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// <q> PPC (Peripheral Protection Controller) [PPC_CORSTONE310_MAIN_EXP1]
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// <i> Configuration settings for Driver_PPC_CORSTONE310_MAIN_EXP1 in component ::Drivers:PPC
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#define RTE_PPC_CORSTONE310_MAIN_EXP1 0
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// <q> PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH0]
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// <i> Configuration settings for Driver_PPC_CORSTONE310_PERIPH0 in component ::Drivers:PPC
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#define RTE_PPC_CORSTONE310_PERIPH0 0
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// <q> PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH1]
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// <i> Configuration settings for Driver_PPC_CORSTONE310_PERIPH1 in component ::Drivers:PPC
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#define RTE_PPC_CORSTONE310_PERIPH1 0
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// <q> PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH_EXP0]
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// <i> Configuration settings for Driver_PPC_CORSTONE310_PERIPH_EXP0 in component ::Drivers:PPC
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#define RTE_PPC_CORSTONE310_PERIPH_EXP0 0
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// <q> PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH_EXP1]
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// <i> Configuration settings for Driver_PPC_CORSTONE310_PERIPH_EXP1 in component ::Drivers:PPC
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#define RTE_PPC_CORSTONE310_PERIPH_EXP1 0
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// <q> PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH_EXP2]
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// <i> Configuration settings for Driver_PPC_CORSTONE310_PERIPH_EXP2 in component ::Drivers:PPC
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#define RTE_PPC_CORSTONE310_PERIPH_EXP2 0
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// <q> Flash device emulated by SRAM [Driver_Flash0]
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// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
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#define RTE_FLASH0 1
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// <q> I2C SBCon [Driver_I2C0]
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// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
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#define RTE_I2C0 1
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#endif /* __RTE_DEVICE_H */
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