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154 lines
5.0 KiB
C
154 lines
5.0 KiB
C
/*
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* Copyright (c) 2020-2022 Arm Limited. All rights reserved.
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*
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* Licensed under the Apache License Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing software
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* distributed under the License is distributed on an "AS IS" BASIS
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __DEVICE_CFG_H__
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#define __DEVICE_CFG_H__
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/**
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* \file device_cfg.h
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* \brief Configuration file native driver re-targeting
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*
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* \details This file can be used to add native driver specific macro
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* definitions to select which peripherals are available in the build.
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*
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* This is a default device configuration file with all peripherals enabled.
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*/
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/* Secure only peripheral configuration */
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/* ARM MPS3 IO SCC */
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#define MPS3_IO_S
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#define MPS3_IO_DEV MPS3_IO_DEV_S
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/* I2C_SBCon */
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#define I2C0_SBCON_S
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#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S
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/* I2S */
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#define MPS3_I2S_S
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#define MPS3_I2S_DEV MPS3_I2S_DEV_S
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/* ARM UART Controller PL011 */
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#define UART0_CMSDK_S
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#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S
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#define UART1_CMSDK_S
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#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S
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#define DEFAULT_UART_BAUDRATE 115200U
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/* To be used as CODE and DATA sram */
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#define MPC_ISRAM0_S
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#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S
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#define MPC_ISRAM1_S
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#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S
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#define MPC_SRAM_S
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#define MPC_SRAM_DEV MPC_SRAM_DEV_S
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#define MPC_QSPI_S
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#define MPC_QSPI_DEV MPC_QSPI_DEV_S
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/** System Counter Armv8-M */
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#define SYSCOUNTER_CNTRL_ARMV8_M_S
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#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
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#define SYSCOUNTER_READ_ARMV8_M_S
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#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S
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/**
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* Arbitrary scaling values for test purposes
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*/
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#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u
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#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u
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#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u
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#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u
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/* System timer */
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#define SYSTIMER0_ARMV8_M_S
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#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S
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#define SYSTIMER1_ARMV8_M_S
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#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S
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#define SYSTIMER2_ARMV8_M_S
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#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S
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#define SYSTIMER3_ARMV8_M_S
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#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S
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#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul)
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#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul)
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#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul)
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#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul)
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/* CMSDK GPIO driver structures */
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#define GPIO0_CMSDK_S
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#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
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#define GPIO1_CMSDK_S
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#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
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#define GPIO2_CMSDK_S
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#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
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#define GPIO3_CMSDK_S
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#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
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/* System Watchdogs */
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#define SYSWDOG_ARMV8_M_S
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#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
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/* ARM MPC SIE 310 driver structures */
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#define MPC_VM0_S
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#define MPC_VM0_DEV MPC_VM0_DEV_S
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#define MPC_VM1_S
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#define MPC_VM1_DEV MPC_VM1_DEV_S
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#define MPC_SSRAM2_S
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#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
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#define MPC_SSRAM3_S
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#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
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/* ARM PPC driver structures */
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#define PPC_CORSTONE310_MAIN0_S
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#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S
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#define PPC_CORSTONE310_MAIN_EXP0_S
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#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S
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#define PPC_CORSTONE310_MAIN_EXP1_S
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#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S
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#define PPC_CORSTONE310_MAIN_EXP2_S
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#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S
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#define PPC_CORSTONE310_MAIN_EXP3_S
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#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S
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#define PPC_CORSTONE310_PERIPH0_S
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#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S
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#define PPC_CORSTONE310_PERIPH1_S
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#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S
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#define PPC_CORSTONE310_PERIPH_EXP0_S
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#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S
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#define PPC_CORSTONE310_PERIPH_EXP1_S
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#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S
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#define PPC_CORSTONE310_PERIPH_EXP2_S
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#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S
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#define PPC_CORSTONE310_PERIPH_EXP3_S
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#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S
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/* DMA350 */
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#define DMA350_DMA0_S
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#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S
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/* ARM SPI PL022 */
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/* Invalid device stubs are not defined */
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#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */
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#define SPI1_PL022_S
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#define SPI1_PL022_DEV SPI1_PL022_DEV_S
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#endif /* __DEVICE_CFG_H__ */
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