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370 lines
15 KiB
ArmAsm
370 lines
15 KiB
ArmAsm
/******************************************************************************
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* @file startup_ARMCR8.c
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* @brief Unvalidated Startup File for a Cortex-R8 Device
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******************************************************************************/
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/*
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* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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// Region size <256 bytes is unpredictable
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#define Region_256B 0b00111
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#define Region_512B 0b01000
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#define Region_1K 0b01001
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#define Region_2K 0b01010
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#define Region_4K 0b01011
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#define Region_8K 0b01100
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#define Region_16K 0b01101
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#define Region_32K 0b01110
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#define Region_64K 0b01111
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#define Region_128K 0b10000
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#define Region_256K 0b10001
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#define Region_512K 0b10010
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#define Region_1M 0b10011
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#define Region_2M 0b10100
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#define Region_4M 0b10101
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#define Region_8M 0b10110
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#define Region_16M 0b10111
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#define Region_32M 0b11000
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#define Region_64M 0b11001
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#define Region_128M 0b11010
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#define Region_256M 0b11011
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#define Region_512M 0b11100
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#define Region_1G 0b11101
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#define Region_2G 0b11110
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#define Region_4G 0b11111
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#define Region_Enable 0b1
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#define Execute_Never 0x1000 // Bit 12
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#define Normal_nShared 0x03 // Outer and Inner write-back, no write-allocate
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#define Device_nShared 0x10
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#define Full_Access 0b011
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#define Read_Only 0b110
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//----------------------------------------------------------------
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.eabi_attribute Tag_ABI_align8_preserved,1
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.section VECTORS,"ax"
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.align 3
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.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame
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//----------------------------------------------------------------
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// Entry point for the Reset handler
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//----------------------------------------------------------------
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.global Start
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Start:
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//----------------------------------------------------------------
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// Exception Vector Table
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//----------------------------------------------------------------
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// Note: LDR PC instructions are used here, though branch (B) instructions
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// could also be used, unless the exception handlers are >32MB away.
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Vectors:
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LDR PC, Reset_Addr
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LDR PC, Undefined_Addr
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LDR PC, SVC_Addr
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LDR PC, Prefetch_Addr
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LDR PC, Abort_Addr
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B . // Reserved vector
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LDR PC, IRQ_Addr
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LDR PC, FIQ_Addr
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.balign 4
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Reset_Addr: .word Reset_Handler
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Undefined_Addr: .word Undefined_Handler
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SVC_Addr: .word SVC_Handler
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Prefetch_Addr: .word Prefetch_Handler
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Abort_Addr: .word Abort_Handler
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IRQ_Addr: .word IRQ_Handler
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FIQ_Addr: .word FIQ_Handler
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//----------------------------------------------------------------
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// Exception Handlers
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//----------------------------------------------------------------
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Undefined_Handler:
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B Undefined_Handler
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SVC_Handler:
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B SVC_Handler
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Prefetch_Handler:
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B Prefetch_Handler
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Abort_Handler:
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B Abort_Handler
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IRQ_Handler:
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B IRQ_Handler
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FIQ_Handler:
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B FIQ_Handler
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//----------------------------------------------------------------
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// Reset Handler
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//----------------------------------------------------------------
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.global Reset_Handler
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.type Reset_Handler, "function"
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Reset_Handler:
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//----------------------------------------------------------------
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// Disable MPU and caches
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//----------------------------------------------------------------
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// Disable MPU and cache in case it was left enabled from an earlier run
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// This does not need to be done from a cold reset
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MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
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BIC r0, r0, #0x05 // Disable MPU (M bit) and data cache (C bit)
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BIC r0, r0, #0x800 // Disable branch prediction (Z bit)
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BIC r0, r0, #0x1000 // Disable instruction cache (I bit)
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DSB // Ensure all previous loads/stores have completed
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MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
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ISB // Ensure subsequent insts execute wrt new MPU settings
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//----------------------------------------------------------------
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// Initialize Supervisor Mode Stack using Linker symbol from scatter file.
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// Stacks must be 8 byte aligned.
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//----------------------------------------------------------------
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.global Image$$ARM_LIB_STACKHEAP$$ZI$$Limit
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LDR SP, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit
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//----------------------------------------------------------------
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// Cache invalidation
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//----------------------------------------------------------------
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DSB
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MOV r0, #0
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MCR p15, 0, r0, c7, c5, 0 // invalidate I cache
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MCR p15, 0, r0, c15, c5, 0 // invalidate D cache
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//----------------------------------------------------------------
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// TCM Configuration
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//----------------------------------------------------------------
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// Cortex-R8 optionally provides two Tightly-Coupled Memory (TCM) blocks (ITCM and DTCM)
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// for fast access to code or data.
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// ITCM typically holds interrupt or exception code that must be accessed at high speed,
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// without any potential delay resulting from a cache miss.
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// DTCM typically holds a block of data for intensive processing, such as audio or video data.
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// The following illustrates basic TCM configuration, as the basis for exploration by the user
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.global Image$$CODE$$Base
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.global Image$$DATA$$Base
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MRC p15, 0, r0, c0, c0, 2 // Read TCM Type Register
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// r0 now contains ITCM & DTCM availability
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MRC p15, 0, r0, c9, c1, 1 // Read ITCM Region Register
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// r0 now contains ITCM size in bits [5:2]
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LDR r0, =Image$$CODE$$Base // Set ITCM base address
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ORR r0, r0, #1 // Enable it
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MCR p15, 0, r0, c9, c1, 1 // Write ITCM Region Register
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MRC p15, 0, r0, c9, c1, 0 // Read DTCM Region Register
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// r0 now contains DTCM size in bits [5:2]
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LDR r0, =Image$$DATA$$Base // Set DTCM base address
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ORR r0, r0, #1 // Enable it
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MCR p15, 0, r0, c9, c1, 0 // Write DTCM Region Register
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MRC p15, 0, r0, c1, c0, 1
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TST r0, #(1 << 6) // SMP bit
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ORREQ r0, r0, #(1 << 6) // Set SMP bit in aux control register
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MCREQ p15, 0, r0, c1, c0, 1 // write Aux Control Register (ACTLR)
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//----------------------------------------------------------------
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// MPU Configuration
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//----------------------------------------------------------------
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// Notes:
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// * Regions apply to both instruction and data accesses.
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// * Each region base address must be a multiple of its size
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// * Any address range not covered by an enabled region will abort
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// * The region at 0x0 over the Vector table is needed to support semihosting
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// Region 0: Code Base = 0x0000 Size = 32KB Normal Non-shared Read-only Executable
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// Region 1: Data Base = 0x40000 Size = 128KB Normal Non-shared Full access Not Executable
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// Region 2: Stack/Heap Base = 0x100000 Size = 64KB Normal Non-shared Full access Not Executable
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// Region 3: Vectors Base = 0x0000 Size = 1KB Normal Non-shared Full access Executable
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// Region 4: Peripherals Base = 0xB0000000 Limit = 0xBFFFFFC0 Device Full access Not Executable
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// Import linker symbols to get region base addresses
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.global Image$$CODE$$Base
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.global Image$$DATA$$Base
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.global Image$$ARM_LIB_STACKHEAP$$Base
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// Region 0 - Code
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MOV r1, #0
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MCR p15, 0, r1, c6, c2, 0 // Set memory region number register
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ISB // Ensure subsequent insts execute wrt this region
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LDR r2, =Image$$CODE$$Base
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MCR p15, 0, r2, c6, c1, 0 // Set region base address register
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LDR r2, =0x0 | (Region_1M << 1) | Region_Enable
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MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register
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LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared
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MCR p15, 0, r2, c6, c1, 4 // Set region access control register
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// Region 1 - Data
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ADD r1, r1, #1
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MCR p15, 0, r1, c6, c2, 0 // Set memory region number register
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ISB // Ensure subsequent insts execute wrt this region
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LDR r2, =Image$$DATA$$Base
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MCR p15, 0, r2, c6, c1, 0 // Set region base address register
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LDR r2, =0x0 | (Region_1M << 1) | Region_Enable
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MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register
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LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never
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MCR p15, 0, r2, c6, c1, 4 // Set region access control register
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// Region 2 - Stack/Heap
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ADD r1, r1, #1
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MCR p15, 0, r1, c6, c2, 0 // Set memory region number register
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ISB // Ensure subsequent insts execute wrt this region
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LDR r2, =Image$$ARM_LIB_STACKHEAP$$Base
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MCR p15, 0, r2, c6, c1, 0 // Set region base address register
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LDR r2, =0x0 | (Region_1M << 1) | Region_Enable
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MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register
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LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never
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MCR p15, 0, r2, c6, c1, 4 // Set region access control register
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// Region 3 - Vectors
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ADD r1, r1, #1
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MCR p15, 0, r1, c6, c2, 0 // Set memory region number register
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ISB // Ensure subsequent insts execute wrt this region
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LDR r2, =0
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MCR p15, 0, r2, c6, c1, 0 // Set region base address register
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LDR r2, =0x0 | (Region_1K << 1) | Region_Enable
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MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register
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LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared
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MCR p15, 0, r2, c6, c1, 4 // Set region access control register
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// Region 4 - Peripherals
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ADD r1, r1, #1
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MCR p15, 0, r1, c6, c2, 0 // Set memory region number register
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ISB // Ensure subsequent insts execute wrt this region
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LDR r2, =0xB0000000
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MCR p15, 0, r2, c6, c1, 0 // Set region base address register
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LDR r2, =0x0 | (Region_1K << 1) | Region_Enable
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MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register
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LDR r2, =0x0 | (Full_Access << 8) | Device_nShared | Execute_Never
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MCR p15, 0, r2, c6, c1, 4 // Set region access control register
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// Disable all higher priority regions (assumes unified regions, which is always true for Cortex-R8)
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MRC p15, 0, r0, c0, c0, 4 // Read MPU Type register (MPUIR)
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LSR r0, r0, #8
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AND r0, r0, #0xff // r0 = Number of MPU regions (12, 16, 20, or 24 for Cortex-R8)
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MOV r2, #0 // Value to write to disable region
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region_loop:
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ADD r1, r1, #1
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CMP r0, r1
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BLS regions_done
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MCR p15, 0, r1, c6, c2, 0 // Set memory region number register (RGNR)
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MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register (DRSR)
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B region_loop
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regions_done:
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#ifdef __ARM_FP
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//----------------------------------------------------------------
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// Enable access to VFP by enabling access to Coprocessors 10 and 11.
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// Enables Full Access i.e. in both privileged and non privileged modes
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//----------------------------------------------------------------
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MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR)
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ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11
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MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR)
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ISB
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//----------------------------------------------------------------
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// Switch on the VFP hardware
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//----------------------------------------------------------------
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MOV r0, #0x40000000
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VMSR FPEXC, r0 // Write FPEXC register, EN bit set
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#endif
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//
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// SMP initialization
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// -------------------
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MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register
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ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field
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BNE secondaryCPUsInit
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//----------------------------------------------------------------
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// Enable MPU and branch to C library init
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// Leaving the caches disabled until after scatter loading.
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//----------------------------------------------------------------
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MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
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ORR r0, r0, #0x01 // Set M bit to enable MPU
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ORR r0, r0, #0x800 // Set Z bit to enable branch prediction
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DSB // Ensure all previous loads/stores have completed
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MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
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ISB // Ensure subsequent insts execute wrt new MPU settings
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.global __main
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B __main
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.size Reset_Handler, . - Reset_Handler
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// ------------------------------------------------------------
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// Initialization for SECONDARY CPUs
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// ------------------------------------------------------------
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.global secondaryCPUsInit
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.type secondaryCPUsInit, "function"
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secondaryCPUsInit:
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wfi
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//----------------------------------------------------------------
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// Global Enable for Instruction and Data Caching
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//----------------------------------------------------------------
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.global enable_caches
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.type enable_caches, "function"
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.cfi_startproc
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enable_caches:
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MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
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ORR r0, r0, #(0x1 << 12) // enable I Cache
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ORR r0, r0, #(0x1 << 2) // enable D Cache
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MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
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ISB
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BX lr
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.cfi_endproc
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.size enable_caches, . - enable_caches
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