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CMSIS-DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MML_config.txt

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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
NSC_CFG_0=0 # (bool , init-time) default = '0' : Whether 0x10000000..0x1FFFFFFF is non-secure-callable
NSC_CFG_1=0 # (bool , init-time) default = '0' : Whether 0x30000000..0x3FFFFFFF is non-secure-callable
cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.vfp-enable_at_reset=0 # (bool , init-time) default = '0' : Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: ARM recommends going though the implementation's suggested VFP power-up sequence!
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
cpu0.semihosting-heap_limit=0x10700000 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_base=0x10700000 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_limit=0x10800000 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
cpu0.MPU_TYPE_S.DREGION=0x10 # (int , init-time) default = '0x10' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x100]
cpu0.MPU_TYPE_NS.DREGION=0x10 # (int , init-time) default = '0x10' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x100]
cpu0.ignore_out_of_range_RNR_write=0 # (bool , init-time) default = '0' : If an MPU_RNR.REGION write is out of range, ignore it ; if false, MPU_RNR values wrap
cpu0.ignore_RNR_top_nibble=0 # (bool , init-time) default = '0' : If set, only the bottom four bits of MPU_RNR.REGION are used
cpu0.ITM=1 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included (unless baseline)
cpu0.DWT_TRACE=1 # (bool , init-time) default = '1' : Support for DWT trace. false : No DWT trace included, true: DWT trace included (unless ITM=0, or baseline)
cpu0.number_of_itm_stimulus_ports=0x20 # (int , init-time) default = '0x20' : The number of ITM stimulus ports : [0x8..0x100]
cpu0.LVL_WIDTH=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority (baseline has 2) : [0x3..0x8]
cpu0.AIRCR.ENDIANNESS=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu0.BB_PRESENT=0 # (bool , init-time) default = '0' : Enable bitbanding
cpu0.INITVTOR_S=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITVTOR_NS=0x0 # (int , init-time) default = '0x0' : Non-secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.VTOR_MASK=0xFFFFFF80 # (int , init-time) default = '0xFFFFFF80' : VTOR write mask : [0x0..0xFFFFFF80]
cpu0.min_sync_level=0x0 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.MVFR0.Double-precision=1 # (bool , init-time) default = '1' : Support 8-byte floats
cpu0.scheduler_mode=0x0 # (int , init-time) default = '0x0' : Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare) : [0x0..0x3]
cpu0.has_writebuffer=0 # (bool , init-time) default = '0' : Implement write accesses buffering before L1 cache. May affect ext_abort behaviour.
cpu0.exercise_strex_fail=0 # (bool , init-time) default = '0' : Reject a pseudo-random majority of exclusive store instructions
cpu0.dcache-size=0x8000 # (int , init-time) default = '0x8000' : L1 D-cache size in bytes : [0x0..0x100000]
cpu0.dcache-ways=0x4 # (int , init-time) default = '0x4' : L1 D-cache ways (sets are implicit from size) : [0x1..0x40]
cpu0.icache-size=0x8000 # (int , init-time) default = '0x8000' : L1 I-cache size in bytes : [0x0..0x100000]
cpu0.icache-ways=0x2 # (int , init-time) default = '0x2' : L1 I-cache ways (sets are implicit from size) : [0x1..0x40]
cpu0.itcm_size=0x100 # (int , init-time) default = '0x100' : ITCM size in KB : [0x0..0x4000]
cpu0.dtcm_size=0x100 # (int , init-time) default = '0x100' : DTCM size in KB : [0x0..0x4000]
cpu0.itcm_enable=0 # (bool , init-time) default = '0' : Enable ITCM at reset
cpu0.dtcm_enable=0 # (bool , init-time) default = '0' : Enable DTCM at reset
cpu0.duplicate_CADI_TCM_writes=0 # (bool , init-time) default = '0' : CADI writes to TCMs are also sent to downstream memory at same addresses (for validation platforms)
cpu0.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation
cpu0.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation
cpu0.dcache-invalidate-ns-cleans-s=0 # (bool , init-time) default = '0' : Whether V8M DCI* in non-secure should clean-and-invalidate secure cache contents.
cpu0.rd_s_bus_err_behave=0x1 # (int , init-time) default = '0x1' : External read aborts in secure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO. : [0x0..0x3]
cpu0.wr_s_bus_err_behave=0x3 # (int , init-time) default = '0x3' : External write aborts in secure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO. : [0x0..0x3]
cpu0.rd_ns_bus_err_behave=0x1 # (int , init-time) default = '0x1' : External read aborts in nonsecure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO. : [0x0..0x3]
cpu0.wr_ns_bus_err_behave=0x3 # (int , init-time) default = '0x3' : External write aborts in nonsecure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO. : [0x0..0x3]
cpu0.VTOR_S=1 # (bool , init-time) default = '1' : Secure Vector Table Offset Register is writeable
cpu0.VTOR_NS=1 # (bool , init-time) default = '1' : NonSecure Vector Table Offset Register is writeable
cpu0.ID_DFR0.Debug_Model_M_profile=1 # (bool , init-time) default = '1' : Set whether debug extensions are implemented
cpu0.FP_CTRL.NUM_CODE=0x8 # (int , init-time) default = '0x8' : Number of breakpoint unit comparators implemented (limited to 15 in V6M or baseline) : [0x0..0x7F]
cpu0.DWT_CTRL.NUMCOMP=0x4 # (int , init-time) default = '0x4' : Number of watchpoint unit comparators implemented : [0x0..0xF]
cpu0.DWT_CTRL.NOCYCCNT=0 # (bool , init-time) default = '0' : DWT cycle-counter not present (v8M_bl/v6M never have one).
cpu0.DWT_CTRL.NOPRFCNT=0 # (bool , init-time) default = '0' : DWT performance-counters not present (v8M_bl/v6M never have them).
cpu0.FP_REMAP.RMPSPT=1 # (bool , init-time) default = '1' : FPB supports remapping (ignored if baseline or SECEXT)
cpu0.FP_CTRL.NUM_LIT=0x0 # (int , init-time) default = '0x0' : How many Literals FPB supports remapping (ignored if baseline or TZM) : [0x0..0xF]
cpu0.DWT_FUNCTION0.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION0. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION1.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION1. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION2.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION2. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION3.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION3. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION4.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION4. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION5.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION5. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION6.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION6. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION7.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION7. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION8.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION8. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION9.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION9. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION10.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION10. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION11.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION11. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION12.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION12. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION13.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION13. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION14.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION14. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.DWT_FUNCTION15.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION15. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu0.SAU_TYPE.SREGION=0x10 # (int , init-time) default = '0x10' : Number of SAU regions (0 => no SAU) : [0x0..0x100]
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
cpu0.REGISTER_PUSH_ORDER="" # (string, init-time) default = '' : Order in which the registers are pushed on to the stack during exception handling. A comma separated list of register names and ranges. eg PC,R0-R3,R13-R14,S0-S5,FPSCR
cpu0.SAU_REGION0.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region0 at reset
cpu0.SAU_REGION0.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region0 at reset
cpu0.SAU_REGION0.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region0 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION0.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region0 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION1.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region1 at reset
cpu0.SAU_REGION1.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region1 at reset
cpu0.SAU_REGION1.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region1 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION1.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region1 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION2.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region2 at reset
cpu0.SAU_REGION2.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region2 at reset
cpu0.SAU_REGION2.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region2 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION2.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region2 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION3.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region3 at reset
cpu0.SAU_REGION3.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region3 at reset
cpu0.SAU_REGION3.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region3 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION3.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region3 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION4.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region4 at reset
cpu0.SAU_REGION4.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region4 at reset
cpu0.SAU_REGION4.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region4 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION4.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region4 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION5.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region5 at reset
cpu0.SAU_REGION5.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region5 at reset
cpu0.SAU_REGION5.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region5 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION5.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region5 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION6.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region6 at reset
cpu0.SAU_REGION6.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region6 at reset
cpu0.SAU_REGION6.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region6 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION6.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region6 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION7.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region7 at reset
cpu0.SAU_REGION7.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region7 at reset
cpu0.SAU_REGION7.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region7 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION7.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region7 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION8.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region8 at reset
cpu0.SAU_REGION8.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region8 at reset
cpu0.SAU_REGION8.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region8 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION8.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region8 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION9.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region9 at reset
cpu0.SAU_REGION9.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region9 at reset
cpu0.SAU_REGION9.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region9 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION9.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region9 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION10.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region10 at reset
cpu0.SAU_REGION10.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region10 at reset
cpu0.SAU_REGION10.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region10 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION10.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region10 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION11.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region11 at reset
cpu0.SAU_REGION11.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region11 at reset
cpu0.SAU_REGION11.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region11 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION11.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region11 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION12.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region12 at reset
cpu0.SAU_REGION12.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region12 at reset
cpu0.SAU_REGION12.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region12 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION12.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region12 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION13.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region13 at reset
cpu0.SAU_REGION13.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region13 at reset
cpu0.SAU_REGION13.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region13 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION13.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region13 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION14.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region14 at reset
cpu0.SAU_REGION14.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region14 at reset
cpu0.SAU_REGION14.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region14 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION14.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region14 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION15.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region15 at reset
cpu0.SAU_REGION15.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region15 at reset
cpu0.SAU_REGION15.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region15 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION15.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region15 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION16.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region16 at reset
cpu0.SAU_REGION16.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region16 at reset
cpu0.SAU_REGION16.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region16 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION16.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region16 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION17.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region17 at reset
cpu0.SAU_REGION17.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region17 at reset
cpu0.SAU_REGION17.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region17 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION17.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region17 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION18.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region18 at reset
cpu0.SAU_REGION18.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region18 at reset
cpu0.SAU_REGION18.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region18 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION18.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region18 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION19.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region19 at reset
cpu0.SAU_REGION19.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region19 at reset
cpu0.SAU_REGION19.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region19 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION19.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region19 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION20.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region20 at reset
cpu0.SAU_REGION20.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region20 at reset
cpu0.SAU_REGION20.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region20 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION20.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region20 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION21.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region21 at reset
cpu0.SAU_REGION21.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region21 at reset
cpu0.SAU_REGION21.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region21 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION21.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region21 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION22.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region22 at reset
cpu0.SAU_REGION22.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region22 at reset
cpu0.SAU_REGION22.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region22 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION22.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region22 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION23.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region23 at reset
cpu0.SAU_REGION23.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region23 at reset
cpu0.SAU_REGION23.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region23 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION23.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region23 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION24.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region24 at reset
cpu0.SAU_REGION24.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region24 at reset
cpu0.SAU_REGION24.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region24 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION24.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region24 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION25.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region25 at reset
cpu0.SAU_REGION25.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region25 at reset
cpu0.SAU_REGION25.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region25 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION25.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region25 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION26.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region26 at reset
cpu0.SAU_REGION26.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region26 at reset
cpu0.SAU_REGION26.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region26 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION26.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region26 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION27.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region27 at reset
cpu0.SAU_REGION27.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region27 at reset
cpu0.SAU_REGION27.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region27 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION27.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region27 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION28.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region28 at reset
cpu0.SAU_REGION28.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region28 at reset
cpu0.SAU_REGION28.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region28 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION28.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region28 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION29.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region29 at reset
cpu0.SAU_REGION29.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region29 at reset
cpu0.SAU_REGION29.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region29 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION29.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region29 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION30.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region30 at reset
cpu0.SAU_REGION30.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region30 at reset
cpu0.SAU_REGION30.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region30 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION30.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region30 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION31.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region31 at reset
cpu0.SAU_REGION31.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region31 at reset
cpu0.SAU_REGION31.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region31 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION31.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region31 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION32.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region32 at reset
cpu0.SAU_REGION32.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region32 at reset
cpu0.SAU_REGION32.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region32 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION32.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region32 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION33.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region33 at reset
cpu0.SAU_REGION33.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region33 at reset
cpu0.SAU_REGION33.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region33 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION33.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region33 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION34.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region34 at reset
cpu0.SAU_REGION34.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region34 at reset
cpu0.SAU_REGION34.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region34 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION34.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region34 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION35.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region35 at reset
cpu0.SAU_REGION35.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region35 at reset
cpu0.SAU_REGION35.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region35 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION35.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region35 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION36.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region36 at reset
cpu0.SAU_REGION36.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region36 at reset
cpu0.SAU_REGION36.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region36 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION36.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region36 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION37.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region37 at reset
cpu0.SAU_REGION37.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region37 at reset
cpu0.SAU_REGION37.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region37 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION37.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region37 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION38.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region38 at reset
cpu0.SAU_REGION38.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region38 at reset
cpu0.SAU_REGION38.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region38 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION38.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region38 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION39.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region39 at reset
cpu0.SAU_REGION39.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region39 at reset
cpu0.SAU_REGION39.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region39 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION39.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region39 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION40.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region40 at reset
cpu0.SAU_REGION40.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region40 at reset
cpu0.SAU_REGION40.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region40 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION40.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region40 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION41.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region41 at reset
cpu0.SAU_REGION41.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region41 at reset
cpu0.SAU_REGION41.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region41 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION41.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region41 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION42.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region42 at reset
cpu0.SAU_REGION42.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region42 at reset
cpu0.SAU_REGION42.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region42 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION42.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region42 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION43.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region43 at reset
cpu0.SAU_REGION43.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region43 at reset
cpu0.SAU_REGION43.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region43 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION43.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region43 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION44.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region44 at reset
cpu0.SAU_REGION44.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region44 at reset
cpu0.SAU_REGION44.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region44 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION44.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region44 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION45.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region45 at reset
cpu0.SAU_REGION45.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region45 at reset
cpu0.SAU_REGION45.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region45 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION45.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region45 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION46.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region46 at reset
cpu0.SAU_REGION46.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region46 at reset
cpu0.SAU_REGION46.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region46 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION46.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region46 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION47.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region47 at reset
cpu0.SAU_REGION47.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region47 at reset
cpu0.SAU_REGION47.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region47 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION47.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region47 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION48.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region48 at reset
cpu0.SAU_REGION48.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region48 at reset
cpu0.SAU_REGION48.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region48 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION48.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region48 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION49.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region49 at reset
cpu0.SAU_REGION49.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region49 at reset
cpu0.SAU_REGION49.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region49 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION49.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region49 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION50.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region50 at reset
cpu0.SAU_REGION50.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region50 at reset
cpu0.SAU_REGION50.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region50 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION50.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region50 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION51.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region51 at reset
cpu0.SAU_REGION51.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region51 at reset
cpu0.SAU_REGION51.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region51 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION51.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region51 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION52.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region52 at reset
cpu0.SAU_REGION52.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region52 at reset
cpu0.SAU_REGION52.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region52 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION52.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region52 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION53.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region53 at reset
cpu0.SAU_REGION53.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region53 at reset
cpu0.SAU_REGION53.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region53 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION53.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region53 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION54.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region54 at reset
cpu0.SAU_REGION54.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region54 at reset
cpu0.SAU_REGION54.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region54 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION54.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region54 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION55.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region55 at reset
cpu0.SAU_REGION55.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region55 at reset
cpu0.SAU_REGION55.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region55 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION55.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region55 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION56.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region56 at reset
cpu0.SAU_REGION56.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region56 at reset
cpu0.SAU_REGION56.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region56 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION56.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region56 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION57.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region57 at reset
cpu0.SAU_REGION57.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region57 at reset
cpu0.SAU_REGION57.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region57 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION57.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region57 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION58.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region58 at reset
cpu0.SAU_REGION58.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region58 at reset
cpu0.SAU_REGION58.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region58 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION58.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region58 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION59.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region59 at reset
cpu0.SAU_REGION59.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region59 at reset
cpu0.SAU_REGION59.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region59 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION59.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region59 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION60.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region60 at reset
cpu0.SAU_REGION60.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region60 at reset
cpu0.SAU_REGION60.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region60 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION60.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region60 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION61.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region61 at reset
cpu0.SAU_REGION61.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region61 at reset
cpu0.SAU_REGION61.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region61 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION61.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region61 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION62.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region62 at reset
cpu0.SAU_REGION62.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region62 at reset
cpu0.SAU_REGION62.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region62 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION62.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region62 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION63.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region63 at reset
cpu0.SAU_REGION63.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region63 at reset
cpu0.SAU_REGION63.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region63 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION63.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region63 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION64.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region64 at reset
cpu0.SAU_REGION64.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region64 at reset
cpu0.SAU_REGION64.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region64 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION64.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region64 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION65.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region65 at reset
cpu0.SAU_REGION65.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region65 at reset
cpu0.SAU_REGION65.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region65 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION65.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region65 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION66.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region66 at reset
cpu0.SAU_REGION66.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region66 at reset
cpu0.SAU_REGION66.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region66 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION66.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region66 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION67.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region67 at reset
cpu0.SAU_REGION67.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region67 at reset
cpu0.SAU_REGION67.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region67 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION67.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region67 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION68.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region68 at reset
cpu0.SAU_REGION68.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region68 at reset
cpu0.SAU_REGION68.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region68 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION68.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region68 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION69.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region69 at reset
cpu0.SAU_REGION69.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region69 at reset
cpu0.SAU_REGION69.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region69 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION69.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region69 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION70.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region70 at reset
cpu0.SAU_REGION70.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region70 at reset
cpu0.SAU_REGION70.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region70 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION70.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region70 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION71.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region71 at reset
cpu0.SAU_REGION71.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region71 at reset
cpu0.SAU_REGION71.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region71 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION71.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region71 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION72.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region72 at reset
cpu0.SAU_REGION72.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region72 at reset
cpu0.SAU_REGION72.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region72 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION72.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region72 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION73.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region73 at reset
cpu0.SAU_REGION73.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region73 at reset
cpu0.SAU_REGION73.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region73 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION73.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region73 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION74.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region74 at reset
cpu0.SAU_REGION74.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region74 at reset
cpu0.SAU_REGION74.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region74 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION74.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region74 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION75.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region75 at reset
cpu0.SAU_REGION75.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region75 at reset
cpu0.SAU_REGION75.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region75 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION75.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region75 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION76.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region76 at reset
cpu0.SAU_REGION76.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region76 at reset
cpu0.SAU_REGION76.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region76 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION76.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region76 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION77.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region77 at reset
cpu0.SAU_REGION77.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region77 at reset
cpu0.SAU_REGION77.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region77 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION77.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region77 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION78.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region78 at reset
cpu0.SAU_REGION78.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region78 at reset
cpu0.SAU_REGION78.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region78 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION78.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region78 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION79.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region79 at reset
cpu0.SAU_REGION79.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region79 at reset
cpu0.SAU_REGION79.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region79 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION79.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region79 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION80.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region80 at reset
cpu0.SAU_REGION80.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region80 at reset
cpu0.SAU_REGION80.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region80 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION80.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region80 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION81.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region81 at reset
cpu0.SAU_REGION81.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region81 at reset
cpu0.SAU_REGION81.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region81 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION81.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region81 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION82.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region82 at reset
cpu0.SAU_REGION82.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region82 at reset
cpu0.SAU_REGION82.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region82 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION82.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region82 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION83.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region83 at reset
cpu0.SAU_REGION83.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region83 at reset
cpu0.SAU_REGION83.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region83 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION83.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region83 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION84.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region84 at reset
cpu0.SAU_REGION84.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region84 at reset
cpu0.SAU_REGION84.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region84 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION84.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region84 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION85.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region85 at reset
cpu0.SAU_REGION85.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region85 at reset
cpu0.SAU_REGION85.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region85 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION85.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region85 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION86.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region86 at reset
cpu0.SAU_REGION86.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region86 at reset
cpu0.SAU_REGION86.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region86 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION86.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region86 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION87.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region87 at reset
cpu0.SAU_REGION87.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region87 at reset
cpu0.SAU_REGION87.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region87 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION87.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region87 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION88.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region88 at reset
cpu0.SAU_REGION88.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region88 at reset
cpu0.SAU_REGION88.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region88 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION88.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region88 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION89.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region89 at reset
cpu0.SAU_REGION89.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region89 at reset
cpu0.SAU_REGION89.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region89 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION89.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region89 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION90.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region90 at reset
cpu0.SAU_REGION90.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region90 at reset
cpu0.SAU_REGION90.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region90 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION90.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region90 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION91.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region91 at reset
cpu0.SAU_REGION91.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region91 at reset
cpu0.SAU_REGION91.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region91 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION91.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region91 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION92.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region92 at reset
cpu0.SAU_REGION92.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region92 at reset
cpu0.SAU_REGION92.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region92 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION92.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region92 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION93.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region93 at reset
cpu0.SAU_REGION93.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region93 at reset
cpu0.SAU_REGION93.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region93 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION93.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region93 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION94.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region94 at reset
cpu0.SAU_REGION94.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region94 at reset
cpu0.SAU_REGION94.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region94 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION94.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region94 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION95.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region95 at reset
cpu0.SAU_REGION95.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region95 at reset
cpu0.SAU_REGION95.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region95 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION95.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region95 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION96.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region96 at reset
cpu0.SAU_REGION96.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region96 at reset
cpu0.SAU_REGION96.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region96 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION96.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region96 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION97.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region97 at reset
cpu0.SAU_REGION97.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region97 at reset
cpu0.SAU_REGION97.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region97 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION97.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region97 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION98.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region98 at reset
cpu0.SAU_REGION98.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region98 at reset
cpu0.SAU_REGION98.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region98 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION98.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region98 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION99.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region99 at reset
cpu0.SAU_REGION99.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region99 at reset
cpu0.SAU_REGION99.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region99 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION99.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region99 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION100.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region100 at reset
cpu0.SAU_REGION100.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region100 at reset
cpu0.SAU_REGION100.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region100 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION100.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region100 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION101.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region101 at reset
cpu0.SAU_REGION101.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region101 at reset
cpu0.SAU_REGION101.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region101 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION101.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region101 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION102.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region102 at reset
cpu0.SAU_REGION102.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region102 at reset
cpu0.SAU_REGION102.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region102 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION102.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region102 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION103.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region103 at reset
cpu0.SAU_REGION103.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region103 at reset
cpu0.SAU_REGION103.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region103 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION103.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region103 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION104.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region104 at reset
cpu0.SAU_REGION104.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region104 at reset
cpu0.SAU_REGION104.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region104 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION104.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region104 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION105.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region105 at reset
cpu0.SAU_REGION105.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region105 at reset
cpu0.SAU_REGION105.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region105 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION105.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region105 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION106.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region106 at reset
cpu0.SAU_REGION106.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region106 at reset
cpu0.SAU_REGION106.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region106 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION106.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region106 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION107.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region107 at reset
cpu0.SAU_REGION107.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region107 at reset
cpu0.SAU_REGION107.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region107 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION107.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region107 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION108.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region108 at reset
cpu0.SAU_REGION108.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region108 at reset
cpu0.SAU_REGION108.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region108 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION108.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region108 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION109.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region109 at reset
cpu0.SAU_REGION109.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region109 at reset
cpu0.SAU_REGION109.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region109 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION109.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region109 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION110.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region110 at reset
cpu0.SAU_REGION110.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region110 at reset
cpu0.SAU_REGION110.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region110 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION110.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region110 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION111.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region111 at reset
cpu0.SAU_REGION111.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region111 at reset
cpu0.SAU_REGION111.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region111 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION111.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region111 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION112.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region112 at reset
cpu0.SAU_REGION112.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region112 at reset
cpu0.SAU_REGION112.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region112 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION112.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region112 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION113.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region113 at reset
cpu0.SAU_REGION113.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region113 at reset
cpu0.SAU_REGION113.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region113 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION113.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region113 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION114.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region114 at reset
cpu0.SAU_REGION114.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region114 at reset
cpu0.SAU_REGION114.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region114 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION114.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region114 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION115.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region115 at reset
cpu0.SAU_REGION115.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region115 at reset
cpu0.SAU_REGION115.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region115 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION115.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region115 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION116.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region116 at reset
cpu0.SAU_REGION116.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region116 at reset
cpu0.SAU_REGION116.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region116 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION116.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region116 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION117.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region117 at reset
cpu0.SAU_REGION117.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region117 at reset
cpu0.SAU_REGION117.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region117 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION117.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region117 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION118.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region118 at reset
cpu0.SAU_REGION118.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region118 at reset
cpu0.SAU_REGION118.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region118 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION118.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region118 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION119.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region119 at reset
cpu0.SAU_REGION119.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region119 at reset
cpu0.SAU_REGION119.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region119 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION119.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region119 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION120.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region120 at reset
cpu0.SAU_REGION120.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region120 at reset
cpu0.SAU_REGION120.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region120 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION120.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region120 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION121.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region121 at reset
cpu0.SAU_REGION121.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region121 at reset
cpu0.SAU_REGION121.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region121 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION121.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region121 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION122.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region122 at reset
cpu0.SAU_REGION122.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region122 at reset
cpu0.SAU_REGION122.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region122 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION122.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region122 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION123.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region123 at reset
cpu0.SAU_REGION123.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region123 at reset
cpu0.SAU_REGION123.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region123 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION123.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region123 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION124.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region124 at reset
cpu0.SAU_REGION124.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region124 at reset
cpu0.SAU_REGION124.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region124 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION124.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region124 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION125.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region125 at reset
cpu0.SAU_REGION125.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region125 at reset
cpu0.SAU_REGION125.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region125 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION125.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region125 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION126.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region126 at reset
cpu0.SAU_REGION126.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region126 at reset
cpu0.SAU_REGION126.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region126 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION126.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region126 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION127.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region127 at reset
cpu0.SAU_REGION127.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region127 at reset
cpu0.SAU_REGION127.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region127 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION127.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region127 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION128.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region128 at reset
cpu0.SAU_REGION128.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region128 at reset
cpu0.SAU_REGION128.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region128 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION128.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region128 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION129.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region129 at reset
cpu0.SAU_REGION129.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region129 at reset
cpu0.SAU_REGION129.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region129 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION129.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region129 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION130.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region130 at reset
cpu0.SAU_REGION130.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region130 at reset
cpu0.SAU_REGION130.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region130 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION130.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region130 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION131.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region131 at reset
cpu0.SAU_REGION131.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region131 at reset
cpu0.SAU_REGION131.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region131 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION131.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region131 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION132.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region132 at reset
cpu0.SAU_REGION132.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region132 at reset
cpu0.SAU_REGION132.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region132 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION132.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region132 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION133.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region133 at reset
cpu0.SAU_REGION133.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region133 at reset
cpu0.SAU_REGION133.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region133 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION133.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region133 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION134.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region134 at reset
cpu0.SAU_REGION134.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region134 at reset
cpu0.SAU_REGION134.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region134 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION134.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region134 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION135.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region135 at reset
cpu0.SAU_REGION135.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region135 at reset
cpu0.SAU_REGION135.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region135 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION135.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region135 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION136.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region136 at reset
cpu0.SAU_REGION136.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region136 at reset
cpu0.SAU_REGION136.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region136 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION136.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region136 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION137.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region137 at reset
cpu0.SAU_REGION137.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region137 at reset
cpu0.SAU_REGION137.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region137 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION137.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region137 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION138.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region138 at reset
cpu0.SAU_REGION138.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region138 at reset
cpu0.SAU_REGION138.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region138 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION138.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region138 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION139.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region139 at reset
cpu0.SAU_REGION139.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region139 at reset
cpu0.SAU_REGION139.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region139 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION139.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region139 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION140.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region140 at reset
cpu0.SAU_REGION140.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region140 at reset
cpu0.SAU_REGION140.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region140 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION140.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region140 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION141.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region141 at reset
cpu0.SAU_REGION141.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region141 at reset
cpu0.SAU_REGION141.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region141 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION141.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region141 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION142.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region142 at reset
cpu0.SAU_REGION142.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region142 at reset
cpu0.SAU_REGION142.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region142 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION142.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region142 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION143.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region143 at reset
cpu0.SAU_REGION143.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region143 at reset
cpu0.SAU_REGION143.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region143 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION143.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region143 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION144.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region144 at reset
cpu0.SAU_REGION144.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region144 at reset
cpu0.SAU_REGION144.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region144 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION144.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region144 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION145.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region145 at reset
cpu0.SAU_REGION145.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region145 at reset
cpu0.SAU_REGION145.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region145 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION145.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region145 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION146.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region146 at reset
cpu0.SAU_REGION146.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region146 at reset
cpu0.SAU_REGION146.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region146 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION146.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region146 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION147.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region147 at reset
cpu0.SAU_REGION147.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region147 at reset
cpu0.SAU_REGION147.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region147 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION147.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region147 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION148.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region148 at reset
cpu0.SAU_REGION148.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region148 at reset
cpu0.SAU_REGION148.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region148 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION148.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region148 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION149.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region149 at reset
cpu0.SAU_REGION149.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region149 at reset
cpu0.SAU_REGION149.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region149 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION149.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region149 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION150.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region150 at reset
cpu0.SAU_REGION150.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region150 at reset
cpu0.SAU_REGION150.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region150 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION150.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region150 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION151.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region151 at reset
cpu0.SAU_REGION151.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region151 at reset
cpu0.SAU_REGION151.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region151 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION151.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region151 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION152.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region152 at reset
cpu0.SAU_REGION152.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region152 at reset
cpu0.SAU_REGION152.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region152 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION152.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region152 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION153.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region153 at reset
cpu0.SAU_REGION153.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region153 at reset
cpu0.SAU_REGION153.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region153 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION153.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region153 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION154.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region154 at reset
cpu0.SAU_REGION154.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region154 at reset
cpu0.SAU_REGION154.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region154 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION154.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region154 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION155.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region155 at reset
cpu0.SAU_REGION155.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region155 at reset
cpu0.SAU_REGION155.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region155 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION155.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region155 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION156.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region156 at reset
cpu0.SAU_REGION156.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region156 at reset
cpu0.SAU_REGION156.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region156 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION156.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region156 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION157.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region157 at reset
cpu0.SAU_REGION157.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region157 at reset
cpu0.SAU_REGION157.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region157 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION157.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region157 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION158.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region158 at reset
cpu0.SAU_REGION158.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region158 at reset
cpu0.SAU_REGION158.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region158 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION158.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region158 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION159.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region159 at reset
cpu0.SAU_REGION159.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region159 at reset
cpu0.SAU_REGION159.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region159 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION159.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region159 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION160.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region160 at reset
cpu0.SAU_REGION160.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region160 at reset
cpu0.SAU_REGION160.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region160 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION160.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region160 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION161.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region161 at reset
cpu0.SAU_REGION161.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region161 at reset
cpu0.SAU_REGION161.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region161 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION161.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region161 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION162.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region162 at reset
cpu0.SAU_REGION162.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region162 at reset
cpu0.SAU_REGION162.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region162 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION162.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region162 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION163.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region163 at reset
cpu0.SAU_REGION163.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region163 at reset
cpu0.SAU_REGION163.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region163 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION163.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region163 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION164.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region164 at reset
cpu0.SAU_REGION164.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region164 at reset
cpu0.SAU_REGION164.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region164 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION164.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region164 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION165.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region165 at reset
cpu0.SAU_REGION165.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region165 at reset
cpu0.SAU_REGION165.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region165 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION165.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region165 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION166.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region166 at reset
cpu0.SAU_REGION166.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region166 at reset
cpu0.SAU_REGION166.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region166 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION166.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region166 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION167.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region167 at reset
cpu0.SAU_REGION167.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region167 at reset
cpu0.SAU_REGION167.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region167 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION167.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region167 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION168.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region168 at reset
cpu0.SAU_REGION168.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region168 at reset
cpu0.SAU_REGION168.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region168 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION168.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region168 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION169.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region169 at reset
cpu0.SAU_REGION169.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region169 at reset
cpu0.SAU_REGION169.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region169 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION169.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region169 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION170.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region170 at reset
cpu0.SAU_REGION170.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region170 at reset
cpu0.SAU_REGION170.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region170 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION170.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region170 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION171.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region171 at reset
cpu0.SAU_REGION171.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region171 at reset
cpu0.SAU_REGION171.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region171 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION171.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region171 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION172.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region172 at reset
cpu0.SAU_REGION172.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region172 at reset
cpu0.SAU_REGION172.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region172 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION172.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region172 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION173.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region173 at reset
cpu0.SAU_REGION173.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region173 at reset
cpu0.SAU_REGION173.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region173 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION173.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region173 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION174.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region174 at reset
cpu0.SAU_REGION174.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region174 at reset
cpu0.SAU_REGION174.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region174 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION174.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region174 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION175.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region175 at reset
cpu0.SAU_REGION175.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region175 at reset
cpu0.SAU_REGION175.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region175 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION175.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region175 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION176.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region176 at reset
cpu0.SAU_REGION176.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region176 at reset
cpu0.SAU_REGION176.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region176 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION176.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region176 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION177.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region177 at reset
cpu0.SAU_REGION177.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region177 at reset
cpu0.SAU_REGION177.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region177 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION177.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region177 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION178.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region178 at reset
cpu0.SAU_REGION178.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region178 at reset
cpu0.SAU_REGION178.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region178 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION178.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region178 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION179.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region179 at reset
cpu0.SAU_REGION179.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region179 at reset
cpu0.SAU_REGION179.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region179 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION179.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region179 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION180.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region180 at reset
cpu0.SAU_REGION180.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region180 at reset
cpu0.SAU_REGION180.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region180 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION180.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region180 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION181.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region181 at reset
cpu0.SAU_REGION181.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region181 at reset
cpu0.SAU_REGION181.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region181 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION181.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region181 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION182.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region182 at reset
cpu0.SAU_REGION182.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region182 at reset
cpu0.SAU_REGION182.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region182 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION182.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region182 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION183.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region183 at reset
cpu0.SAU_REGION183.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region183 at reset
cpu0.SAU_REGION183.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region183 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION183.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region183 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION184.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region184 at reset
cpu0.SAU_REGION184.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region184 at reset
cpu0.SAU_REGION184.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region184 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION184.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region184 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION185.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region185 at reset
cpu0.SAU_REGION185.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region185 at reset
cpu0.SAU_REGION185.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region185 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION185.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region185 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION186.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region186 at reset
cpu0.SAU_REGION186.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region186 at reset
cpu0.SAU_REGION186.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region186 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION186.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region186 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION187.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region187 at reset
cpu0.SAU_REGION187.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region187 at reset
cpu0.SAU_REGION187.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region187 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION187.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region187 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION188.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region188 at reset
cpu0.SAU_REGION188.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region188 at reset
cpu0.SAU_REGION188.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region188 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION188.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region188 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION189.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region189 at reset
cpu0.SAU_REGION189.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region189 at reset
cpu0.SAU_REGION189.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region189 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION189.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region189 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION190.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region190 at reset
cpu0.SAU_REGION190.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region190 at reset
cpu0.SAU_REGION190.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region190 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION190.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region190 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION191.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region191 at reset
cpu0.SAU_REGION191.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region191 at reset
cpu0.SAU_REGION191.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region191 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION191.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region191 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION192.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region192 at reset
cpu0.SAU_REGION192.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region192 at reset
cpu0.SAU_REGION192.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region192 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION192.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region192 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION193.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region193 at reset
cpu0.SAU_REGION193.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region193 at reset
cpu0.SAU_REGION193.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region193 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION193.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region193 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION194.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region194 at reset
cpu0.SAU_REGION194.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region194 at reset
cpu0.SAU_REGION194.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region194 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION194.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region194 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION195.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region195 at reset
cpu0.SAU_REGION195.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region195 at reset
cpu0.SAU_REGION195.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region195 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION195.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region195 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION196.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region196 at reset
cpu0.SAU_REGION196.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region196 at reset
cpu0.SAU_REGION196.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region196 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION196.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region196 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION197.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region197 at reset
cpu0.SAU_REGION197.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region197 at reset
cpu0.SAU_REGION197.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region197 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION197.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region197 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION198.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region198 at reset
cpu0.SAU_REGION198.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region198 at reset
cpu0.SAU_REGION198.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region198 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION198.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region198 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION199.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region199 at reset
cpu0.SAU_REGION199.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region199 at reset
cpu0.SAU_REGION199.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region199 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION199.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region199 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION200.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region200 at reset
cpu0.SAU_REGION200.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region200 at reset
cpu0.SAU_REGION200.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region200 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION200.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region200 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION201.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region201 at reset
cpu0.SAU_REGION201.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region201 at reset
cpu0.SAU_REGION201.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region201 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION201.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region201 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION202.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region202 at reset
cpu0.SAU_REGION202.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region202 at reset
cpu0.SAU_REGION202.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region202 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION202.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region202 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION203.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region203 at reset
cpu0.SAU_REGION203.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region203 at reset
cpu0.SAU_REGION203.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region203 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION203.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region203 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION204.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region204 at reset
cpu0.SAU_REGION204.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region204 at reset
cpu0.SAU_REGION204.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region204 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION204.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region204 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION205.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region205 at reset
cpu0.SAU_REGION205.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region205 at reset
cpu0.SAU_REGION205.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region205 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION205.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region205 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION206.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region206 at reset
cpu0.SAU_REGION206.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region206 at reset
cpu0.SAU_REGION206.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region206 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION206.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region206 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION207.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region207 at reset
cpu0.SAU_REGION207.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region207 at reset
cpu0.SAU_REGION207.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region207 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION207.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region207 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION208.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region208 at reset
cpu0.SAU_REGION208.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region208 at reset
cpu0.SAU_REGION208.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region208 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION208.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region208 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION209.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region209 at reset
cpu0.SAU_REGION209.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region209 at reset
cpu0.SAU_REGION209.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region209 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION209.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region209 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION210.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region210 at reset
cpu0.SAU_REGION210.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region210 at reset
cpu0.SAU_REGION210.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region210 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION210.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region210 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION211.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region211 at reset
cpu0.SAU_REGION211.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region211 at reset
cpu0.SAU_REGION211.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region211 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION211.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region211 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION212.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region212 at reset
cpu0.SAU_REGION212.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region212 at reset
cpu0.SAU_REGION212.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region212 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION212.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region212 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION213.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region213 at reset
cpu0.SAU_REGION213.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region213 at reset
cpu0.SAU_REGION213.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region213 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION213.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region213 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION214.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region214 at reset
cpu0.SAU_REGION214.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region214 at reset
cpu0.SAU_REGION214.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region214 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION214.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region214 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION215.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region215 at reset
cpu0.SAU_REGION215.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region215 at reset
cpu0.SAU_REGION215.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region215 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION215.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region215 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION216.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region216 at reset
cpu0.SAU_REGION216.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region216 at reset
cpu0.SAU_REGION216.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region216 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION216.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region216 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION217.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region217 at reset
cpu0.SAU_REGION217.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region217 at reset
cpu0.SAU_REGION217.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region217 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION217.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region217 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION218.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region218 at reset
cpu0.SAU_REGION218.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region218 at reset
cpu0.SAU_REGION218.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region218 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION218.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region218 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION219.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region219 at reset
cpu0.SAU_REGION219.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region219 at reset
cpu0.SAU_REGION219.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region219 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION219.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region219 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION220.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region220 at reset
cpu0.SAU_REGION220.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region220 at reset
cpu0.SAU_REGION220.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region220 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION220.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region220 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION221.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region221 at reset
cpu0.SAU_REGION221.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region221 at reset
cpu0.SAU_REGION221.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region221 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION221.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region221 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION222.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region222 at reset
cpu0.SAU_REGION222.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region222 at reset
cpu0.SAU_REGION222.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region222 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION222.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region222 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION223.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region223 at reset
cpu0.SAU_REGION223.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region223 at reset
cpu0.SAU_REGION223.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region223 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION223.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region223 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION224.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region224 at reset
cpu0.SAU_REGION224.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region224 at reset
cpu0.SAU_REGION224.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region224 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION224.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region224 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION225.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region225 at reset
cpu0.SAU_REGION225.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region225 at reset
cpu0.SAU_REGION225.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region225 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION225.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region225 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION226.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region226 at reset
cpu0.SAU_REGION226.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region226 at reset
cpu0.SAU_REGION226.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region226 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION226.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region226 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION227.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region227 at reset
cpu0.SAU_REGION227.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region227 at reset
cpu0.SAU_REGION227.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region227 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION227.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region227 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION228.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region228 at reset
cpu0.SAU_REGION228.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region228 at reset
cpu0.SAU_REGION228.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region228 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION228.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region228 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION229.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region229 at reset
cpu0.SAU_REGION229.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region229 at reset
cpu0.SAU_REGION229.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region229 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION229.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region229 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION230.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region230 at reset
cpu0.SAU_REGION230.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region230 at reset
cpu0.SAU_REGION230.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region230 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION230.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region230 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION231.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region231 at reset
cpu0.SAU_REGION231.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region231 at reset
cpu0.SAU_REGION231.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region231 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION231.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region231 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION232.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region232 at reset
cpu0.SAU_REGION232.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region232 at reset
cpu0.SAU_REGION232.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region232 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION232.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region232 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION233.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region233 at reset
cpu0.SAU_REGION233.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region233 at reset
cpu0.SAU_REGION233.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region233 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION233.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region233 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION234.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region234 at reset
cpu0.SAU_REGION234.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region234 at reset
cpu0.SAU_REGION234.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region234 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION234.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region234 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION235.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region235 at reset
cpu0.SAU_REGION235.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region235 at reset
cpu0.SAU_REGION235.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region235 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION235.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region235 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION236.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region236 at reset
cpu0.SAU_REGION236.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region236 at reset
cpu0.SAU_REGION236.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region236 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION236.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region236 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION237.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region237 at reset
cpu0.SAU_REGION237.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region237 at reset
cpu0.SAU_REGION237.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region237 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION237.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region237 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION238.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region238 at reset
cpu0.SAU_REGION238.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region238 at reset
cpu0.SAU_REGION238.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region238 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION238.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region238 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION239.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region239 at reset
cpu0.SAU_REGION239.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region239 at reset
cpu0.SAU_REGION239.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region239 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION239.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region239 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION240.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region240 at reset
cpu0.SAU_REGION240.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region240 at reset
cpu0.SAU_REGION240.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region240 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION240.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region240 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION241.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region241 at reset
cpu0.SAU_REGION241.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region241 at reset
cpu0.SAU_REGION241.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region241 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION241.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region241 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION242.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region242 at reset
cpu0.SAU_REGION242.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region242 at reset
cpu0.SAU_REGION242.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region242 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION242.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region242 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION243.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region243 at reset
cpu0.SAU_REGION243.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region243 at reset
cpu0.SAU_REGION243.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region243 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION243.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region243 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION244.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region244 at reset
cpu0.SAU_REGION244.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region244 at reset
cpu0.SAU_REGION244.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region244 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION244.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region244 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION245.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region245 at reset
cpu0.SAU_REGION245.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region245 at reset
cpu0.SAU_REGION245.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region245 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION245.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region245 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION246.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region246 at reset
cpu0.SAU_REGION246.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region246 at reset
cpu0.SAU_REGION246.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region246 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION246.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region246 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION247.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region247 at reset
cpu0.SAU_REGION247.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region247 at reset
cpu0.SAU_REGION247.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region247 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION247.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region247 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION248.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region248 at reset
cpu0.SAU_REGION248.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region248 at reset
cpu0.SAU_REGION248.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region248 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION248.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region248 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION249.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region249 at reset
cpu0.SAU_REGION249.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region249 at reset
cpu0.SAU_REGION249.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region249 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION249.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region249 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION250.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region250 at reset
cpu0.SAU_REGION250.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region250 at reset
cpu0.SAU_REGION250.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region250 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION250.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region250 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION251.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region251 at reset
cpu0.SAU_REGION251.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region251 at reset
cpu0.SAU_REGION251.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region251 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION251.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region251 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION252.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region252 at reset
cpu0.SAU_REGION252.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region252 at reset
cpu0.SAU_REGION252.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region252 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION252.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region252 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION253.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region253 at reset
cpu0.SAU_REGION253.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region253 at reset
cpu0.SAU_REGION253.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region253 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION253.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region253 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION254.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region254 at reset
cpu0.SAU_REGION254.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region254 at reset
cpu0.SAU_REGION254.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region254 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION254.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region254 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION255.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region255 at reset
cpu0.SAU_REGION255.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region255 at reset
cpu0.SAU_REGION255.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region255 at reset : [0x0..0xFFFFFFFF]
cpu0.SAU_REGION255.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region255 at reset : [0x0..0xFFFFFFFF]
cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.IDAU_REGION0.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region0 as exempt
cpu0.IDAU_REGION1.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region1 as exempt
cpu0.IDAU_REGION2.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region2 as exempt
cpu0.IDAU_REGION3.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region3 as exempt
cpu0.IDAU_REGION4.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region4 as exempt
cpu0.IDAU_REGION5.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region5 as exempt
cpu0.IDAU_REGION6.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region6 as exempt
cpu0.IDAU_REGION7.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region7 as exempt
cpu0.IDAU_REGION8.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region8 as exempt
cpu0.IDAU_REGION9.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region9 as exempt
cpu0.IDAU_REGION10.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region10 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION10.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region10
cpu0.IDAU_REGION10.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region10 as exempt
cpu0.IDAU_REGION10.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region10 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION10.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region10 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION11.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region11 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION11.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region11
cpu0.IDAU_REGION11.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region11 as exempt
cpu0.IDAU_REGION11.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region11 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION11.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region11 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION12.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region12 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION12.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region12
cpu0.IDAU_REGION12.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region12 as exempt
cpu0.IDAU_REGION12.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region12 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION12.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region12 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION13.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region13 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION13.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region13
cpu0.IDAU_REGION13.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region13 as exempt
cpu0.IDAU_REGION13.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region13 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION13.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region13 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION14.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region14 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION14.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region14
cpu0.IDAU_REGION14.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region14 as exempt
cpu0.IDAU_REGION14.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region14 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION14.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region14 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION15.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region15 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION15.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region15
cpu0.IDAU_REGION15.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region15 as exempt
cpu0.IDAU_REGION15.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region15 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION15.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region15 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION16.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region16 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION16.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region16
cpu0.IDAU_REGION16.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region16 as exempt
cpu0.IDAU_REGION16.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region16 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION16.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region16 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION17.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region17 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION17.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region17
cpu0.IDAU_REGION17.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region17 as exempt
cpu0.IDAU_REGION17.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region17 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION17.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region17 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION18.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region18 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION18.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region18
cpu0.IDAU_REGION18.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region18 as exempt
cpu0.IDAU_REGION18.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region18 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION18.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region18 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION19.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region19 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION19.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region19
cpu0.IDAU_REGION19.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region19 as exempt
cpu0.IDAU_REGION19.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region19 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION19.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region19 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION20.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region20 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION20.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region20
cpu0.IDAU_REGION20.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region20 as exempt
cpu0.IDAU_REGION20.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region20 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION20.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region20 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION21.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region21 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION21.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region21
cpu0.IDAU_REGION21.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region21 as exempt
cpu0.IDAU_REGION21.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region21 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION21.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region21 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION22.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region22 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION22.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region22
cpu0.IDAU_REGION22.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region22 as exempt
cpu0.IDAU_REGION22.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region22 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION22.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region22 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION23.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region23 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION23.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region23
cpu0.IDAU_REGION23.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region23 as exempt
cpu0.IDAU_REGION23.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region23 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION23.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region23 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION24.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region24 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION24.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region24
cpu0.IDAU_REGION24.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region24 as exempt
cpu0.IDAU_REGION24.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region24 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION24.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region24 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION25.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region25 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION25.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region25
cpu0.IDAU_REGION25.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region25 as exempt
cpu0.IDAU_REGION25.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region25 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION25.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region25 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION26.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region26 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION26.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region26
cpu0.IDAU_REGION26.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region26 as exempt
cpu0.IDAU_REGION26.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region26 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION26.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region26 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION27.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region27 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION27.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region27
cpu0.IDAU_REGION27.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region27 as exempt
cpu0.IDAU_REGION27.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region27 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION27.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region27 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION28.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region28 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION28.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region28
cpu0.IDAU_REGION28.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region28 as exempt
cpu0.IDAU_REGION28.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region28 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION28.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region28 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION29.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region29 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION29.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region29
cpu0.IDAU_REGION29.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region29 as exempt
cpu0.IDAU_REGION29.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region29 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION29.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region29 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION30.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region30 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION30.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region30
cpu0.IDAU_REGION30.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region30 as exempt
cpu0.IDAU_REGION30.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region30 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION30.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region30 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION31.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region31 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION31.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region31
cpu0.IDAU_REGION31.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region31 as exempt
cpu0.IDAU_REGION31.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region31 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION31.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region31 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION32.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region32 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION32.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region32
cpu0.IDAU_REGION32.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region32 as exempt
cpu0.IDAU_REGION32.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region32 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION32.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region32 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION33.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region33 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION33.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region33
cpu0.IDAU_REGION33.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region33 as exempt
cpu0.IDAU_REGION33.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region33 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION33.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region33 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION34.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region34 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION34.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region34
cpu0.IDAU_REGION34.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region34 as exempt
cpu0.IDAU_REGION34.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region34 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION34.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region34 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION35.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region35 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION35.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region35
cpu0.IDAU_REGION35.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region35 as exempt
cpu0.IDAU_REGION35.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region35 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION35.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region35 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION36.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region36 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION36.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region36
cpu0.IDAU_REGION36.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region36 as exempt
cpu0.IDAU_REGION36.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region36 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION36.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region36 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION37.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region37 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION37.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region37
cpu0.IDAU_REGION37.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region37 as exempt
cpu0.IDAU_REGION37.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region37 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION37.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region37 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION38.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region38 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION38.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region38
cpu0.IDAU_REGION38.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region38 as exempt
cpu0.IDAU_REGION38.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region38 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION38.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region38 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION39.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region39 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION39.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region39
cpu0.IDAU_REGION39.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region39 as exempt
cpu0.IDAU_REGION39.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region39 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION39.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region39 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION40.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region40 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION40.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region40
cpu0.IDAU_REGION40.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region40 as exempt
cpu0.IDAU_REGION40.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region40 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION40.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region40 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION41.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region41 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION41.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region41
cpu0.IDAU_REGION41.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region41 as exempt
cpu0.IDAU_REGION41.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region41 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION41.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region41 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION42.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region42 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION42.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region42
cpu0.IDAU_REGION42.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region42 as exempt
cpu0.IDAU_REGION42.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region42 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION42.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region42 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION43.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region43 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION43.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region43
cpu0.IDAU_REGION43.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region43 as exempt
cpu0.IDAU_REGION43.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region43 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION43.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region43 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION44.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region44 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION44.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region44
cpu0.IDAU_REGION44.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region44 as exempt
cpu0.IDAU_REGION44.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region44 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION44.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region44 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION45.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region45 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION45.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region45
cpu0.IDAU_REGION45.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region45 as exempt
cpu0.IDAU_REGION45.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region45 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION45.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region45 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION46.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region46 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION46.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region46
cpu0.IDAU_REGION46.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region46 as exempt
cpu0.IDAU_REGION46.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region46 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION46.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region46 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION47.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region47 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION47.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region47
cpu0.IDAU_REGION47.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region47 as exempt
cpu0.IDAU_REGION47.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region47 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION47.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region47 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION48.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region48 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION48.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region48
cpu0.IDAU_REGION48.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region48 as exempt
cpu0.IDAU_REGION48.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region48 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION48.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region48 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION49.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region49 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION49.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region49
cpu0.IDAU_REGION49.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region49 as exempt
cpu0.IDAU_REGION49.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region49 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION49.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region49 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION50.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region50 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION50.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region50
cpu0.IDAU_REGION50.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region50 as exempt
cpu0.IDAU_REGION50.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region50 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION50.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region50 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION51.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region51 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION51.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region51
cpu0.IDAU_REGION51.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region51 as exempt
cpu0.IDAU_REGION51.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region51 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION51.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region51 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION52.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region52 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION52.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region52
cpu0.IDAU_REGION52.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region52 as exempt
cpu0.IDAU_REGION52.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region52 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION52.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region52 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION53.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region53 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION53.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region53
cpu0.IDAU_REGION53.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region53 as exempt
cpu0.IDAU_REGION53.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region53 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION53.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region53 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION54.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region54 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION54.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region54
cpu0.IDAU_REGION54.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region54 as exempt
cpu0.IDAU_REGION54.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region54 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION54.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region54 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION55.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region55 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION55.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region55
cpu0.IDAU_REGION55.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region55 as exempt
cpu0.IDAU_REGION55.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region55 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION55.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region55 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION56.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region56 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION56.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region56
cpu0.IDAU_REGION56.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region56 as exempt
cpu0.IDAU_REGION56.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region56 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION56.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region56 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION57.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region57 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION57.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region57
cpu0.IDAU_REGION57.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region57 as exempt
cpu0.IDAU_REGION57.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region57 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION57.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region57 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION58.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region58 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION58.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region58
cpu0.IDAU_REGION58.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region58 as exempt
cpu0.IDAU_REGION58.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region58 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION58.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region58 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION59.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region59 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION59.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region59
cpu0.IDAU_REGION59.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region59 as exempt
cpu0.IDAU_REGION59.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region59 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION59.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region59 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION60.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region60 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION60.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region60
cpu0.IDAU_REGION60.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region60 as exempt
cpu0.IDAU_REGION60.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region60 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION60.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region60 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION61.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region61 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION61.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region61
cpu0.IDAU_REGION61.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region61 as exempt
cpu0.IDAU_REGION61.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region61 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION61.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region61 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION62.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region62 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION62.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region62
cpu0.IDAU_REGION62.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region62 as exempt
cpu0.IDAU_REGION62.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region62 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION62.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region62 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION63.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region63 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION63.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region63
cpu0.IDAU_REGION63.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region63 as exempt
cpu0.IDAU_REGION63.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region63 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION63.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region63 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION64.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region64 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION64.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region64
cpu0.IDAU_REGION64.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region64 as exempt
cpu0.IDAU_REGION64.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region64 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION64.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region64 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION65.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region65 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION65.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region65
cpu0.IDAU_REGION65.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region65 as exempt
cpu0.IDAU_REGION65.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region65 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION65.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region65 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION66.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region66 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION66.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region66
cpu0.IDAU_REGION66.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region66 as exempt
cpu0.IDAU_REGION66.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region66 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION66.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region66 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION67.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region67 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION67.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region67
cpu0.IDAU_REGION67.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region67 as exempt
cpu0.IDAU_REGION67.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region67 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION67.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region67 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION68.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region68 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION68.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region68
cpu0.IDAU_REGION68.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region68 as exempt
cpu0.IDAU_REGION68.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region68 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION68.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region68 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION69.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region69 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION69.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region69
cpu0.IDAU_REGION69.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region69 as exempt
cpu0.IDAU_REGION69.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region69 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION69.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region69 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION70.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region70 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION70.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region70
cpu0.IDAU_REGION70.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region70 as exempt
cpu0.IDAU_REGION70.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region70 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION70.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region70 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION71.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region71 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION71.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region71
cpu0.IDAU_REGION71.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region71 as exempt
cpu0.IDAU_REGION71.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region71 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION71.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region71 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION72.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region72 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION72.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region72
cpu0.IDAU_REGION72.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region72 as exempt
cpu0.IDAU_REGION72.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region72 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION72.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region72 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION73.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region73 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION73.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region73
cpu0.IDAU_REGION73.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region73 as exempt
cpu0.IDAU_REGION73.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region73 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION73.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region73 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION74.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region74 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION74.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region74
cpu0.IDAU_REGION74.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region74 as exempt
cpu0.IDAU_REGION74.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region74 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION74.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region74 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION75.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region75 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION75.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region75
cpu0.IDAU_REGION75.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region75 as exempt
cpu0.IDAU_REGION75.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region75 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION75.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region75 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION76.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region76 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION76.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region76
cpu0.IDAU_REGION76.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region76 as exempt
cpu0.IDAU_REGION76.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region76 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION76.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region76 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION77.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region77 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION77.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region77
cpu0.IDAU_REGION77.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region77 as exempt
cpu0.IDAU_REGION77.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region77 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION77.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region77 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION78.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region78 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION78.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region78
cpu0.IDAU_REGION78.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region78 as exempt
cpu0.IDAU_REGION78.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region78 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION78.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region78 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION79.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region79 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION79.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region79
cpu0.IDAU_REGION79.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region79 as exempt
cpu0.IDAU_REGION79.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region79 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION79.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region79 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION80.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region80 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION80.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region80
cpu0.IDAU_REGION80.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region80 as exempt
cpu0.IDAU_REGION80.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region80 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION80.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region80 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION81.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region81 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION81.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region81
cpu0.IDAU_REGION81.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region81 as exempt
cpu0.IDAU_REGION81.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region81 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION81.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region81 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION82.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region82 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION82.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region82
cpu0.IDAU_REGION82.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region82 as exempt
cpu0.IDAU_REGION82.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region82 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION82.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region82 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION83.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region83 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION83.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region83
cpu0.IDAU_REGION83.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region83 as exempt
cpu0.IDAU_REGION83.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region83 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION83.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region83 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION84.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region84 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION84.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region84
cpu0.IDAU_REGION84.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region84 as exempt
cpu0.IDAU_REGION84.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region84 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION84.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region84 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION85.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region85 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION85.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region85
cpu0.IDAU_REGION85.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region85 as exempt
cpu0.IDAU_REGION85.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region85 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION85.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region85 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION86.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region86 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION86.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region86
cpu0.IDAU_REGION86.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region86 as exempt
cpu0.IDAU_REGION86.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region86 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION86.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region86 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION87.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region87 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION87.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region87
cpu0.IDAU_REGION87.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region87 as exempt
cpu0.IDAU_REGION87.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region87 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION87.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region87 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION88.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region88 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION88.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region88
cpu0.IDAU_REGION88.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region88 as exempt
cpu0.IDAU_REGION88.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region88 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION88.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region88 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION89.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region89 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION89.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region89
cpu0.IDAU_REGION89.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region89 as exempt
cpu0.IDAU_REGION89.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region89 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION89.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region89 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION90.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region90 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION90.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region90
cpu0.IDAU_REGION90.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region90 as exempt
cpu0.IDAU_REGION90.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region90 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION90.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region90 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION91.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region91 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION91.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region91
cpu0.IDAU_REGION91.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region91 as exempt
cpu0.IDAU_REGION91.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region91 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION91.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region91 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION92.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region92 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION92.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region92
cpu0.IDAU_REGION92.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region92 as exempt
cpu0.IDAU_REGION92.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region92 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION92.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region92 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION93.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region93 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION93.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region93
cpu0.IDAU_REGION93.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region93 as exempt
cpu0.IDAU_REGION93.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region93 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION93.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region93 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION94.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region94 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION94.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region94
cpu0.IDAU_REGION94.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region94 as exempt
cpu0.IDAU_REGION94.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region94 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION94.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region94 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION95.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region95 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION95.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region95
cpu0.IDAU_REGION95.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region95 as exempt
cpu0.IDAU_REGION95.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region95 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION95.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region95 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION96.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region96 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION96.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region96
cpu0.IDAU_REGION96.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region96 as exempt
cpu0.IDAU_REGION96.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region96 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION96.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region96 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION97.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region97 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION97.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region97
cpu0.IDAU_REGION97.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region97 as exempt
cpu0.IDAU_REGION97.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region97 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION97.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region97 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION98.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region98 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION98.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region98
cpu0.IDAU_REGION98.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region98 as exempt
cpu0.IDAU_REGION98.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region98 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION98.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region98 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION99.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region99 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION99.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region99
cpu0.IDAU_REGION99.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region99 as exempt
cpu0.IDAU_REGION99.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region99 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION99.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region99 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION100.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region100 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION100.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region100
cpu0.IDAU_REGION100.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region100 as exempt
cpu0.IDAU_REGION100.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region100 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION100.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region100 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION101.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region101 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION101.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region101
cpu0.IDAU_REGION101.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region101 as exempt
cpu0.IDAU_REGION101.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region101 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION101.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region101 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION102.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region102 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION102.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region102
cpu0.IDAU_REGION102.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region102 as exempt
cpu0.IDAU_REGION102.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region102 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION102.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region102 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION103.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region103 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION103.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region103
cpu0.IDAU_REGION103.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region103 as exempt
cpu0.IDAU_REGION103.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region103 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION103.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region103 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION104.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region104 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION104.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region104
cpu0.IDAU_REGION104.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region104 as exempt
cpu0.IDAU_REGION104.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region104 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION104.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region104 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION105.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region105 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION105.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region105
cpu0.IDAU_REGION105.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region105 as exempt
cpu0.IDAU_REGION105.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region105 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION105.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region105 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION106.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region106 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION106.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region106
cpu0.IDAU_REGION106.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region106 as exempt
cpu0.IDAU_REGION106.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region106 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION106.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region106 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION107.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region107 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION107.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region107
cpu0.IDAU_REGION107.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region107 as exempt
cpu0.IDAU_REGION107.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region107 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION107.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region107 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION108.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region108 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION108.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region108
cpu0.IDAU_REGION108.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region108 as exempt
cpu0.IDAU_REGION108.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region108 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION108.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region108 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION109.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region109 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION109.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region109
cpu0.IDAU_REGION109.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region109 as exempt
cpu0.IDAU_REGION109.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region109 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION109.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region109 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION110.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region110 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION110.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region110
cpu0.IDAU_REGION110.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region110 as exempt
cpu0.IDAU_REGION110.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region110 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION110.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region110 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION111.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region111 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION111.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region111
cpu0.IDAU_REGION111.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region111 as exempt
cpu0.IDAU_REGION111.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region111 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION111.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region111 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION112.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region112 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION112.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region112
cpu0.IDAU_REGION112.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region112 as exempt
cpu0.IDAU_REGION112.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region112 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION112.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region112 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION113.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region113 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION113.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region113
cpu0.IDAU_REGION113.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region113 as exempt
cpu0.IDAU_REGION113.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region113 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION113.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region113 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION114.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region114 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION114.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region114
cpu0.IDAU_REGION114.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region114 as exempt
cpu0.IDAU_REGION114.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region114 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION114.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region114 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION115.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region115 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION115.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region115
cpu0.IDAU_REGION115.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region115 as exempt
cpu0.IDAU_REGION115.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region115 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION115.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region115 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION116.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region116 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION116.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region116
cpu0.IDAU_REGION116.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region116 as exempt
cpu0.IDAU_REGION116.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region116 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION116.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region116 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION117.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region117 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION117.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region117
cpu0.IDAU_REGION117.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region117 as exempt
cpu0.IDAU_REGION117.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region117 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION117.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region117 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION118.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region118 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION118.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region118
cpu0.IDAU_REGION118.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region118 as exempt
cpu0.IDAU_REGION118.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region118 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION118.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region118 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION119.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region119 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION119.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region119
cpu0.IDAU_REGION119.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region119 as exempt
cpu0.IDAU_REGION119.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region119 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION119.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region119 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION120.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region120 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION120.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region120
cpu0.IDAU_REGION120.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region120 as exempt
cpu0.IDAU_REGION120.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region120 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION120.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region120 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION121.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region121 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION121.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region121
cpu0.IDAU_REGION121.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region121 as exempt
cpu0.IDAU_REGION121.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region121 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION121.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region121 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION122.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region122 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION122.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region122
cpu0.IDAU_REGION122.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region122 as exempt
cpu0.IDAU_REGION122.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region122 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION122.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region122 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION123.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region123 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION123.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region123
cpu0.IDAU_REGION123.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region123 as exempt
cpu0.IDAU_REGION123.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region123 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION123.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region123 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION124.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region124 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION124.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region124
cpu0.IDAU_REGION124.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region124 as exempt
cpu0.IDAU_REGION124.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region124 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION124.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region124 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION125.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region125 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION125.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region125
cpu0.IDAU_REGION125.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region125 as exempt
cpu0.IDAU_REGION125.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region125 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION125.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region125 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION126.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region126 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION126.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region126
cpu0.IDAU_REGION126.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region126 as exempt
cpu0.IDAU_REGION126.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region126 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION126.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region126 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION127.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region127 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION127.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region127
cpu0.IDAU_REGION127.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region127 as exempt
cpu0.IDAU_REGION127.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region127 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION127.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region127 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION128.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region128 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION128.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region128
cpu0.IDAU_REGION128.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region128 as exempt
cpu0.IDAU_REGION128.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region128 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION128.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region128 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION129.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region129 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION129.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region129
cpu0.IDAU_REGION129.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region129 as exempt
cpu0.IDAU_REGION129.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region129 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION129.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region129 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION130.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region130 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION130.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region130
cpu0.IDAU_REGION130.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region130 as exempt
cpu0.IDAU_REGION130.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region130 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION130.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region130 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION131.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region131 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION131.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region131
cpu0.IDAU_REGION131.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region131 as exempt
cpu0.IDAU_REGION131.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region131 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION131.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region131 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION132.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region132 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION132.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region132
cpu0.IDAU_REGION132.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region132 as exempt
cpu0.IDAU_REGION132.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region132 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION132.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region132 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION133.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region133 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION133.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region133
cpu0.IDAU_REGION133.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region133 as exempt
cpu0.IDAU_REGION133.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region133 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION133.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region133 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION134.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region134 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION134.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region134
cpu0.IDAU_REGION134.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region134 as exempt
cpu0.IDAU_REGION134.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region134 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION134.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region134 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION135.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region135 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION135.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region135
cpu0.IDAU_REGION135.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region135 as exempt
cpu0.IDAU_REGION135.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region135 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION135.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region135 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION136.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region136 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION136.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region136
cpu0.IDAU_REGION136.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region136 as exempt
cpu0.IDAU_REGION136.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region136 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION136.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region136 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION137.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region137 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION137.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region137
cpu0.IDAU_REGION137.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region137 as exempt
cpu0.IDAU_REGION137.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region137 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION137.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region137 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION138.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region138 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION138.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region138
cpu0.IDAU_REGION138.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region138 as exempt
cpu0.IDAU_REGION138.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region138 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION138.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region138 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION139.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region139 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION139.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region139
cpu0.IDAU_REGION139.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region139 as exempt
cpu0.IDAU_REGION139.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region139 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION139.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region139 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION140.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region140 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION140.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region140
cpu0.IDAU_REGION140.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region140 as exempt
cpu0.IDAU_REGION140.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region140 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION140.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region140 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION141.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region141 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION141.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region141
cpu0.IDAU_REGION141.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region141 as exempt
cpu0.IDAU_REGION141.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region141 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION141.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region141 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION142.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region142 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION142.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region142
cpu0.IDAU_REGION142.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region142 as exempt
cpu0.IDAU_REGION142.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region142 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION142.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region142 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION143.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region143 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION143.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region143
cpu0.IDAU_REGION143.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region143 as exempt
cpu0.IDAU_REGION143.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region143 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION143.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region143 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION144.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region144 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION144.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region144
cpu0.IDAU_REGION144.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region144 as exempt
cpu0.IDAU_REGION144.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region144 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION144.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region144 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION145.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region145 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION145.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region145
cpu0.IDAU_REGION145.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region145 as exempt
cpu0.IDAU_REGION145.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region145 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION145.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region145 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION146.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region146 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION146.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region146
cpu0.IDAU_REGION146.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region146 as exempt
cpu0.IDAU_REGION146.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region146 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION146.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region146 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION147.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region147 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION147.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region147
cpu0.IDAU_REGION147.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region147 as exempt
cpu0.IDAU_REGION147.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region147 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION147.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region147 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION148.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region148 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION148.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region148
cpu0.IDAU_REGION148.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region148 as exempt
cpu0.IDAU_REGION148.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region148 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION148.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region148 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION149.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region149 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION149.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region149
cpu0.IDAU_REGION149.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region149 as exempt
cpu0.IDAU_REGION149.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region149 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION149.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region149 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION150.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region150 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION150.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region150
cpu0.IDAU_REGION150.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region150 as exempt
cpu0.IDAU_REGION150.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region150 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION150.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region150 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION151.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region151 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION151.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region151
cpu0.IDAU_REGION151.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region151 as exempt
cpu0.IDAU_REGION151.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region151 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION151.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region151 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION152.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region152 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION152.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region152
cpu0.IDAU_REGION152.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region152 as exempt
cpu0.IDAU_REGION152.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region152 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION152.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region152 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION153.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region153 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION153.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region153
cpu0.IDAU_REGION153.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region153 as exempt
cpu0.IDAU_REGION153.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region153 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION153.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region153 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION154.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region154 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION154.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region154
cpu0.IDAU_REGION154.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region154 as exempt
cpu0.IDAU_REGION154.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region154 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION154.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region154 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION155.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region155 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION155.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region155
cpu0.IDAU_REGION155.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region155 as exempt
cpu0.IDAU_REGION155.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region155 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION155.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region155 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION156.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region156 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION156.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region156
cpu0.IDAU_REGION156.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region156 as exempt
cpu0.IDAU_REGION156.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region156 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION156.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region156 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION157.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region157 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION157.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region157
cpu0.IDAU_REGION157.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region157 as exempt
cpu0.IDAU_REGION157.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region157 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION157.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region157 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION158.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region158 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION158.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region158
cpu0.IDAU_REGION158.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region158 as exempt
cpu0.IDAU_REGION158.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region158 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION158.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region158 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION159.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region159 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION159.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region159
cpu0.IDAU_REGION159.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region159 as exempt
cpu0.IDAU_REGION159.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region159 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION159.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region159 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION160.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region160 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION160.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region160
cpu0.IDAU_REGION160.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region160 as exempt
cpu0.IDAU_REGION160.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region160 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION160.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region160 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION161.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region161 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION161.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region161
cpu0.IDAU_REGION161.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region161 as exempt
cpu0.IDAU_REGION161.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region161 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION161.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region161 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION162.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region162 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION162.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region162
cpu0.IDAU_REGION162.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region162 as exempt
cpu0.IDAU_REGION162.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region162 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION162.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region162 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION163.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region163 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION163.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region163
cpu0.IDAU_REGION163.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region163 as exempt
cpu0.IDAU_REGION163.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region163 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION163.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region163 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION164.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region164 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION164.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region164
cpu0.IDAU_REGION164.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region164 as exempt
cpu0.IDAU_REGION164.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region164 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION164.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region164 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION165.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region165 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION165.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region165
cpu0.IDAU_REGION165.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region165 as exempt
cpu0.IDAU_REGION165.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region165 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION165.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region165 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION166.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region166 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION166.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region166
cpu0.IDAU_REGION166.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region166 as exempt
cpu0.IDAU_REGION166.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region166 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION166.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region166 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION167.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region167 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION167.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region167
cpu0.IDAU_REGION167.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region167 as exempt
cpu0.IDAU_REGION167.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region167 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION167.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region167 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION168.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region168 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION168.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region168
cpu0.IDAU_REGION168.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region168 as exempt
cpu0.IDAU_REGION168.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region168 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION168.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region168 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION169.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region169 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION169.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region169
cpu0.IDAU_REGION169.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region169 as exempt
cpu0.IDAU_REGION169.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region169 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION169.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region169 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION170.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region170 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION170.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region170
cpu0.IDAU_REGION170.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region170 as exempt
cpu0.IDAU_REGION170.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region170 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION170.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region170 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION171.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region171 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION171.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region171
cpu0.IDAU_REGION171.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region171 as exempt
cpu0.IDAU_REGION171.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region171 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION171.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region171 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION172.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region172 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION172.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region172
cpu0.IDAU_REGION172.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region172 as exempt
cpu0.IDAU_REGION172.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region172 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION172.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region172 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION173.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region173 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION173.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region173
cpu0.IDAU_REGION173.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region173 as exempt
cpu0.IDAU_REGION173.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region173 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION173.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region173 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION174.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region174 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION174.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region174
cpu0.IDAU_REGION174.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region174 as exempt
cpu0.IDAU_REGION174.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region174 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION174.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region174 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION175.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region175 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION175.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region175
cpu0.IDAU_REGION175.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region175 as exempt
cpu0.IDAU_REGION175.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region175 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION175.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region175 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION176.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region176 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION176.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region176
cpu0.IDAU_REGION176.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region176 as exempt
cpu0.IDAU_REGION176.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region176 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION176.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region176 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION177.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region177 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION177.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region177
cpu0.IDAU_REGION177.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region177 as exempt
cpu0.IDAU_REGION177.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region177 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION177.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region177 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION178.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region178 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION178.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region178
cpu0.IDAU_REGION178.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region178 as exempt
cpu0.IDAU_REGION178.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region178 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION178.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region178 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION179.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region179 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION179.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region179
cpu0.IDAU_REGION179.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region179 as exempt
cpu0.IDAU_REGION179.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region179 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION179.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region179 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION180.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region180 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION180.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region180
cpu0.IDAU_REGION180.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region180 as exempt
cpu0.IDAU_REGION180.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region180 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION180.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region180 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION181.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region181 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION181.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region181
cpu0.IDAU_REGION181.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region181 as exempt
cpu0.IDAU_REGION181.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region181 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION181.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region181 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION182.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region182 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION182.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region182
cpu0.IDAU_REGION182.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region182 as exempt
cpu0.IDAU_REGION182.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region182 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION182.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region182 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION183.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region183 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION183.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region183
cpu0.IDAU_REGION183.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region183 as exempt
cpu0.IDAU_REGION183.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region183 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION183.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region183 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION184.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region184 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION184.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region184
cpu0.IDAU_REGION184.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region184 as exempt
cpu0.IDAU_REGION184.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region184 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION184.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region184 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION185.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region185 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION185.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region185
cpu0.IDAU_REGION185.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region185 as exempt
cpu0.IDAU_REGION185.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region185 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION185.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region185 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION186.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region186 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION186.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region186
cpu0.IDAU_REGION186.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region186 as exempt
cpu0.IDAU_REGION186.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region186 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION186.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region186 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION187.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region187 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION187.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region187
cpu0.IDAU_REGION187.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region187 as exempt
cpu0.IDAU_REGION187.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region187 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION187.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region187 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION188.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region188 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION188.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region188
cpu0.IDAU_REGION188.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region188 as exempt
cpu0.IDAU_REGION188.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region188 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION188.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region188 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION189.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region189 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION189.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region189
cpu0.IDAU_REGION189.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region189 as exempt
cpu0.IDAU_REGION189.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region189 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION189.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region189 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION190.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region190 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION190.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region190
cpu0.IDAU_REGION190.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region190 as exempt
cpu0.IDAU_REGION190.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region190 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION190.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region190 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION191.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region191 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION191.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region191
cpu0.IDAU_REGION191.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region191 as exempt
cpu0.IDAU_REGION191.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region191 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION191.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region191 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION192.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region192 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION192.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region192
cpu0.IDAU_REGION192.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region192 as exempt
cpu0.IDAU_REGION192.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region192 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION192.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region192 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION193.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region193 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION193.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region193
cpu0.IDAU_REGION193.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region193 as exempt
cpu0.IDAU_REGION193.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region193 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION193.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region193 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION194.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region194 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION194.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region194
cpu0.IDAU_REGION194.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region194 as exempt
cpu0.IDAU_REGION194.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region194 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION194.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region194 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION195.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region195 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION195.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region195
cpu0.IDAU_REGION195.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region195 as exempt
cpu0.IDAU_REGION195.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region195 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION195.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region195 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION196.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region196 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION196.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region196
cpu0.IDAU_REGION196.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region196 as exempt
cpu0.IDAU_REGION196.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region196 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION196.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region196 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION197.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region197 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION197.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region197
cpu0.IDAU_REGION197.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region197 as exempt
cpu0.IDAU_REGION197.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region197 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION197.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region197 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION198.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region198 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION198.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region198
cpu0.IDAU_REGION198.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region198 as exempt
cpu0.IDAU_REGION198.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region198 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION198.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region198 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION199.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region199 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION199.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region199
cpu0.IDAU_REGION199.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region199 as exempt
cpu0.IDAU_REGION199.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region199 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION199.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region199 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION200.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region200 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION200.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region200
cpu0.IDAU_REGION200.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region200 as exempt
cpu0.IDAU_REGION200.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region200 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION200.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region200 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION201.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region201 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION201.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region201
cpu0.IDAU_REGION201.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region201 as exempt
cpu0.IDAU_REGION201.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region201 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION201.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region201 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION202.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region202 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION202.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region202
cpu0.IDAU_REGION202.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region202 as exempt
cpu0.IDAU_REGION202.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region202 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION202.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region202 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION203.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region203 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION203.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region203
cpu0.IDAU_REGION203.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region203 as exempt
cpu0.IDAU_REGION203.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region203 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION203.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region203 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION204.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region204 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION204.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region204
cpu0.IDAU_REGION204.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region204 as exempt
cpu0.IDAU_REGION204.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region204 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION204.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region204 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION205.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region205 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION205.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region205
cpu0.IDAU_REGION205.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region205 as exempt
cpu0.IDAU_REGION205.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region205 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION205.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region205 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION206.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region206 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION206.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region206
cpu0.IDAU_REGION206.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region206 as exempt
cpu0.IDAU_REGION206.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region206 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION206.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region206 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION207.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region207 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION207.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region207
cpu0.IDAU_REGION207.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region207 as exempt
cpu0.IDAU_REGION207.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region207 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION207.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region207 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION208.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region208 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION208.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region208
cpu0.IDAU_REGION208.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region208 as exempt
cpu0.IDAU_REGION208.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region208 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION208.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region208 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION209.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region209 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION209.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region209
cpu0.IDAU_REGION209.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region209 as exempt
cpu0.IDAU_REGION209.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region209 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION209.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region209 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION210.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region210 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION210.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region210
cpu0.IDAU_REGION210.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region210 as exempt
cpu0.IDAU_REGION210.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region210 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION210.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region210 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION211.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region211 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION211.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region211
cpu0.IDAU_REGION211.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region211 as exempt
cpu0.IDAU_REGION211.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region211 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION211.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region211 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION212.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region212 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION212.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region212
cpu0.IDAU_REGION212.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region212 as exempt
cpu0.IDAU_REGION212.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region212 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION212.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region212 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION213.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region213 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION213.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region213
cpu0.IDAU_REGION213.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region213 as exempt
cpu0.IDAU_REGION213.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region213 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION213.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region213 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION214.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region214 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION214.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region214
cpu0.IDAU_REGION214.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region214 as exempt
cpu0.IDAU_REGION214.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region214 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION214.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region214 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION215.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region215 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION215.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region215
cpu0.IDAU_REGION215.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region215 as exempt
cpu0.IDAU_REGION215.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region215 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION215.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region215 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION216.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region216 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION216.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region216
cpu0.IDAU_REGION216.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region216 as exempt
cpu0.IDAU_REGION216.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region216 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION216.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region216 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION217.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region217 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION217.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region217
cpu0.IDAU_REGION217.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region217 as exempt
cpu0.IDAU_REGION217.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region217 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION217.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region217 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION218.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region218 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION218.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region218
cpu0.IDAU_REGION218.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region218 as exempt
cpu0.IDAU_REGION218.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region218 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION218.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region218 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION219.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region219 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION219.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region219
cpu0.IDAU_REGION219.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region219 as exempt
cpu0.IDAU_REGION219.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region219 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION219.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region219 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION220.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region220 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION220.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region220
cpu0.IDAU_REGION220.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region220 as exempt
cpu0.IDAU_REGION220.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region220 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION220.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region220 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION221.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region221 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION221.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region221
cpu0.IDAU_REGION221.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region221 as exempt
cpu0.IDAU_REGION221.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region221 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION221.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region221 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION222.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region222 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION222.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region222
cpu0.IDAU_REGION222.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region222 as exempt
cpu0.IDAU_REGION222.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region222 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION222.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region222 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION223.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region223 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION223.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region223
cpu0.IDAU_REGION223.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region223 as exempt
cpu0.IDAU_REGION223.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region223 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION223.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region223 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION224.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region224 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION224.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region224
cpu0.IDAU_REGION224.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region224 as exempt
cpu0.IDAU_REGION224.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region224 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION224.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region224 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION225.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region225 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION225.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region225
cpu0.IDAU_REGION225.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region225 as exempt
cpu0.IDAU_REGION225.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region225 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION225.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region225 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION226.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region226 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION226.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region226
cpu0.IDAU_REGION226.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region226 as exempt
cpu0.IDAU_REGION226.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region226 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION226.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region226 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION227.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region227 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION227.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region227
cpu0.IDAU_REGION227.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region227 as exempt
cpu0.IDAU_REGION227.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region227 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION227.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region227 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION228.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region228 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION228.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region228
cpu0.IDAU_REGION228.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region228 as exempt
cpu0.IDAU_REGION228.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region228 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION228.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region228 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION229.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region229 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION229.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region229
cpu0.IDAU_REGION229.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region229 as exempt
cpu0.IDAU_REGION229.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region229 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION229.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region229 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION230.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region230 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION230.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region230
cpu0.IDAU_REGION230.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region230 as exempt
cpu0.IDAU_REGION230.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region230 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION230.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region230 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION231.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region231 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION231.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region231
cpu0.IDAU_REGION231.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region231 as exempt
cpu0.IDAU_REGION231.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region231 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION231.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region231 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION232.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region232 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION232.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region232
cpu0.IDAU_REGION232.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region232 as exempt
cpu0.IDAU_REGION232.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region232 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION232.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region232 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION233.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region233 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION233.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region233
cpu0.IDAU_REGION233.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region233 as exempt
cpu0.IDAU_REGION233.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region233 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION233.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region233 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION234.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region234 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION234.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region234
cpu0.IDAU_REGION234.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region234 as exempt
cpu0.IDAU_REGION234.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region234 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION234.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region234 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION235.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region235 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION235.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region235
cpu0.IDAU_REGION235.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region235 as exempt
cpu0.IDAU_REGION235.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region235 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION235.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region235 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION236.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region236 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION236.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region236
cpu0.IDAU_REGION236.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region236 as exempt
cpu0.IDAU_REGION236.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region236 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION236.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region236 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION237.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region237 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION237.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region237
cpu0.IDAU_REGION237.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region237 as exempt
cpu0.IDAU_REGION237.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region237 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION237.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region237 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION238.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region238 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION238.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region238
cpu0.IDAU_REGION238.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region238 as exempt
cpu0.IDAU_REGION238.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region238 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION238.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region238 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION239.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region239 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION239.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region239
cpu0.IDAU_REGION239.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region239 as exempt
cpu0.IDAU_REGION239.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region239 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION239.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region239 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION240.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region240 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION240.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region240
cpu0.IDAU_REGION240.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region240 as exempt
cpu0.IDAU_REGION240.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region240 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION240.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region240 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION241.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region241 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION241.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region241
cpu0.IDAU_REGION241.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region241 as exempt
cpu0.IDAU_REGION241.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region241 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION241.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region241 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION242.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region242 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION242.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region242
cpu0.IDAU_REGION242.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region242 as exempt
cpu0.IDAU_REGION242.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region242 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION242.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region242 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION243.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region243 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION243.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region243
cpu0.IDAU_REGION243.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region243 as exempt
cpu0.IDAU_REGION243.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region243 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION243.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region243 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION244.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region244 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION244.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region244
cpu0.IDAU_REGION244.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region244 as exempt
cpu0.IDAU_REGION244.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region244 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION244.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region244 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION245.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region245 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION245.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region245
cpu0.IDAU_REGION245.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region245 as exempt
cpu0.IDAU_REGION245.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region245 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION245.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region245 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION246.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region246 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION246.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region246
cpu0.IDAU_REGION246.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region246 as exempt
cpu0.IDAU_REGION246.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region246 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION246.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region246 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION247.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region247 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION247.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region247
cpu0.IDAU_REGION247.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region247 as exempt
cpu0.IDAU_REGION247.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region247 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION247.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region247 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION248.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region248 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION248.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region248
cpu0.IDAU_REGION248.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region248 as exempt
cpu0.IDAU_REGION248.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region248 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION248.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region248 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION249.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region249 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION249.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region249
cpu0.IDAU_REGION249.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region249 as exempt
cpu0.IDAU_REGION249.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region249 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION249.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region249 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION250.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region250 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION250.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region250
cpu0.IDAU_REGION250.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region250 as exempt
cpu0.IDAU_REGION250.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region250 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION250.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region250 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION251.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region251 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION251.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region251
cpu0.IDAU_REGION251.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region251 as exempt
cpu0.IDAU_REGION251.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region251 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION251.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region251 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION252.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region252 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION252.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region252
cpu0.IDAU_REGION252.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region252 as exempt
cpu0.IDAU_REGION252.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region252 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION252.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region252 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION253.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region253 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION253.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region253
cpu0.IDAU_REGION253.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region253 as exempt
cpu0.IDAU_REGION253.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region253 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION253.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region253 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION254.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region254 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION254.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region254
cpu0.IDAU_REGION254.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region254 as exempt
cpu0.IDAU_REGION254.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region254 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION254.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region254 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION255.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region255 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu0.IDAU_REGION255.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region255
cpu0.IDAU_REGION255.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region255 as exempt
cpu0.IDAU_REGION255.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region255 : [0x0..0xFFFFFFFF]
cpu0.IDAU_REGION255.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region255 : [0x0..0xFFFFFFFF]
cpu0.CPUID=0x0 # (int , init-time) default = '0x0' : Set SCS CPUID Base Register. If set to zero, a default CPUID is used. : [0x0..0xFFFFFFFF]
cpu0.supports_unprivileged=1 # (bool , init-time) default = '1' : Enable support for Unprivileged/Privileged Extension
cpu0.SYST=0x2 # (int , init-time) default = '0x2' : Include SysTick timer functionality (0=Absent, 1=Secure only, 2=Secure and NS) : [0x0..0x2]
cpu0.baseline=0 # (bool , init-time) default = '1' : When in v8-M mode, use the baseline profile (if false, use mainline)
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPSPRESENT=0xFFFF # (int , init-time) default = '0xFFFF' : Bit N means external coprocessor N (CP15:CP0) is accessible in Secure state : [0x0..0xFFFF]
cpu0.CPNSPRESENT=0xFFFF # (int , init-time) default = '0xFFFF' : Bit N means external coprocessor N (CP15:CP0) is accessible in Non-Secure state : [0x0..0xFFFF]
cpu0.WIC=1 # (bool , init-time) default = '1' : Include support for WIC-mode deep sleep
cpu0.IRQDIS0=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+0] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS1=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+32] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS2=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+64] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS3=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+96] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS4=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+128] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS5=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+160] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS6=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+192] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS7=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+224] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS8=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+256] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS9=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+288] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS10=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+320] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS11=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+352] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS12=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+384] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS13=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+416] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS14=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+448] : [0x0..0xFFFFFFFF]
cpu0.IRQDIS15=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+480] : [0x0..0xFFFFFFFF]
cpu0.NVIC_ITNS0="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS1="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS2="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS3="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS4="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS5="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS6="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS7="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS8="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS9="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS10="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS11="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS12="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS13="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS14="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.NVIC_ITNS15="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu0.cpu_can_access_debug_regs=1 # (bool , init-time) default = '1' : The DWT, BPU, ROM table, DCB, and the SHCSR and DFSR registers access from the processor
cpu0.stack_limit_check=0x3 # (int , init-time) default = '0x3' : Support Stack limit Check on Load instructions (0:Only v6M, 1:Exclusives from ARMv7-M, 2:Semaphores and atomics from ARMv8-A/R, 3:Both #1 and #2 : [0x0..0x3]
cpu0.stack_limit_check_optimization=1 # (bool , init-time) default = '1' : Stack limit check optimization (0: limit check done for each word on the stack, 1: limit check done only on stack pointer
cpu0.sequential_security_transitions=0x1 # (int , init-time) default = '0x1' : Allow transition of security state in sequential instruction fetches that cross from non-secure to secure memory with SG instruction 0: never, 1: always, 2: 32-bit instrs, 3: ISB. : [0x0..0x3]
cpu0.bp_on_2nd_halfword=1 # (bool , init-time) default = '1' : Respect DWT/BPU breakpoint-hit on 2nd halfword of 32-bit instruction
cpu0.condition_flags_reset=0x0 # (int , init-time) default = '0x0' : Reset Value of condition flags in APSR : [0x0..0xF]
cpu0.ID_ISAR0.coproc_instrs=0x4 # (int , init-time) default = '0x4' : Supported Coprocessor instructions 0: None 1: CDP, LDC, MCR, MRC, and STC instructions 2: As for 1, and CDP2, LDC2, MCR2, MRC2, and STC2 instructions 3: As for 2, and MCRR and MRRC instructions 4: As for 2, and MCRR and MRRC instructions : [0x0..0x4]
cpu0.ID_ISAR1.interwork_instrs=0x3 # (int , init-time) default = '0x3' : level of support for Interworking instructions : [0x0..0x3]
cpu0.ID_ISAR1.extend_instrs=0x2 # (int , init-time) default = '0x2' : level of support for extend instructions, under the control of support_dsp_ext : [0x0..0x2]
cpu0.ID_ISAR2.multU_instrs=0x2 # (int , init-time) default = '0x2' : level of support for advanced unsigned Multiply instructions, under the control of support_dsp_ext : [0x0..0x2]
cpu0.ID_ISAR2.multS_instrs=0x3 # (int , init-time) default = '0x3' : level of support for advanced signed Multiply instructions, under the control of support_dsp_ext : [0x0..0x3]
cpu0.ID_ISAR3.SIMD_instrs=0x3 # (int , init-time) default = '0x3' : level of support for SIMD instructions, under the control of support_dsp_ext : [0x0..0x3]
cpu0.ID_ISAR3.saturate_instrs=0x1 # (int , init-time) default = '0x1' : level of support for saturate instructions, under the control of support_dsp_ext : [0x0..0x1]
cpu0.ID_ISAR3.synchprim_instrs=0x2 # (int , init-time) default = '0x2' : level of support for synchronization primitives ID_ISAR3 : [0x0..0x2]
cpu0.ID_ISAR4.unpriv_instrs=0x2 # (int , init-time) default = '0x2' : supported unprivileged instructions 0: None 1: LDRBT, LDRT, STRBT, and STRT instructions 2: As for 1, and LDRHT, LDRSBT, LDRSHT, and STRHT instructions : [0x0..0x2]
cpu0.ID_ISAR4.withshifts_instrs=0x4 # (int , init-time) default = '0x4' : level of support for instructions with shifts : [0x0..0x4]
cpu0.ID_ISAR4.synchPrim_instrs_frac=0x0 # (int , init-time) default = '0x0' : level of support for synchronization primitives ID_ISAR4 : [0x0..0x3]
cpu0.MVFR1.fp_hpfp=0x2 # (int , init-time) default = '0x2' : FP extension implements half-precision and double-precision floating-point conversion instructions; 0x1: half-precision and single precision 1: As for 0x1, and also supports conversion between half-precision and double-precision : [0x1..0x2]
cpu0.tail_chain=1 # (bool , init-time) default = '1' : Enable tail-chaining optimisation
cpu0.late_arrival=1 # (bool , init-time) default = '1' : Enable late arrival support
cpu0.IOP=0 # (bool , init-time) default = '0' : Send all d-side transactions to the port, io_port_out. Transactions which do not match should be returned to the port, io_port_in
cpu0.ID_MMFR0.Auxiliary_registers=1 # (bool , init-time) default = '1' : Auxiliary registers bits in ID_MMFR0, indicate the support for Auxiliary registers
cpu0.ID_MMFR0.Outermost_shareability=0x0 # (int , init-time) default = '0x0' : Outermost shareability bits in ID_MMFR0, indicate the outermost shareability domain implemented : [0x0..0xF]
cpu0.AIRCR.PRIS_writable=1 # (bool , init-time) default = '1' : Is AIRCR.BFHFNMINS bit[13] writeable
cpu0.AIRCR.BFHFNMINS_writable=1 # (bool , init-time) default = '1' : Is AIRCR.PRIS bit[14] writeable
cpu0.AIRCR.VECTCLRACTIVE_changes_mode=1 # (bool , init-time) default = '1' : Asserting AIRCR.VECTCLRACTIVE clears IPSR and any active exceptions. The mode is also changed to thread if this flag is true. Ignored for v8-M
cpu0.vector_fetch_as_wpt_event=0 # (bool , init-time) default = '0' : Watchpoint on exception vector fetch
cpu0.vector_fetch_on_iside=1 # (bool , init-time) default = '1' : Perform vector fetch on I-side
cpu0.CCR.BP=1 # (bool , init-time) default = '1' : Reset value of the Configuration and Control Register's branch prediction enable bit
cpu0.CCR.BP_writable=0 # (bool , init-time) default = '0' : Whether it is possible to modify the Configuration and Control Register's branch prediction enable bit
cpu0.ignore-SCR.SLEEPONEXIT=0 # (bool , init-time) default = '0' : Never sleep on exit from handler to thread mode.
cpu0.register_reset_data=0x0 # (int , init-time) default = '0x0' : Data used to fill register bits when they become UNKNOWN at reset. : [0x0..0xFFFFFFFF]
cpu0.write_unknown_regs_at_exception=0 # (bool , init-time) default = '0' : Do we write registers when they become UNKNOWN at exception or exception-return.
cpu0.unknown_regs_at_exception_value=0x0 # (int , init-time) default = '0x0' : Data used to fill registers when they become UNKNOWN at exception and exception-return. : [0x0..0xFFFFFFFF]
cpu0.ignore_unpred_SBZSBO=0 # (bool , init-time) default = '0' : Use smaller decoder does not UNDEF some unpredicable SBZ/SBO fields.
cpu0.ignore_unpred_ZeroRegistersInList=0 # (bool , init-time) default = '0' : VLDM,VSTM,STM,LDM with no registers NOP instead of UNDEF.
cpu0.unpred_msr_psr_with_zero_mask_is_nop=0 # (bool , init-time) default = '0' : If true, MSR to *PSR with a zero mask does nothing.
cpu0.unpred_msr_psr_with_one_mask_and_nodsp_is_nop=1 # (bool , init-time) default = '1' : If true, MSR to *PSR with a one mask and no DSP does nothing.
cpu0.abort_unaligned_nonNormal=1 # (bool , init-time) default = '1' : If true, UNPREDICTABLE accesses of device and strongly ordered memory abort; if false they are allowed.
cpu0.has_ahbp=1 # (bool , init-time) default = '1' : Are Vendor-Sys accesses sent to a separate bus (AHBP on CM7).
cpu0.has_separate_etm_reset=0 # (bool , init-time) default = '0' : If true, signal 'etmreset' resets the core, else the core power-on-reset does
cpu0.share_fault_address_reg=0 # (bool , init-time) default = '0' : If true, Fault Address Register is shared
cpu0.clear_non_secure_EXC_RETURN.ES_on_tailchain=1 # (bool , init-time) default = '1' : Clear EXC_RETURN.ES in LR value on entry to a tail-chained exception when returning from Non-secure state
cpu1.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu1.vfp-enable_at_reset=0 # (bool , init-time) default = '0' : Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: ARM recommends going though the implementation's suggested VFP power-up sequence!
cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu1.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
cpu1.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
cpu1.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
cpu1.semihosting-heap_limit=0x10700000 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
cpu1.semihosting-stack_base=0x10700000 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
cpu1.semihosting-stack_limit=0x10800000 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
cpu1.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
cpu1.MPU_TYPE_S.DREGION=0x10 # (int , init-time) default = '0x10' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x100]
cpu1.MPU_TYPE_NS.DREGION=0x10 # (int , init-time) default = '0x10' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x100]
cpu1.ignore_out_of_range_RNR_write=0 # (bool , init-time) default = '0' : If an MPU_RNR.REGION write is out of range, ignore it ; if false, MPU_RNR values wrap
cpu1.ignore_RNR_top_nibble=0 # (bool , init-time) default = '0' : If set, only the bottom four bits of MPU_RNR.REGION are used
cpu1.ITM=1 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included (unless baseline)
cpu1.DWT_TRACE=1 # (bool , init-time) default = '1' : Support for DWT trace. false : No DWT trace included, true: DWT trace included (unless ITM=0, or baseline)
cpu1.number_of_itm_stimulus_ports=0x20 # (int , init-time) default = '0x20' : The number of ITM stimulus ports : [0x8..0x100]
cpu1.LVL_WIDTH=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority (baseline has 2) : [0x3..0x8]
cpu1.AIRCR.ENDIANNESS=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu1.BB_PRESENT=0 # (bool , init-time) default = '0' : Enable bitbanding
cpu1.INITVTOR_S=0x0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu1.INITVTOR_NS=0x0 # (int , init-time) default = '0x0' : Non-secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu1.VTOR_MASK=0xFFFFFF80 # (int , init-time) default = '0xFFFFFF80' : VTOR write mask : [0x0..0xFFFFFF80]
cpu1.min_sync_level=0x0 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu1.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu1.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu1.MVFR0.Double-precision=1 # (bool , init-time) default = '1' : Support 8-byte floats
cpu1.scheduler_mode=0x0 # (int , init-time) default = '0x0' : Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare) : [0x0..0x3]
cpu1.has_writebuffer=0 # (bool , init-time) default = '0' : Implement write accesses buffering before L1 cache. May affect ext_abort behaviour.
cpu1.exercise_strex_fail=0 # (bool , init-time) default = '0' : Reject a pseudo-random majority of exclusive store instructions
cpu1.dcache-size=0x8000 # (int , init-time) default = '0x8000' : L1 D-cache size in bytes : [0x0..0x100000]
cpu1.dcache-ways=0x4 # (int , init-time) default = '0x4' : L1 D-cache ways (sets are implicit from size) : [0x1..0x40]
cpu1.icache-size=0x8000 # (int , init-time) default = '0x8000' : L1 I-cache size in bytes : [0x0..0x100000]
cpu1.icache-ways=0x2 # (int , init-time) default = '0x2' : L1 I-cache ways (sets are implicit from size) : [0x1..0x40]
cpu1.itcm_size=0x100 # (int , init-time) default = '0x100' : ITCM size in KB : [0x0..0x4000]
cpu1.dtcm_size=0x100 # (int , init-time) default = '0x100' : DTCM size in KB : [0x0..0x4000]
cpu1.itcm_enable=0 # (bool , init-time) default = '0' : Enable ITCM at reset
cpu1.dtcm_enable=0 # (bool , init-time) default = '0' : Enable DTCM at reset
cpu1.duplicate_CADI_TCM_writes=0 # (bool , init-time) default = '0' : CADI writes to TCMs are also sent to downstream memory at same addresses (for validation platforms)
cpu1.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation
cpu1.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation
cpu1.dcache-invalidate-ns-cleans-s=0 # (bool , init-time) default = '0' : Whether V8M DCI* in non-secure should clean-and-invalidate secure cache contents.
cpu1.rd_s_bus_err_behave=0x1 # (int , init-time) default = '0x1' : External read aborts in secure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO. : [0x0..0x3]
cpu1.wr_s_bus_err_behave=0x3 # (int , init-time) default = '0x3' : External write aborts in secure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO. : [0x0..0x3]
cpu1.rd_ns_bus_err_behave=0x1 # (int , init-time) default = '0x1' : External read aborts in nonsecure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO. : [0x0..0x3]
cpu1.wr_ns_bus_err_behave=0x3 # (int , init-time) default = '0x3' : External write aborts in nonsecure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO. : [0x0..0x3]
cpu1.VTOR_S=1 # (bool , init-time) default = '1' : Secure Vector Table Offset Register is writeable
cpu1.VTOR_NS=1 # (bool , init-time) default = '1' : NonSecure Vector Table Offset Register is writeable
cpu1.ID_DFR0.Debug_Model_M_profile=1 # (bool , init-time) default = '1' : Set whether debug extensions are implemented
cpu1.FP_CTRL.NUM_CODE=0x8 # (int , init-time) default = '0x8' : Number of breakpoint unit comparators implemented (limited to 15 in V6M or baseline) : [0x0..0x7F]
cpu1.DWT_CTRL.NUMCOMP=0x4 # (int , init-time) default = '0x4' : Number of watchpoint unit comparators implemented : [0x0..0xF]
cpu1.DWT_CTRL.NOCYCCNT=0 # (bool , init-time) default = '0' : DWT cycle-counter not present (v8M_bl/v6M never have one).
cpu1.DWT_CTRL.NOPRFCNT=0 # (bool , init-time) default = '0' : DWT performance-counters not present (v8M_bl/v6M never have them).
cpu1.FP_REMAP.RMPSPT=1 # (bool , init-time) default = '1' : FPB supports remapping (ignored if baseline or SECEXT)
cpu1.FP_CTRL.NUM_LIT=0x0 # (int , init-time) default = '0x0' : How many Literals FPB supports remapping (ignored if baseline or TZM) : [0x0..0xF]
cpu1.DWT_FUNCTION0.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION0. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION1.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION1. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION2.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION2. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION3.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION3. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION4.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION4. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION5.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION5. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION6.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION6. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION7.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION7. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION8.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION8. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION9.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION9. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION10.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION10. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION11.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION11. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION12.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION12. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION13.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION13. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION14.ID=0xB # (int , init-time) default = '0xB' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION14. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.DWT_FUNCTION15.ID=0x1E # (int , init-time) default = '0x1E' : Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION15. If 'baseline' is set, invalid ID bits are cleared : [0x0..0x1E]
cpu1.SAU_TYPE.SREGION=0x10 # (int , init-time) default = '0x10' : Number of SAU regions (0 => no SAU) : [0x0..0x100]
cpu1.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu1.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
cpu1.REGISTER_PUSH_ORDER="" # (string, init-time) default = '' : Order in which the registers are pushed on to the stack during exception handling. A comma separated list of register names and ranges. eg PC,R0-R3,R13-R14,S0-S5,FPSCR
cpu1.SAU_REGION0.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region0 at reset
cpu1.SAU_REGION0.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region0 at reset
cpu1.SAU_REGION0.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region0 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION0.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region0 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION1.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region1 at reset
cpu1.SAU_REGION1.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region1 at reset
cpu1.SAU_REGION1.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region1 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION1.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region1 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION2.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region2 at reset
cpu1.SAU_REGION2.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region2 at reset
cpu1.SAU_REGION2.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region2 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION2.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region2 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION3.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region3 at reset
cpu1.SAU_REGION3.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region3 at reset
cpu1.SAU_REGION3.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region3 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION3.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region3 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION4.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region4 at reset
cpu1.SAU_REGION4.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region4 at reset
cpu1.SAU_REGION4.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region4 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION4.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region4 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION5.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region5 at reset
cpu1.SAU_REGION5.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region5 at reset
cpu1.SAU_REGION5.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region5 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION5.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region5 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION6.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region6 at reset
cpu1.SAU_REGION6.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region6 at reset
cpu1.SAU_REGION6.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region6 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION6.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region6 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION7.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region7 at reset
cpu1.SAU_REGION7.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region7 at reset
cpu1.SAU_REGION7.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region7 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION7.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region7 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION8.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region8 at reset
cpu1.SAU_REGION8.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region8 at reset
cpu1.SAU_REGION8.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region8 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION8.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region8 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION9.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region9 at reset
cpu1.SAU_REGION9.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region9 at reset
cpu1.SAU_REGION9.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region9 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION9.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region9 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION10.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region10 at reset
cpu1.SAU_REGION10.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region10 at reset
cpu1.SAU_REGION10.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region10 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION10.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region10 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION11.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region11 at reset
cpu1.SAU_REGION11.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region11 at reset
cpu1.SAU_REGION11.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region11 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION11.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region11 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION12.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region12 at reset
cpu1.SAU_REGION12.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region12 at reset
cpu1.SAU_REGION12.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region12 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION12.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region12 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION13.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region13 at reset
cpu1.SAU_REGION13.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region13 at reset
cpu1.SAU_REGION13.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region13 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION13.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region13 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION14.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region14 at reset
cpu1.SAU_REGION14.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region14 at reset
cpu1.SAU_REGION14.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region14 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION14.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region14 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION15.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region15 at reset
cpu1.SAU_REGION15.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region15 at reset
cpu1.SAU_REGION15.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region15 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION15.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region15 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION16.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region16 at reset
cpu1.SAU_REGION16.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region16 at reset
cpu1.SAU_REGION16.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region16 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION16.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region16 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION17.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region17 at reset
cpu1.SAU_REGION17.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region17 at reset
cpu1.SAU_REGION17.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region17 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION17.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region17 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION18.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region18 at reset
cpu1.SAU_REGION18.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region18 at reset
cpu1.SAU_REGION18.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region18 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION18.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region18 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION19.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region19 at reset
cpu1.SAU_REGION19.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region19 at reset
cpu1.SAU_REGION19.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region19 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION19.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region19 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION20.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region20 at reset
cpu1.SAU_REGION20.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region20 at reset
cpu1.SAU_REGION20.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region20 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION20.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region20 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION21.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region21 at reset
cpu1.SAU_REGION21.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region21 at reset
cpu1.SAU_REGION21.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region21 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION21.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region21 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION22.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region22 at reset
cpu1.SAU_REGION22.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region22 at reset
cpu1.SAU_REGION22.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region22 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION22.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region22 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION23.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region23 at reset
cpu1.SAU_REGION23.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region23 at reset
cpu1.SAU_REGION23.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region23 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION23.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region23 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION24.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region24 at reset
cpu1.SAU_REGION24.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region24 at reset
cpu1.SAU_REGION24.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region24 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION24.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region24 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION25.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region25 at reset
cpu1.SAU_REGION25.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region25 at reset
cpu1.SAU_REGION25.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region25 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION25.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region25 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION26.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region26 at reset
cpu1.SAU_REGION26.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region26 at reset
cpu1.SAU_REGION26.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region26 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION26.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region26 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION27.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region27 at reset
cpu1.SAU_REGION27.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region27 at reset
cpu1.SAU_REGION27.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region27 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION27.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region27 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION28.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region28 at reset
cpu1.SAU_REGION28.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region28 at reset
cpu1.SAU_REGION28.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region28 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION28.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region28 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION29.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region29 at reset
cpu1.SAU_REGION29.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region29 at reset
cpu1.SAU_REGION29.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region29 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION29.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region29 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION30.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region30 at reset
cpu1.SAU_REGION30.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region30 at reset
cpu1.SAU_REGION30.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region30 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION30.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region30 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION31.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region31 at reset
cpu1.SAU_REGION31.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region31 at reset
cpu1.SAU_REGION31.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region31 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION31.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region31 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION32.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region32 at reset
cpu1.SAU_REGION32.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region32 at reset
cpu1.SAU_REGION32.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region32 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION32.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region32 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION33.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region33 at reset
cpu1.SAU_REGION33.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region33 at reset
cpu1.SAU_REGION33.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region33 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION33.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region33 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION34.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region34 at reset
cpu1.SAU_REGION34.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region34 at reset
cpu1.SAU_REGION34.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region34 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION34.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region34 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION35.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region35 at reset
cpu1.SAU_REGION35.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region35 at reset
cpu1.SAU_REGION35.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region35 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION35.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region35 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION36.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region36 at reset
cpu1.SAU_REGION36.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region36 at reset
cpu1.SAU_REGION36.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region36 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION36.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region36 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION37.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region37 at reset
cpu1.SAU_REGION37.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region37 at reset
cpu1.SAU_REGION37.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region37 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION37.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region37 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION38.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region38 at reset
cpu1.SAU_REGION38.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region38 at reset
cpu1.SAU_REGION38.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region38 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION38.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region38 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION39.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region39 at reset
cpu1.SAU_REGION39.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region39 at reset
cpu1.SAU_REGION39.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region39 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION39.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region39 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION40.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region40 at reset
cpu1.SAU_REGION40.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region40 at reset
cpu1.SAU_REGION40.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region40 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION40.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region40 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION41.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region41 at reset
cpu1.SAU_REGION41.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region41 at reset
cpu1.SAU_REGION41.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region41 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION41.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region41 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION42.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region42 at reset
cpu1.SAU_REGION42.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region42 at reset
cpu1.SAU_REGION42.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region42 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION42.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region42 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION43.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region43 at reset
cpu1.SAU_REGION43.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region43 at reset
cpu1.SAU_REGION43.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region43 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION43.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region43 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION44.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region44 at reset
cpu1.SAU_REGION44.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region44 at reset
cpu1.SAU_REGION44.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region44 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION44.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region44 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION45.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region45 at reset
cpu1.SAU_REGION45.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region45 at reset
cpu1.SAU_REGION45.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region45 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION45.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region45 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION46.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region46 at reset
cpu1.SAU_REGION46.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region46 at reset
cpu1.SAU_REGION46.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region46 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION46.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region46 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION47.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region47 at reset
cpu1.SAU_REGION47.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region47 at reset
cpu1.SAU_REGION47.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region47 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION47.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region47 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION48.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region48 at reset
cpu1.SAU_REGION48.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region48 at reset
cpu1.SAU_REGION48.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region48 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION48.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region48 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION49.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region49 at reset
cpu1.SAU_REGION49.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region49 at reset
cpu1.SAU_REGION49.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region49 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION49.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region49 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION50.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region50 at reset
cpu1.SAU_REGION50.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region50 at reset
cpu1.SAU_REGION50.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region50 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION50.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region50 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION51.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region51 at reset
cpu1.SAU_REGION51.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region51 at reset
cpu1.SAU_REGION51.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region51 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION51.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region51 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION52.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region52 at reset
cpu1.SAU_REGION52.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region52 at reset
cpu1.SAU_REGION52.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region52 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION52.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region52 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION53.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region53 at reset
cpu1.SAU_REGION53.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region53 at reset
cpu1.SAU_REGION53.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region53 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION53.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region53 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION54.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region54 at reset
cpu1.SAU_REGION54.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region54 at reset
cpu1.SAU_REGION54.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region54 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION54.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region54 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION55.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region55 at reset
cpu1.SAU_REGION55.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region55 at reset
cpu1.SAU_REGION55.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region55 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION55.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region55 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION56.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region56 at reset
cpu1.SAU_REGION56.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region56 at reset
cpu1.SAU_REGION56.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region56 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION56.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region56 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION57.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region57 at reset
cpu1.SAU_REGION57.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region57 at reset
cpu1.SAU_REGION57.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region57 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION57.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region57 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION58.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region58 at reset
cpu1.SAU_REGION58.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region58 at reset
cpu1.SAU_REGION58.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region58 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION58.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region58 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION59.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region59 at reset
cpu1.SAU_REGION59.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region59 at reset
cpu1.SAU_REGION59.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region59 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION59.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region59 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION60.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region60 at reset
cpu1.SAU_REGION60.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region60 at reset
cpu1.SAU_REGION60.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region60 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION60.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region60 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION61.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region61 at reset
cpu1.SAU_REGION61.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region61 at reset
cpu1.SAU_REGION61.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region61 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION61.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region61 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION62.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region62 at reset
cpu1.SAU_REGION62.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region62 at reset
cpu1.SAU_REGION62.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region62 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION62.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region62 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION63.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region63 at reset
cpu1.SAU_REGION63.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region63 at reset
cpu1.SAU_REGION63.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region63 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION63.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region63 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION64.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region64 at reset
cpu1.SAU_REGION64.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region64 at reset
cpu1.SAU_REGION64.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region64 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION64.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region64 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION65.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region65 at reset
cpu1.SAU_REGION65.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region65 at reset
cpu1.SAU_REGION65.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region65 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION65.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region65 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION66.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region66 at reset
cpu1.SAU_REGION66.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region66 at reset
cpu1.SAU_REGION66.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region66 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION66.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region66 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION67.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region67 at reset
cpu1.SAU_REGION67.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region67 at reset
cpu1.SAU_REGION67.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region67 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION67.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region67 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION68.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region68 at reset
cpu1.SAU_REGION68.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region68 at reset
cpu1.SAU_REGION68.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region68 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION68.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region68 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION69.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region69 at reset
cpu1.SAU_REGION69.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region69 at reset
cpu1.SAU_REGION69.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region69 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION69.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region69 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION70.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region70 at reset
cpu1.SAU_REGION70.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region70 at reset
cpu1.SAU_REGION70.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region70 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION70.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region70 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION71.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region71 at reset
cpu1.SAU_REGION71.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region71 at reset
cpu1.SAU_REGION71.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region71 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION71.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region71 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION72.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region72 at reset
cpu1.SAU_REGION72.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region72 at reset
cpu1.SAU_REGION72.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region72 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION72.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region72 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION73.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region73 at reset
cpu1.SAU_REGION73.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region73 at reset
cpu1.SAU_REGION73.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region73 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION73.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region73 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION74.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region74 at reset
cpu1.SAU_REGION74.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region74 at reset
cpu1.SAU_REGION74.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region74 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION74.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region74 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION75.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region75 at reset
cpu1.SAU_REGION75.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region75 at reset
cpu1.SAU_REGION75.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region75 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION75.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region75 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION76.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region76 at reset
cpu1.SAU_REGION76.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region76 at reset
cpu1.SAU_REGION76.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region76 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION76.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region76 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION77.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region77 at reset
cpu1.SAU_REGION77.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region77 at reset
cpu1.SAU_REGION77.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region77 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION77.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region77 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION78.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region78 at reset
cpu1.SAU_REGION78.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region78 at reset
cpu1.SAU_REGION78.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region78 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION78.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region78 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION79.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region79 at reset
cpu1.SAU_REGION79.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region79 at reset
cpu1.SAU_REGION79.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region79 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION79.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region79 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION80.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region80 at reset
cpu1.SAU_REGION80.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region80 at reset
cpu1.SAU_REGION80.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region80 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION80.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region80 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION81.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region81 at reset
cpu1.SAU_REGION81.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region81 at reset
cpu1.SAU_REGION81.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region81 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION81.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region81 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION82.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region82 at reset
cpu1.SAU_REGION82.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region82 at reset
cpu1.SAU_REGION82.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region82 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION82.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region82 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION83.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region83 at reset
cpu1.SAU_REGION83.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region83 at reset
cpu1.SAU_REGION83.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region83 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION83.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region83 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION84.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region84 at reset
cpu1.SAU_REGION84.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region84 at reset
cpu1.SAU_REGION84.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region84 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION84.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region84 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION85.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region85 at reset
cpu1.SAU_REGION85.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region85 at reset
cpu1.SAU_REGION85.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region85 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION85.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region85 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION86.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region86 at reset
cpu1.SAU_REGION86.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region86 at reset
cpu1.SAU_REGION86.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region86 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION86.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region86 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION87.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region87 at reset
cpu1.SAU_REGION87.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region87 at reset
cpu1.SAU_REGION87.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region87 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION87.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region87 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION88.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region88 at reset
cpu1.SAU_REGION88.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region88 at reset
cpu1.SAU_REGION88.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region88 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION88.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region88 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION89.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region89 at reset
cpu1.SAU_REGION89.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region89 at reset
cpu1.SAU_REGION89.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region89 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION89.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region89 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION90.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region90 at reset
cpu1.SAU_REGION90.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region90 at reset
cpu1.SAU_REGION90.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region90 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION90.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region90 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION91.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region91 at reset
cpu1.SAU_REGION91.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region91 at reset
cpu1.SAU_REGION91.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region91 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION91.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region91 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION92.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region92 at reset
cpu1.SAU_REGION92.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region92 at reset
cpu1.SAU_REGION92.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region92 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION92.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region92 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION93.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region93 at reset
cpu1.SAU_REGION93.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region93 at reset
cpu1.SAU_REGION93.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region93 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION93.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region93 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION94.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region94 at reset
cpu1.SAU_REGION94.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region94 at reset
cpu1.SAU_REGION94.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region94 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION94.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region94 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION95.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region95 at reset
cpu1.SAU_REGION95.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region95 at reset
cpu1.SAU_REGION95.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region95 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION95.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region95 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION96.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region96 at reset
cpu1.SAU_REGION96.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region96 at reset
cpu1.SAU_REGION96.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region96 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION96.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region96 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION97.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region97 at reset
cpu1.SAU_REGION97.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region97 at reset
cpu1.SAU_REGION97.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region97 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION97.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region97 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION98.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region98 at reset
cpu1.SAU_REGION98.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region98 at reset
cpu1.SAU_REGION98.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region98 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION98.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region98 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION99.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region99 at reset
cpu1.SAU_REGION99.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region99 at reset
cpu1.SAU_REGION99.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region99 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION99.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region99 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION100.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region100 at reset
cpu1.SAU_REGION100.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region100 at reset
cpu1.SAU_REGION100.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region100 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION100.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region100 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION101.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region101 at reset
cpu1.SAU_REGION101.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region101 at reset
cpu1.SAU_REGION101.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region101 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION101.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region101 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION102.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region102 at reset
cpu1.SAU_REGION102.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region102 at reset
cpu1.SAU_REGION102.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region102 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION102.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region102 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION103.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region103 at reset
cpu1.SAU_REGION103.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region103 at reset
cpu1.SAU_REGION103.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region103 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION103.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region103 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION104.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region104 at reset
cpu1.SAU_REGION104.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region104 at reset
cpu1.SAU_REGION104.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region104 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION104.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region104 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION105.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region105 at reset
cpu1.SAU_REGION105.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region105 at reset
cpu1.SAU_REGION105.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region105 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION105.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region105 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION106.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region106 at reset
cpu1.SAU_REGION106.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region106 at reset
cpu1.SAU_REGION106.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region106 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION106.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region106 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION107.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region107 at reset
cpu1.SAU_REGION107.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region107 at reset
cpu1.SAU_REGION107.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region107 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION107.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region107 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION108.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region108 at reset
cpu1.SAU_REGION108.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region108 at reset
cpu1.SAU_REGION108.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region108 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION108.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region108 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION109.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region109 at reset
cpu1.SAU_REGION109.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region109 at reset
cpu1.SAU_REGION109.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region109 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION109.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region109 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION110.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region110 at reset
cpu1.SAU_REGION110.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region110 at reset
cpu1.SAU_REGION110.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region110 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION110.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region110 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION111.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region111 at reset
cpu1.SAU_REGION111.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region111 at reset
cpu1.SAU_REGION111.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region111 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION111.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region111 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION112.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region112 at reset
cpu1.SAU_REGION112.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region112 at reset
cpu1.SAU_REGION112.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region112 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION112.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region112 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION113.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region113 at reset
cpu1.SAU_REGION113.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region113 at reset
cpu1.SAU_REGION113.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region113 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION113.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region113 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION114.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region114 at reset
cpu1.SAU_REGION114.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region114 at reset
cpu1.SAU_REGION114.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region114 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION114.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region114 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION115.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region115 at reset
cpu1.SAU_REGION115.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region115 at reset
cpu1.SAU_REGION115.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region115 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION115.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region115 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION116.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region116 at reset
cpu1.SAU_REGION116.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region116 at reset
cpu1.SAU_REGION116.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region116 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION116.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region116 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION117.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region117 at reset
cpu1.SAU_REGION117.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region117 at reset
cpu1.SAU_REGION117.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region117 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION117.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region117 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION118.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region118 at reset
cpu1.SAU_REGION118.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region118 at reset
cpu1.SAU_REGION118.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region118 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION118.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region118 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION119.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region119 at reset
cpu1.SAU_REGION119.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region119 at reset
cpu1.SAU_REGION119.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region119 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION119.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region119 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION120.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region120 at reset
cpu1.SAU_REGION120.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region120 at reset
cpu1.SAU_REGION120.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region120 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION120.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region120 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION121.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region121 at reset
cpu1.SAU_REGION121.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region121 at reset
cpu1.SAU_REGION121.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region121 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION121.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region121 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION122.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region122 at reset
cpu1.SAU_REGION122.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region122 at reset
cpu1.SAU_REGION122.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region122 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION122.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region122 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION123.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region123 at reset
cpu1.SAU_REGION123.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region123 at reset
cpu1.SAU_REGION123.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region123 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION123.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region123 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION124.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region124 at reset
cpu1.SAU_REGION124.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region124 at reset
cpu1.SAU_REGION124.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region124 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION124.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region124 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION125.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region125 at reset
cpu1.SAU_REGION125.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region125 at reset
cpu1.SAU_REGION125.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region125 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION125.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region125 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION126.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region126 at reset
cpu1.SAU_REGION126.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region126 at reset
cpu1.SAU_REGION126.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region126 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION126.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region126 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION127.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region127 at reset
cpu1.SAU_REGION127.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region127 at reset
cpu1.SAU_REGION127.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region127 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION127.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region127 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION128.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region128 at reset
cpu1.SAU_REGION128.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region128 at reset
cpu1.SAU_REGION128.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region128 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION128.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region128 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION129.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region129 at reset
cpu1.SAU_REGION129.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region129 at reset
cpu1.SAU_REGION129.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region129 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION129.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region129 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION130.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region130 at reset
cpu1.SAU_REGION130.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region130 at reset
cpu1.SAU_REGION130.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region130 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION130.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region130 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION131.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region131 at reset
cpu1.SAU_REGION131.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region131 at reset
cpu1.SAU_REGION131.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region131 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION131.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region131 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION132.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region132 at reset
cpu1.SAU_REGION132.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region132 at reset
cpu1.SAU_REGION132.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region132 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION132.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region132 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION133.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region133 at reset
cpu1.SAU_REGION133.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region133 at reset
cpu1.SAU_REGION133.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region133 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION133.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region133 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION134.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region134 at reset
cpu1.SAU_REGION134.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region134 at reset
cpu1.SAU_REGION134.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region134 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION134.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region134 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION135.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region135 at reset
cpu1.SAU_REGION135.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region135 at reset
cpu1.SAU_REGION135.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region135 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION135.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region135 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION136.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region136 at reset
cpu1.SAU_REGION136.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region136 at reset
cpu1.SAU_REGION136.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region136 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION136.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region136 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION137.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region137 at reset
cpu1.SAU_REGION137.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region137 at reset
cpu1.SAU_REGION137.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region137 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION137.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region137 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION138.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region138 at reset
cpu1.SAU_REGION138.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region138 at reset
cpu1.SAU_REGION138.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region138 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION138.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region138 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION139.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region139 at reset
cpu1.SAU_REGION139.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region139 at reset
cpu1.SAU_REGION139.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region139 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION139.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region139 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION140.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region140 at reset
cpu1.SAU_REGION140.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region140 at reset
cpu1.SAU_REGION140.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region140 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION140.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region140 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION141.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region141 at reset
cpu1.SAU_REGION141.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region141 at reset
cpu1.SAU_REGION141.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region141 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION141.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region141 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION142.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region142 at reset
cpu1.SAU_REGION142.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region142 at reset
cpu1.SAU_REGION142.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region142 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION142.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region142 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION143.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region143 at reset
cpu1.SAU_REGION143.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region143 at reset
cpu1.SAU_REGION143.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region143 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION143.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region143 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION144.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region144 at reset
cpu1.SAU_REGION144.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region144 at reset
cpu1.SAU_REGION144.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region144 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION144.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region144 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION145.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region145 at reset
cpu1.SAU_REGION145.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region145 at reset
cpu1.SAU_REGION145.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region145 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION145.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region145 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION146.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region146 at reset
cpu1.SAU_REGION146.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region146 at reset
cpu1.SAU_REGION146.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region146 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION146.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region146 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION147.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region147 at reset
cpu1.SAU_REGION147.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region147 at reset
cpu1.SAU_REGION147.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region147 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION147.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region147 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION148.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region148 at reset
cpu1.SAU_REGION148.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region148 at reset
cpu1.SAU_REGION148.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region148 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION148.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region148 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION149.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region149 at reset
cpu1.SAU_REGION149.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region149 at reset
cpu1.SAU_REGION149.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region149 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION149.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region149 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION150.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region150 at reset
cpu1.SAU_REGION150.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region150 at reset
cpu1.SAU_REGION150.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region150 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION150.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region150 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION151.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region151 at reset
cpu1.SAU_REGION151.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region151 at reset
cpu1.SAU_REGION151.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region151 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION151.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region151 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION152.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region152 at reset
cpu1.SAU_REGION152.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region152 at reset
cpu1.SAU_REGION152.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region152 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION152.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region152 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION153.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region153 at reset
cpu1.SAU_REGION153.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region153 at reset
cpu1.SAU_REGION153.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region153 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION153.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region153 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION154.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region154 at reset
cpu1.SAU_REGION154.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region154 at reset
cpu1.SAU_REGION154.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region154 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION154.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region154 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION155.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region155 at reset
cpu1.SAU_REGION155.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region155 at reset
cpu1.SAU_REGION155.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region155 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION155.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region155 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION156.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region156 at reset
cpu1.SAU_REGION156.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region156 at reset
cpu1.SAU_REGION156.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region156 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION156.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region156 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION157.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region157 at reset
cpu1.SAU_REGION157.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region157 at reset
cpu1.SAU_REGION157.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region157 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION157.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region157 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION158.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region158 at reset
cpu1.SAU_REGION158.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region158 at reset
cpu1.SAU_REGION158.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region158 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION158.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region158 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION159.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region159 at reset
cpu1.SAU_REGION159.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region159 at reset
cpu1.SAU_REGION159.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region159 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION159.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region159 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION160.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region160 at reset
cpu1.SAU_REGION160.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region160 at reset
cpu1.SAU_REGION160.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region160 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION160.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region160 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION161.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region161 at reset
cpu1.SAU_REGION161.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region161 at reset
cpu1.SAU_REGION161.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region161 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION161.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region161 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION162.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region162 at reset
cpu1.SAU_REGION162.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region162 at reset
cpu1.SAU_REGION162.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region162 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION162.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region162 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION163.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region163 at reset
cpu1.SAU_REGION163.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region163 at reset
cpu1.SAU_REGION163.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region163 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION163.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region163 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION164.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region164 at reset
cpu1.SAU_REGION164.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region164 at reset
cpu1.SAU_REGION164.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region164 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION164.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region164 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION165.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region165 at reset
cpu1.SAU_REGION165.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region165 at reset
cpu1.SAU_REGION165.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region165 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION165.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region165 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION166.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region166 at reset
cpu1.SAU_REGION166.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region166 at reset
cpu1.SAU_REGION166.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region166 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION166.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region166 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION167.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region167 at reset
cpu1.SAU_REGION167.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region167 at reset
cpu1.SAU_REGION167.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region167 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION167.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region167 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION168.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region168 at reset
cpu1.SAU_REGION168.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region168 at reset
cpu1.SAU_REGION168.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region168 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION168.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region168 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION169.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region169 at reset
cpu1.SAU_REGION169.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region169 at reset
cpu1.SAU_REGION169.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region169 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION169.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region169 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION170.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region170 at reset
cpu1.SAU_REGION170.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region170 at reset
cpu1.SAU_REGION170.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region170 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION170.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region170 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION171.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region171 at reset
cpu1.SAU_REGION171.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region171 at reset
cpu1.SAU_REGION171.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region171 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION171.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region171 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION172.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region172 at reset
cpu1.SAU_REGION172.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region172 at reset
cpu1.SAU_REGION172.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region172 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION172.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region172 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION173.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region173 at reset
cpu1.SAU_REGION173.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region173 at reset
cpu1.SAU_REGION173.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region173 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION173.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region173 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION174.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region174 at reset
cpu1.SAU_REGION174.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region174 at reset
cpu1.SAU_REGION174.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region174 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION174.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region174 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION175.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region175 at reset
cpu1.SAU_REGION175.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region175 at reset
cpu1.SAU_REGION175.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region175 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION175.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region175 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION176.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region176 at reset
cpu1.SAU_REGION176.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region176 at reset
cpu1.SAU_REGION176.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region176 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION176.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region176 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION177.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region177 at reset
cpu1.SAU_REGION177.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region177 at reset
cpu1.SAU_REGION177.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region177 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION177.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region177 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION178.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region178 at reset
cpu1.SAU_REGION178.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region178 at reset
cpu1.SAU_REGION178.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region178 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION178.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region178 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION179.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region179 at reset
cpu1.SAU_REGION179.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region179 at reset
cpu1.SAU_REGION179.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region179 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION179.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region179 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION180.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region180 at reset
cpu1.SAU_REGION180.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region180 at reset
cpu1.SAU_REGION180.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region180 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION180.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region180 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION181.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region181 at reset
cpu1.SAU_REGION181.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region181 at reset
cpu1.SAU_REGION181.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region181 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION181.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region181 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION182.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region182 at reset
cpu1.SAU_REGION182.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region182 at reset
cpu1.SAU_REGION182.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region182 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION182.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region182 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION183.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region183 at reset
cpu1.SAU_REGION183.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region183 at reset
cpu1.SAU_REGION183.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region183 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION183.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region183 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION184.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region184 at reset
cpu1.SAU_REGION184.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region184 at reset
cpu1.SAU_REGION184.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region184 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION184.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region184 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION185.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region185 at reset
cpu1.SAU_REGION185.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region185 at reset
cpu1.SAU_REGION185.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region185 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION185.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region185 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION186.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region186 at reset
cpu1.SAU_REGION186.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region186 at reset
cpu1.SAU_REGION186.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region186 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION186.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region186 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION187.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region187 at reset
cpu1.SAU_REGION187.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region187 at reset
cpu1.SAU_REGION187.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region187 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION187.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region187 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION188.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region188 at reset
cpu1.SAU_REGION188.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region188 at reset
cpu1.SAU_REGION188.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region188 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION188.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region188 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION189.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region189 at reset
cpu1.SAU_REGION189.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region189 at reset
cpu1.SAU_REGION189.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region189 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION189.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region189 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION190.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region190 at reset
cpu1.SAU_REGION190.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region190 at reset
cpu1.SAU_REGION190.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region190 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION190.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region190 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION191.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region191 at reset
cpu1.SAU_REGION191.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region191 at reset
cpu1.SAU_REGION191.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region191 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION191.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region191 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION192.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region192 at reset
cpu1.SAU_REGION192.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region192 at reset
cpu1.SAU_REGION192.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region192 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION192.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region192 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION193.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region193 at reset
cpu1.SAU_REGION193.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region193 at reset
cpu1.SAU_REGION193.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region193 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION193.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region193 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION194.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region194 at reset
cpu1.SAU_REGION194.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region194 at reset
cpu1.SAU_REGION194.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region194 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION194.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region194 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION195.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region195 at reset
cpu1.SAU_REGION195.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region195 at reset
cpu1.SAU_REGION195.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region195 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION195.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region195 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION196.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region196 at reset
cpu1.SAU_REGION196.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region196 at reset
cpu1.SAU_REGION196.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region196 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION196.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region196 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION197.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region197 at reset
cpu1.SAU_REGION197.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region197 at reset
cpu1.SAU_REGION197.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region197 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION197.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region197 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION198.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region198 at reset
cpu1.SAU_REGION198.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region198 at reset
cpu1.SAU_REGION198.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region198 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION198.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region198 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION199.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region199 at reset
cpu1.SAU_REGION199.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region199 at reset
cpu1.SAU_REGION199.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region199 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION199.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region199 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION200.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region200 at reset
cpu1.SAU_REGION200.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region200 at reset
cpu1.SAU_REGION200.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region200 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION200.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region200 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION201.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region201 at reset
cpu1.SAU_REGION201.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region201 at reset
cpu1.SAU_REGION201.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region201 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION201.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region201 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION202.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region202 at reset
cpu1.SAU_REGION202.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region202 at reset
cpu1.SAU_REGION202.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region202 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION202.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region202 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION203.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region203 at reset
cpu1.SAU_REGION203.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region203 at reset
cpu1.SAU_REGION203.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region203 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION203.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region203 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION204.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region204 at reset
cpu1.SAU_REGION204.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region204 at reset
cpu1.SAU_REGION204.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region204 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION204.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region204 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION205.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region205 at reset
cpu1.SAU_REGION205.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region205 at reset
cpu1.SAU_REGION205.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region205 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION205.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region205 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION206.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region206 at reset
cpu1.SAU_REGION206.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region206 at reset
cpu1.SAU_REGION206.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region206 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION206.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region206 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION207.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region207 at reset
cpu1.SAU_REGION207.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region207 at reset
cpu1.SAU_REGION207.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region207 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION207.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region207 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION208.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region208 at reset
cpu1.SAU_REGION208.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region208 at reset
cpu1.SAU_REGION208.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region208 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION208.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region208 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION209.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region209 at reset
cpu1.SAU_REGION209.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region209 at reset
cpu1.SAU_REGION209.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region209 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION209.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region209 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION210.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region210 at reset
cpu1.SAU_REGION210.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region210 at reset
cpu1.SAU_REGION210.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region210 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION210.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region210 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION211.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region211 at reset
cpu1.SAU_REGION211.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region211 at reset
cpu1.SAU_REGION211.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region211 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION211.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region211 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION212.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region212 at reset
cpu1.SAU_REGION212.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region212 at reset
cpu1.SAU_REGION212.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region212 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION212.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region212 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION213.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region213 at reset
cpu1.SAU_REGION213.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region213 at reset
cpu1.SAU_REGION213.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region213 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION213.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region213 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION214.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region214 at reset
cpu1.SAU_REGION214.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region214 at reset
cpu1.SAU_REGION214.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region214 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION214.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region214 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION215.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region215 at reset
cpu1.SAU_REGION215.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region215 at reset
cpu1.SAU_REGION215.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region215 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION215.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region215 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION216.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region216 at reset
cpu1.SAU_REGION216.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region216 at reset
cpu1.SAU_REGION216.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region216 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION216.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region216 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION217.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region217 at reset
cpu1.SAU_REGION217.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region217 at reset
cpu1.SAU_REGION217.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region217 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION217.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region217 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION218.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region218 at reset
cpu1.SAU_REGION218.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region218 at reset
cpu1.SAU_REGION218.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region218 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION218.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region218 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION219.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region219 at reset
cpu1.SAU_REGION219.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region219 at reset
cpu1.SAU_REGION219.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region219 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION219.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region219 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION220.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region220 at reset
cpu1.SAU_REGION220.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region220 at reset
cpu1.SAU_REGION220.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region220 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION220.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region220 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION221.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region221 at reset
cpu1.SAU_REGION221.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region221 at reset
cpu1.SAU_REGION221.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region221 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION221.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region221 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION222.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region222 at reset
cpu1.SAU_REGION222.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region222 at reset
cpu1.SAU_REGION222.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region222 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION222.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region222 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION223.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region223 at reset
cpu1.SAU_REGION223.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region223 at reset
cpu1.SAU_REGION223.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region223 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION223.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region223 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION224.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region224 at reset
cpu1.SAU_REGION224.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region224 at reset
cpu1.SAU_REGION224.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region224 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION224.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region224 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION225.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region225 at reset
cpu1.SAU_REGION225.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region225 at reset
cpu1.SAU_REGION225.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region225 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION225.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region225 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION226.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region226 at reset
cpu1.SAU_REGION226.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region226 at reset
cpu1.SAU_REGION226.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region226 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION226.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region226 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION227.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region227 at reset
cpu1.SAU_REGION227.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region227 at reset
cpu1.SAU_REGION227.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region227 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION227.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region227 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION228.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region228 at reset
cpu1.SAU_REGION228.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region228 at reset
cpu1.SAU_REGION228.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region228 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION228.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region228 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION229.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region229 at reset
cpu1.SAU_REGION229.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region229 at reset
cpu1.SAU_REGION229.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region229 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION229.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region229 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION230.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region230 at reset
cpu1.SAU_REGION230.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region230 at reset
cpu1.SAU_REGION230.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region230 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION230.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region230 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION231.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region231 at reset
cpu1.SAU_REGION231.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region231 at reset
cpu1.SAU_REGION231.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region231 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION231.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region231 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION232.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region232 at reset
cpu1.SAU_REGION232.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region232 at reset
cpu1.SAU_REGION232.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region232 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION232.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region232 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION233.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region233 at reset
cpu1.SAU_REGION233.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region233 at reset
cpu1.SAU_REGION233.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region233 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION233.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region233 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION234.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region234 at reset
cpu1.SAU_REGION234.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region234 at reset
cpu1.SAU_REGION234.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region234 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION234.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region234 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION235.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region235 at reset
cpu1.SAU_REGION235.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region235 at reset
cpu1.SAU_REGION235.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region235 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION235.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region235 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION236.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region236 at reset
cpu1.SAU_REGION236.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region236 at reset
cpu1.SAU_REGION236.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region236 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION236.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region236 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION237.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region237 at reset
cpu1.SAU_REGION237.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region237 at reset
cpu1.SAU_REGION237.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region237 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION237.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region237 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION238.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region238 at reset
cpu1.SAU_REGION238.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region238 at reset
cpu1.SAU_REGION238.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region238 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION238.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region238 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION239.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region239 at reset
cpu1.SAU_REGION239.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region239 at reset
cpu1.SAU_REGION239.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region239 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION239.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region239 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION240.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region240 at reset
cpu1.SAU_REGION240.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region240 at reset
cpu1.SAU_REGION240.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region240 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION240.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region240 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION241.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region241 at reset
cpu1.SAU_REGION241.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region241 at reset
cpu1.SAU_REGION241.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region241 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION241.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region241 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION242.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region242 at reset
cpu1.SAU_REGION242.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region242 at reset
cpu1.SAU_REGION242.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region242 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION242.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region242 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION243.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region243 at reset
cpu1.SAU_REGION243.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region243 at reset
cpu1.SAU_REGION243.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region243 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION243.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region243 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION244.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region244 at reset
cpu1.SAU_REGION244.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region244 at reset
cpu1.SAU_REGION244.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region244 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION244.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region244 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION245.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region245 at reset
cpu1.SAU_REGION245.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region245 at reset
cpu1.SAU_REGION245.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region245 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION245.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region245 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION246.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region246 at reset
cpu1.SAU_REGION246.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region246 at reset
cpu1.SAU_REGION246.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region246 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION246.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region246 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION247.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region247 at reset
cpu1.SAU_REGION247.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region247 at reset
cpu1.SAU_REGION247.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region247 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION247.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region247 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION248.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region248 at reset
cpu1.SAU_REGION248.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region248 at reset
cpu1.SAU_REGION248.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region248 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION248.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region248 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION249.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region249 at reset
cpu1.SAU_REGION249.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region249 at reset
cpu1.SAU_REGION249.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region249 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION249.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region249 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION250.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region250 at reset
cpu1.SAU_REGION250.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region250 at reset
cpu1.SAU_REGION250.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region250 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION250.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region250 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION251.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region251 at reset
cpu1.SAU_REGION251.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region251 at reset
cpu1.SAU_REGION251.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region251 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION251.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region251 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION252.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region252 at reset
cpu1.SAU_REGION252.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region252 at reset
cpu1.SAU_REGION252.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region252 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION252.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region252 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION253.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region253 at reset
cpu1.SAU_REGION253.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region253 at reset
cpu1.SAU_REGION253.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region253 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION253.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region253 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION254.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region254 at reset
cpu1.SAU_REGION254.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region254 at reset
cpu1.SAU_REGION254.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region254 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION254.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region254 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION255.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU region255 at reset
cpu1.SAU_REGION255.NSC=0 # (bool , init-time) default = '0' : Set NSC for SAU region255 at reset
cpu1.SAU_REGION255.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of SAU region255 at reset : [0x0..0xFFFFFFFF]
cpu1.SAU_REGION255.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of SAU region255 at reset : [0x0..0xFFFFFFFF]
cpu1.NUM_IDAU_REGION=0xA # (int , init-time) default = '0xA' :
cpu1.IDAU_REGION0.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region0 as exempt
cpu1.IDAU_REGION1.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region1 as exempt
cpu1.IDAU_REGION2.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region2 as exempt
cpu1.IDAU_REGION3.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region3 as exempt
cpu1.IDAU_REGION4.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region4 as exempt
cpu1.IDAU_REGION5.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region5 as exempt
cpu1.IDAU_REGION6.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region6 as exempt
cpu1.IDAU_REGION7.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region7 as exempt
cpu1.IDAU_REGION8.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region8 as exempt
cpu1.IDAU_REGION9.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region9 as exempt
cpu1.IDAU_REGION10.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region10 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION10.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region10
cpu1.IDAU_REGION10.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region10 as exempt
cpu1.IDAU_REGION10.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region10 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION10.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region10 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION11.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region11 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION11.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region11
cpu1.IDAU_REGION11.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region11 as exempt
cpu1.IDAU_REGION11.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region11 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION11.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region11 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION12.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region12 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION12.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region12
cpu1.IDAU_REGION12.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region12 as exempt
cpu1.IDAU_REGION12.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region12 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION12.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region12 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION13.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region13 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION13.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region13
cpu1.IDAU_REGION13.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region13 as exempt
cpu1.IDAU_REGION13.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region13 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION13.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region13 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION14.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region14 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION14.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region14
cpu1.IDAU_REGION14.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region14 as exempt
cpu1.IDAU_REGION14.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region14 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION14.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region14 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION15.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region15 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION15.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region15
cpu1.IDAU_REGION15.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region15 as exempt
cpu1.IDAU_REGION15.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region15 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION15.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region15 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION16.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region16 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION16.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region16
cpu1.IDAU_REGION16.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region16 as exempt
cpu1.IDAU_REGION16.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region16 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION16.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region16 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION17.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region17 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION17.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region17
cpu1.IDAU_REGION17.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region17 as exempt
cpu1.IDAU_REGION17.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region17 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION17.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region17 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION18.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region18 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION18.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region18
cpu1.IDAU_REGION18.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region18 as exempt
cpu1.IDAU_REGION18.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region18 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION18.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region18 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION19.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region19 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION19.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region19
cpu1.IDAU_REGION19.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region19 as exempt
cpu1.IDAU_REGION19.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region19 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION19.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region19 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION20.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region20 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION20.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region20
cpu1.IDAU_REGION20.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region20 as exempt
cpu1.IDAU_REGION20.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region20 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION20.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region20 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION21.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region21 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION21.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region21
cpu1.IDAU_REGION21.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region21 as exempt
cpu1.IDAU_REGION21.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region21 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION21.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region21 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION22.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region22 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION22.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region22
cpu1.IDAU_REGION22.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region22 as exempt
cpu1.IDAU_REGION22.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region22 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION22.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region22 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION23.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region23 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION23.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region23
cpu1.IDAU_REGION23.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region23 as exempt
cpu1.IDAU_REGION23.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region23 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION23.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region23 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION24.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region24 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION24.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region24
cpu1.IDAU_REGION24.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region24 as exempt
cpu1.IDAU_REGION24.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region24 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION24.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region24 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION25.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region25 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION25.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region25
cpu1.IDAU_REGION25.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region25 as exempt
cpu1.IDAU_REGION25.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region25 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION25.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region25 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION26.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region26 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION26.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region26
cpu1.IDAU_REGION26.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region26 as exempt
cpu1.IDAU_REGION26.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region26 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION26.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region26 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION27.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region27 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION27.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region27
cpu1.IDAU_REGION27.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region27 as exempt
cpu1.IDAU_REGION27.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region27 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION27.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region27 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION28.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region28 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION28.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region28
cpu1.IDAU_REGION28.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region28 as exempt
cpu1.IDAU_REGION28.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region28 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION28.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region28 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION29.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region29 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION29.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region29
cpu1.IDAU_REGION29.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region29 as exempt
cpu1.IDAU_REGION29.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region29 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION29.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region29 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION30.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region30 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION30.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region30
cpu1.IDAU_REGION30.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region30 as exempt
cpu1.IDAU_REGION30.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region30 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION30.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region30 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION31.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region31 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION31.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region31
cpu1.IDAU_REGION31.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region31 as exempt
cpu1.IDAU_REGION31.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region31 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION31.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region31 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION32.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region32 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION32.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region32
cpu1.IDAU_REGION32.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region32 as exempt
cpu1.IDAU_REGION32.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region32 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION32.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region32 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION33.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region33 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION33.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region33
cpu1.IDAU_REGION33.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region33 as exempt
cpu1.IDAU_REGION33.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region33 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION33.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region33 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION34.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region34 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION34.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region34
cpu1.IDAU_REGION34.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region34 as exempt
cpu1.IDAU_REGION34.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region34 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION34.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region34 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION35.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region35 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION35.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region35
cpu1.IDAU_REGION35.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region35 as exempt
cpu1.IDAU_REGION35.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region35 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION35.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region35 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION36.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region36 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION36.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region36
cpu1.IDAU_REGION36.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region36 as exempt
cpu1.IDAU_REGION36.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region36 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION36.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region36 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION37.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region37 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION37.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region37
cpu1.IDAU_REGION37.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region37 as exempt
cpu1.IDAU_REGION37.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region37 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION37.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region37 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION38.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region38 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION38.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region38
cpu1.IDAU_REGION38.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region38 as exempt
cpu1.IDAU_REGION38.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region38 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION38.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region38 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION39.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region39 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION39.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region39
cpu1.IDAU_REGION39.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region39 as exempt
cpu1.IDAU_REGION39.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region39 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION39.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region39 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION40.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region40 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION40.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region40
cpu1.IDAU_REGION40.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region40 as exempt
cpu1.IDAU_REGION40.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region40 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION40.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region40 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION41.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region41 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION41.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region41
cpu1.IDAU_REGION41.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region41 as exempt
cpu1.IDAU_REGION41.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region41 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION41.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region41 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION42.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region42 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION42.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region42
cpu1.IDAU_REGION42.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region42 as exempt
cpu1.IDAU_REGION42.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region42 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION42.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region42 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION43.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region43 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION43.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region43
cpu1.IDAU_REGION43.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region43 as exempt
cpu1.IDAU_REGION43.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region43 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION43.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region43 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION44.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region44 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION44.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region44
cpu1.IDAU_REGION44.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region44 as exempt
cpu1.IDAU_REGION44.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region44 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION44.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region44 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION45.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region45 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION45.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region45
cpu1.IDAU_REGION45.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region45 as exempt
cpu1.IDAU_REGION45.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region45 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION45.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region45 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION46.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region46 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION46.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region46
cpu1.IDAU_REGION46.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region46 as exempt
cpu1.IDAU_REGION46.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region46 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION46.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region46 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION47.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region47 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION47.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region47
cpu1.IDAU_REGION47.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region47 as exempt
cpu1.IDAU_REGION47.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region47 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION47.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region47 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION48.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region48 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION48.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region48
cpu1.IDAU_REGION48.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region48 as exempt
cpu1.IDAU_REGION48.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region48 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION48.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region48 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION49.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region49 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION49.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region49
cpu1.IDAU_REGION49.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region49 as exempt
cpu1.IDAU_REGION49.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region49 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION49.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region49 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION50.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region50 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION50.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region50
cpu1.IDAU_REGION50.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region50 as exempt
cpu1.IDAU_REGION50.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region50 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION50.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region50 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION51.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region51 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION51.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region51
cpu1.IDAU_REGION51.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region51 as exempt
cpu1.IDAU_REGION51.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region51 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION51.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region51 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION52.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region52 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION52.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region52
cpu1.IDAU_REGION52.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region52 as exempt
cpu1.IDAU_REGION52.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region52 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION52.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region52 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION53.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region53 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION53.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region53
cpu1.IDAU_REGION53.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region53 as exempt
cpu1.IDAU_REGION53.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region53 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION53.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region53 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION54.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region54 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION54.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region54
cpu1.IDAU_REGION54.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region54 as exempt
cpu1.IDAU_REGION54.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region54 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION54.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region54 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION55.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region55 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION55.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region55
cpu1.IDAU_REGION55.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region55 as exempt
cpu1.IDAU_REGION55.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region55 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION55.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region55 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION56.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region56 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION56.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region56
cpu1.IDAU_REGION56.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region56 as exempt
cpu1.IDAU_REGION56.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region56 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION56.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region56 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION57.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region57 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION57.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region57
cpu1.IDAU_REGION57.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region57 as exempt
cpu1.IDAU_REGION57.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region57 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION57.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region57 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION58.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region58 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION58.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region58
cpu1.IDAU_REGION58.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region58 as exempt
cpu1.IDAU_REGION58.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region58 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION58.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region58 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION59.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region59 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION59.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region59
cpu1.IDAU_REGION59.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region59 as exempt
cpu1.IDAU_REGION59.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region59 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION59.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region59 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION60.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region60 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION60.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region60
cpu1.IDAU_REGION60.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region60 as exempt
cpu1.IDAU_REGION60.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region60 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION60.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region60 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION61.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region61 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION61.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region61
cpu1.IDAU_REGION61.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region61 as exempt
cpu1.IDAU_REGION61.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region61 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION61.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region61 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION62.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region62 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION62.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region62
cpu1.IDAU_REGION62.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region62 as exempt
cpu1.IDAU_REGION62.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region62 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION62.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region62 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION63.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region63 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION63.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region63
cpu1.IDAU_REGION63.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region63 as exempt
cpu1.IDAU_REGION63.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region63 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION63.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region63 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION64.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region64 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION64.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region64
cpu1.IDAU_REGION64.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region64 as exempt
cpu1.IDAU_REGION64.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region64 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION64.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region64 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION65.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region65 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION65.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region65
cpu1.IDAU_REGION65.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region65 as exempt
cpu1.IDAU_REGION65.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region65 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION65.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region65 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION66.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region66 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION66.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region66
cpu1.IDAU_REGION66.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region66 as exempt
cpu1.IDAU_REGION66.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region66 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION66.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region66 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION67.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region67 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION67.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region67
cpu1.IDAU_REGION67.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region67 as exempt
cpu1.IDAU_REGION67.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region67 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION67.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region67 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION68.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region68 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION68.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region68
cpu1.IDAU_REGION68.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region68 as exempt
cpu1.IDAU_REGION68.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region68 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION68.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region68 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION69.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region69 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION69.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region69
cpu1.IDAU_REGION69.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region69 as exempt
cpu1.IDAU_REGION69.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region69 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION69.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region69 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION70.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region70 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION70.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region70
cpu1.IDAU_REGION70.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region70 as exempt
cpu1.IDAU_REGION70.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region70 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION70.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region70 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION71.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region71 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION71.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region71
cpu1.IDAU_REGION71.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region71 as exempt
cpu1.IDAU_REGION71.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region71 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION71.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region71 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION72.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region72 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION72.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region72
cpu1.IDAU_REGION72.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region72 as exempt
cpu1.IDAU_REGION72.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region72 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION72.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region72 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION73.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region73 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION73.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region73
cpu1.IDAU_REGION73.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region73 as exempt
cpu1.IDAU_REGION73.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region73 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION73.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region73 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION74.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region74 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION74.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region74
cpu1.IDAU_REGION74.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region74 as exempt
cpu1.IDAU_REGION74.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region74 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION74.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region74 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION75.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region75 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION75.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region75
cpu1.IDAU_REGION75.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region75 as exempt
cpu1.IDAU_REGION75.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region75 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION75.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region75 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION76.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region76 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION76.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region76
cpu1.IDAU_REGION76.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region76 as exempt
cpu1.IDAU_REGION76.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region76 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION76.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region76 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION77.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region77 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION77.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region77
cpu1.IDAU_REGION77.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region77 as exempt
cpu1.IDAU_REGION77.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region77 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION77.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region77 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION78.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region78 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION78.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region78
cpu1.IDAU_REGION78.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region78 as exempt
cpu1.IDAU_REGION78.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region78 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION78.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region78 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION79.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region79 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION79.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region79
cpu1.IDAU_REGION79.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region79 as exempt
cpu1.IDAU_REGION79.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region79 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION79.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region79 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION80.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region80 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION80.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region80
cpu1.IDAU_REGION80.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region80 as exempt
cpu1.IDAU_REGION80.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region80 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION80.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region80 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION81.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region81 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION81.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region81
cpu1.IDAU_REGION81.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region81 as exempt
cpu1.IDAU_REGION81.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region81 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION81.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region81 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION82.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region82 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION82.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region82
cpu1.IDAU_REGION82.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region82 as exempt
cpu1.IDAU_REGION82.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region82 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION82.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region82 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION83.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region83 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION83.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region83
cpu1.IDAU_REGION83.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region83 as exempt
cpu1.IDAU_REGION83.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region83 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION83.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region83 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION84.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region84 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION84.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region84
cpu1.IDAU_REGION84.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region84 as exempt
cpu1.IDAU_REGION84.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region84 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION84.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region84 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION85.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region85 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION85.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region85
cpu1.IDAU_REGION85.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region85 as exempt
cpu1.IDAU_REGION85.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region85 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION85.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region85 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION86.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region86 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION86.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region86
cpu1.IDAU_REGION86.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region86 as exempt
cpu1.IDAU_REGION86.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region86 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION86.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region86 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION87.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region87 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION87.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region87
cpu1.IDAU_REGION87.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region87 as exempt
cpu1.IDAU_REGION87.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region87 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION87.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region87 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION88.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region88 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION88.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region88
cpu1.IDAU_REGION88.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region88 as exempt
cpu1.IDAU_REGION88.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region88 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION88.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region88 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION89.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region89 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION89.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region89
cpu1.IDAU_REGION89.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region89 as exempt
cpu1.IDAU_REGION89.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region89 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION89.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region89 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION90.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region90 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION90.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region90
cpu1.IDAU_REGION90.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region90 as exempt
cpu1.IDAU_REGION90.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region90 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION90.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region90 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION91.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region91 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION91.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region91
cpu1.IDAU_REGION91.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region91 as exempt
cpu1.IDAU_REGION91.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region91 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION91.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region91 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION92.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region92 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION92.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region92
cpu1.IDAU_REGION92.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region92 as exempt
cpu1.IDAU_REGION92.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region92 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION92.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region92 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION93.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region93 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION93.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region93
cpu1.IDAU_REGION93.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region93 as exempt
cpu1.IDAU_REGION93.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region93 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION93.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region93 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION94.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region94 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION94.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region94
cpu1.IDAU_REGION94.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region94 as exempt
cpu1.IDAU_REGION94.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region94 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION94.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region94 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION95.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region95 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION95.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region95
cpu1.IDAU_REGION95.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region95 as exempt
cpu1.IDAU_REGION95.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region95 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION95.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region95 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION96.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region96 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION96.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region96
cpu1.IDAU_REGION96.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region96 as exempt
cpu1.IDAU_REGION96.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region96 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION96.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region96 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION97.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region97 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION97.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region97
cpu1.IDAU_REGION97.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region97 as exempt
cpu1.IDAU_REGION97.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region97 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION97.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region97 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION98.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region98 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION98.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region98
cpu1.IDAU_REGION98.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region98 as exempt
cpu1.IDAU_REGION98.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region98 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION98.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region98 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION99.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region99 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION99.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region99
cpu1.IDAU_REGION99.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region99 as exempt
cpu1.IDAU_REGION99.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region99 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION99.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region99 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION100.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region100 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION100.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region100
cpu1.IDAU_REGION100.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region100 as exempt
cpu1.IDAU_REGION100.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region100 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION100.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region100 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION101.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region101 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION101.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region101
cpu1.IDAU_REGION101.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region101 as exempt
cpu1.IDAU_REGION101.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region101 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION101.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region101 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION102.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region102 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION102.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region102
cpu1.IDAU_REGION102.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region102 as exempt
cpu1.IDAU_REGION102.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region102 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION102.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region102 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION103.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region103 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION103.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region103
cpu1.IDAU_REGION103.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region103 as exempt
cpu1.IDAU_REGION103.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region103 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION103.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region103 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION104.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region104 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION104.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region104
cpu1.IDAU_REGION104.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region104 as exempt
cpu1.IDAU_REGION104.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region104 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION104.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region104 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION105.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region105 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION105.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region105
cpu1.IDAU_REGION105.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region105 as exempt
cpu1.IDAU_REGION105.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region105 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION105.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region105 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION106.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region106 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION106.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region106
cpu1.IDAU_REGION106.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region106 as exempt
cpu1.IDAU_REGION106.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region106 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION106.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region106 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION107.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region107 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION107.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region107
cpu1.IDAU_REGION107.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region107 as exempt
cpu1.IDAU_REGION107.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region107 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION107.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region107 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION108.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region108 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION108.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region108
cpu1.IDAU_REGION108.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region108 as exempt
cpu1.IDAU_REGION108.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region108 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION108.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region108 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION109.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region109 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION109.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region109
cpu1.IDAU_REGION109.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region109 as exempt
cpu1.IDAU_REGION109.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region109 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION109.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region109 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION110.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region110 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION110.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region110
cpu1.IDAU_REGION110.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region110 as exempt
cpu1.IDAU_REGION110.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region110 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION110.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region110 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION111.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region111 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION111.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region111
cpu1.IDAU_REGION111.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region111 as exempt
cpu1.IDAU_REGION111.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region111 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION111.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region111 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION112.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region112 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION112.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region112
cpu1.IDAU_REGION112.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region112 as exempt
cpu1.IDAU_REGION112.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region112 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION112.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region112 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION113.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region113 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION113.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region113
cpu1.IDAU_REGION113.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region113 as exempt
cpu1.IDAU_REGION113.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region113 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION113.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region113 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION114.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region114 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION114.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region114
cpu1.IDAU_REGION114.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region114 as exempt
cpu1.IDAU_REGION114.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region114 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION114.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region114 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION115.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region115 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION115.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region115
cpu1.IDAU_REGION115.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region115 as exempt
cpu1.IDAU_REGION115.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region115 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION115.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region115 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION116.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region116 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION116.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region116
cpu1.IDAU_REGION116.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region116 as exempt
cpu1.IDAU_REGION116.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region116 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION116.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region116 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION117.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region117 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION117.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region117
cpu1.IDAU_REGION117.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region117 as exempt
cpu1.IDAU_REGION117.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region117 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION117.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region117 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION118.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region118 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION118.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region118
cpu1.IDAU_REGION118.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region118 as exempt
cpu1.IDAU_REGION118.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region118 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION118.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region118 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION119.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region119 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION119.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region119
cpu1.IDAU_REGION119.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region119 as exempt
cpu1.IDAU_REGION119.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region119 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION119.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region119 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION120.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region120 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION120.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region120
cpu1.IDAU_REGION120.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region120 as exempt
cpu1.IDAU_REGION120.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region120 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION120.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region120 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION121.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region121 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION121.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region121
cpu1.IDAU_REGION121.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region121 as exempt
cpu1.IDAU_REGION121.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region121 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION121.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region121 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION122.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region122 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION122.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region122
cpu1.IDAU_REGION122.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region122 as exempt
cpu1.IDAU_REGION122.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region122 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION122.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region122 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION123.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region123 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION123.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region123
cpu1.IDAU_REGION123.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region123 as exempt
cpu1.IDAU_REGION123.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region123 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION123.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region123 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION124.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region124 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION124.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region124
cpu1.IDAU_REGION124.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region124 as exempt
cpu1.IDAU_REGION124.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region124 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION124.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region124 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION125.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region125 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION125.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region125
cpu1.IDAU_REGION125.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region125 as exempt
cpu1.IDAU_REGION125.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region125 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION125.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region125 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION126.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region126 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION126.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region126
cpu1.IDAU_REGION126.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region126 as exempt
cpu1.IDAU_REGION126.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region126 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION126.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region126 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION127.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region127 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION127.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region127
cpu1.IDAU_REGION127.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region127 as exempt
cpu1.IDAU_REGION127.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region127 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION127.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region127 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION128.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region128 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION128.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region128
cpu1.IDAU_REGION128.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region128 as exempt
cpu1.IDAU_REGION128.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region128 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION128.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region128 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION129.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region129 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION129.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region129
cpu1.IDAU_REGION129.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region129 as exempt
cpu1.IDAU_REGION129.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region129 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION129.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region129 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION130.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region130 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION130.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region130
cpu1.IDAU_REGION130.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region130 as exempt
cpu1.IDAU_REGION130.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region130 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION130.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region130 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION131.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region131 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION131.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region131
cpu1.IDAU_REGION131.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region131 as exempt
cpu1.IDAU_REGION131.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region131 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION131.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region131 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION132.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region132 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION132.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region132
cpu1.IDAU_REGION132.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region132 as exempt
cpu1.IDAU_REGION132.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region132 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION132.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region132 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION133.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region133 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION133.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region133
cpu1.IDAU_REGION133.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region133 as exempt
cpu1.IDAU_REGION133.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region133 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION133.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region133 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION134.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region134 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION134.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region134
cpu1.IDAU_REGION134.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region134 as exempt
cpu1.IDAU_REGION134.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region134 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION134.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region134 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION135.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region135 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION135.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region135
cpu1.IDAU_REGION135.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region135 as exempt
cpu1.IDAU_REGION135.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region135 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION135.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region135 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION136.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region136 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION136.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region136
cpu1.IDAU_REGION136.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region136 as exempt
cpu1.IDAU_REGION136.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region136 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION136.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region136 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION137.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region137 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION137.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region137
cpu1.IDAU_REGION137.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region137 as exempt
cpu1.IDAU_REGION137.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region137 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION137.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region137 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION138.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region138 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION138.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region138
cpu1.IDAU_REGION138.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region138 as exempt
cpu1.IDAU_REGION138.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region138 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION138.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region138 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION139.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region139 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION139.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region139
cpu1.IDAU_REGION139.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region139 as exempt
cpu1.IDAU_REGION139.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region139 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION139.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region139 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION140.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region140 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION140.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region140
cpu1.IDAU_REGION140.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region140 as exempt
cpu1.IDAU_REGION140.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region140 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION140.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region140 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION141.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region141 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION141.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region141
cpu1.IDAU_REGION141.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region141 as exempt
cpu1.IDAU_REGION141.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region141 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION141.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region141 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION142.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region142 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION142.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region142
cpu1.IDAU_REGION142.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region142 as exempt
cpu1.IDAU_REGION142.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region142 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION142.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region142 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION143.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region143 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION143.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region143
cpu1.IDAU_REGION143.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region143 as exempt
cpu1.IDAU_REGION143.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region143 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION143.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region143 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION144.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region144 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION144.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region144
cpu1.IDAU_REGION144.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region144 as exempt
cpu1.IDAU_REGION144.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region144 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION144.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region144 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION145.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region145 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION145.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region145
cpu1.IDAU_REGION145.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region145 as exempt
cpu1.IDAU_REGION145.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region145 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION145.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region145 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION146.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region146 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION146.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region146
cpu1.IDAU_REGION146.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region146 as exempt
cpu1.IDAU_REGION146.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region146 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION146.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region146 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION147.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region147 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION147.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region147
cpu1.IDAU_REGION147.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region147 as exempt
cpu1.IDAU_REGION147.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region147 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION147.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region147 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION148.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region148 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION148.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region148
cpu1.IDAU_REGION148.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region148 as exempt
cpu1.IDAU_REGION148.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region148 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION148.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region148 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION149.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region149 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION149.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region149
cpu1.IDAU_REGION149.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region149 as exempt
cpu1.IDAU_REGION149.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region149 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION149.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region149 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION150.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region150 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION150.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region150
cpu1.IDAU_REGION150.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region150 as exempt
cpu1.IDAU_REGION150.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region150 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION150.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region150 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION151.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region151 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION151.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region151
cpu1.IDAU_REGION151.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region151 as exempt
cpu1.IDAU_REGION151.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region151 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION151.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region151 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION152.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region152 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION152.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region152
cpu1.IDAU_REGION152.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region152 as exempt
cpu1.IDAU_REGION152.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region152 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION152.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region152 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION153.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region153 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION153.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region153
cpu1.IDAU_REGION153.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region153 as exempt
cpu1.IDAU_REGION153.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region153 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION153.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region153 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION154.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region154 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION154.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region154
cpu1.IDAU_REGION154.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region154 as exempt
cpu1.IDAU_REGION154.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region154 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION154.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region154 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION155.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region155 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION155.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region155
cpu1.IDAU_REGION155.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region155 as exempt
cpu1.IDAU_REGION155.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region155 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION155.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region155 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION156.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region156 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION156.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region156
cpu1.IDAU_REGION156.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region156 as exempt
cpu1.IDAU_REGION156.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region156 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION156.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region156 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION157.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region157 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION157.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region157
cpu1.IDAU_REGION157.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region157 as exempt
cpu1.IDAU_REGION157.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region157 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION157.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region157 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION158.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region158 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION158.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region158
cpu1.IDAU_REGION158.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region158 as exempt
cpu1.IDAU_REGION158.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region158 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION158.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region158 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION159.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region159 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION159.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region159
cpu1.IDAU_REGION159.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region159 as exempt
cpu1.IDAU_REGION159.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region159 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION159.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region159 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION160.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region160 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION160.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region160
cpu1.IDAU_REGION160.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region160 as exempt
cpu1.IDAU_REGION160.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region160 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION160.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region160 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION161.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region161 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION161.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region161
cpu1.IDAU_REGION161.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region161 as exempt
cpu1.IDAU_REGION161.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region161 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION161.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region161 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION162.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region162 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION162.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region162
cpu1.IDAU_REGION162.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region162 as exempt
cpu1.IDAU_REGION162.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region162 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION162.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region162 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION163.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region163 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION163.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region163
cpu1.IDAU_REGION163.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region163 as exempt
cpu1.IDAU_REGION163.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region163 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION163.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region163 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION164.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region164 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION164.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region164
cpu1.IDAU_REGION164.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region164 as exempt
cpu1.IDAU_REGION164.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region164 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION164.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region164 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION165.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region165 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION165.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region165
cpu1.IDAU_REGION165.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region165 as exempt
cpu1.IDAU_REGION165.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region165 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION165.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region165 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION166.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region166 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION166.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region166
cpu1.IDAU_REGION166.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region166 as exempt
cpu1.IDAU_REGION166.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region166 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION166.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region166 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION167.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region167 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION167.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region167
cpu1.IDAU_REGION167.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region167 as exempt
cpu1.IDAU_REGION167.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region167 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION167.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region167 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION168.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region168 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION168.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region168
cpu1.IDAU_REGION168.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region168 as exempt
cpu1.IDAU_REGION168.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region168 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION168.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region168 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION169.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region169 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION169.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region169
cpu1.IDAU_REGION169.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region169 as exempt
cpu1.IDAU_REGION169.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region169 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION169.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region169 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION170.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region170 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION170.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region170
cpu1.IDAU_REGION170.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region170 as exempt
cpu1.IDAU_REGION170.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region170 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION170.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region170 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION171.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region171 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION171.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region171
cpu1.IDAU_REGION171.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region171 as exempt
cpu1.IDAU_REGION171.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region171 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION171.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region171 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION172.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region172 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION172.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region172
cpu1.IDAU_REGION172.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region172 as exempt
cpu1.IDAU_REGION172.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region172 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION172.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region172 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION173.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region173 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION173.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region173
cpu1.IDAU_REGION173.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region173 as exempt
cpu1.IDAU_REGION173.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region173 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION173.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region173 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION174.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region174 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION174.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region174
cpu1.IDAU_REGION174.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region174 as exempt
cpu1.IDAU_REGION174.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region174 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION174.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region174 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION175.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region175 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION175.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region175
cpu1.IDAU_REGION175.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region175 as exempt
cpu1.IDAU_REGION175.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region175 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION175.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region175 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION176.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region176 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION176.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region176
cpu1.IDAU_REGION176.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region176 as exempt
cpu1.IDAU_REGION176.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region176 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION176.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region176 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION177.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region177 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION177.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region177
cpu1.IDAU_REGION177.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region177 as exempt
cpu1.IDAU_REGION177.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region177 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION177.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region177 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION178.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region178 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION178.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region178
cpu1.IDAU_REGION178.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region178 as exempt
cpu1.IDAU_REGION178.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region178 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION178.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region178 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION179.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region179 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION179.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region179
cpu1.IDAU_REGION179.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region179 as exempt
cpu1.IDAU_REGION179.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region179 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION179.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region179 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION180.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region180 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION180.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region180
cpu1.IDAU_REGION180.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region180 as exempt
cpu1.IDAU_REGION180.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region180 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION180.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region180 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION181.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region181 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION181.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region181
cpu1.IDAU_REGION181.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region181 as exempt
cpu1.IDAU_REGION181.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region181 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION181.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region181 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION182.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region182 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION182.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region182
cpu1.IDAU_REGION182.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region182 as exempt
cpu1.IDAU_REGION182.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region182 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION182.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region182 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION183.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region183 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION183.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region183
cpu1.IDAU_REGION183.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region183 as exempt
cpu1.IDAU_REGION183.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region183 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION183.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region183 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION184.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region184 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION184.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region184
cpu1.IDAU_REGION184.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region184 as exempt
cpu1.IDAU_REGION184.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region184 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION184.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region184 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION185.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region185 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION185.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region185
cpu1.IDAU_REGION185.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region185 as exempt
cpu1.IDAU_REGION185.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region185 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION185.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region185 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION186.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region186 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION186.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region186
cpu1.IDAU_REGION186.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region186 as exempt
cpu1.IDAU_REGION186.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region186 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION186.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region186 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION187.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region187 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION187.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region187
cpu1.IDAU_REGION187.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region187 as exempt
cpu1.IDAU_REGION187.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region187 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION187.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region187 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION188.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region188 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION188.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region188
cpu1.IDAU_REGION188.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region188 as exempt
cpu1.IDAU_REGION188.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region188 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION188.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region188 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION189.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region189 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION189.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region189
cpu1.IDAU_REGION189.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region189 as exempt
cpu1.IDAU_REGION189.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region189 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION189.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region189 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION190.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region190 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION190.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region190
cpu1.IDAU_REGION190.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region190 as exempt
cpu1.IDAU_REGION190.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region190 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION190.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region190 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION191.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region191 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION191.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region191
cpu1.IDAU_REGION191.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region191 as exempt
cpu1.IDAU_REGION191.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region191 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION191.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region191 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION192.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region192 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION192.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region192
cpu1.IDAU_REGION192.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region192 as exempt
cpu1.IDAU_REGION192.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region192 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION192.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region192 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION193.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region193 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION193.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region193
cpu1.IDAU_REGION193.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region193 as exempt
cpu1.IDAU_REGION193.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region193 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION193.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region193 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION194.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region194 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION194.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region194
cpu1.IDAU_REGION194.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region194 as exempt
cpu1.IDAU_REGION194.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region194 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION194.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region194 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION195.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region195 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION195.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region195
cpu1.IDAU_REGION195.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region195 as exempt
cpu1.IDAU_REGION195.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region195 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION195.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region195 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION196.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region196 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION196.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region196
cpu1.IDAU_REGION196.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region196 as exempt
cpu1.IDAU_REGION196.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region196 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION196.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region196 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION197.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region197 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION197.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region197
cpu1.IDAU_REGION197.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region197 as exempt
cpu1.IDAU_REGION197.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region197 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION197.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region197 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION198.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region198 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION198.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region198
cpu1.IDAU_REGION198.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region198 as exempt
cpu1.IDAU_REGION198.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region198 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION198.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region198 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION199.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region199 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION199.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region199
cpu1.IDAU_REGION199.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region199 as exempt
cpu1.IDAU_REGION199.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region199 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION199.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region199 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION200.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region200 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION200.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region200
cpu1.IDAU_REGION200.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region200 as exempt
cpu1.IDAU_REGION200.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region200 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION200.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region200 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION201.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region201 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION201.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region201
cpu1.IDAU_REGION201.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region201 as exempt
cpu1.IDAU_REGION201.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region201 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION201.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region201 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION202.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region202 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION202.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region202
cpu1.IDAU_REGION202.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region202 as exempt
cpu1.IDAU_REGION202.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region202 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION202.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region202 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION203.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region203 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION203.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region203
cpu1.IDAU_REGION203.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region203 as exempt
cpu1.IDAU_REGION203.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region203 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION203.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region203 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION204.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region204 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION204.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region204
cpu1.IDAU_REGION204.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region204 as exempt
cpu1.IDAU_REGION204.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region204 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION204.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region204 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION205.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region205 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION205.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region205
cpu1.IDAU_REGION205.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region205 as exempt
cpu1.IDAU_REGION205.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region205 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION205.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region205 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION206.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region206 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION206.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region206
cpu1.IDAU_REGION206.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region206 as exempt
cpu1.IDAU_REGION206.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region206 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION206.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region206 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION207.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region207 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION207.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region207
cpu1.IDAU_REGION207.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region207 as exempt
cpu1.IDAU_REGION207.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region207 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION207.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region207 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION208.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region208 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION208.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region208
cpu1.IDAU_REGION208.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region208 as exempt
cpu1.IDAU_REGION208.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region208 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION208.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region208 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION209.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region209 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION209.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region209
cpu1.IDAU_REGION209.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region209 as exempt
cpu1.IDAU_REGION209.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region209 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION209.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region209 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION210.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region210 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION210.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region210
cpu1.IDAU_REGION210.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region210 as exempt
cpu1.IDAU_REGION210.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region210 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION210.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region210 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION211.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region211 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION211.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region211
cpu1.IDAU_REGION211.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region211 as exempt
cpu1.IDAU_REGION211.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region211 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION211.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region211 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION212.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region212 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION212.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region212
cpu1.IDAU_REGION212.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region212 as exempt
cpu1.IDAU_REGION212.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region212 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION212.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region212 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION213.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region213 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION213.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region213
cpu1.IDAU_REGION213.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region213 as exempt
cpu1.IDAU_REGION213.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region213 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION213.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region213 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION214.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region214 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION214.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region214
cpu1.IDAU_REGION214.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region214 as exempt
cpu1.IDAU_REGION214.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region214 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION214.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region214 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION215.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region215 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION215.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region215
cpu1.IDAU_REGION215.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region215 as exempt
cpu1.IDAU_REGION215.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region215 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION215.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region215 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION216.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region216 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION216.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region216
cpu1.IDAU_REGION216.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region216 as exempt
cpu1.IDAU_REGION216.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region216 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION216.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region216 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION217.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region217 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION217.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region217
cpu1.IDAU_REGION217.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region217 as exempt
cpu1.IDAU_REGION217.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region217 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION217.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region217 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION218.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region218 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION218.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region218
cpu1.IDAU_REGION218.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region218 as exempt
cpu1.IDAU_REGION218.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region218 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION218.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region218 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION219.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region219 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION219.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region219
cpu1.IDAU_REGION219.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region219 as exempt
cpu1.IDAU_REGION219.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region219 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION219.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region219 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION220.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region220 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION220.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region220
cpu1.IDAU_REGION220.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region220 as exempt
cpu1.IDAU_REGION220.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region220 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION220.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region220 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION221.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region221 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION221.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region221
cpu1.IDAU_REGION221.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region221 as exempt
cpu1.IDAU_REGION221.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region221 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION221.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region221 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION222.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region222 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION222.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region222
cpu1.IDAU_REGION222.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region222 as exempt
cpu1.IDAU_REGION222.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region222 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION222.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region222 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION223.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region223 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION223.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region223
cpu1.IDAU_REGION223.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region223 as exempt
cpu1.IDAU_REGION223.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region223 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION223.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region223 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION224.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region224 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION224.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region224
cpu1.IDAU_REGION224.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region224 as exempt
cpu1.IDAU_REGION224.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region224 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION224.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region224 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION225.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region225 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION225.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region225
cpu1.IDAU_REGION225.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region225 as exempt
cpu1.IDAU_REGION225.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region225 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION225.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region225 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION226.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region226 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION226.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region226
cpu1.IDAU_REGION226.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region226 as exempt
cpu1.IDAU_REGION226.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region226 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION226.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region226 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION227.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region227 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION227.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region227
cpu1.IDAU_REGION227.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region227 as exempt
cpu1.IDAU_REGION227.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region227 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION227.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region227 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION228.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region228 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION228.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region228
cpu1.IDAU_REGION228.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region228 as exempt
cpu1.IDAU_REGION228.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region228 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION228.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region228 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION229.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region229 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION229.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region229
cpu1.IDAU_REGION229.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region229 as exempt
cpu1.IDAU_REGION229.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region229 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION229.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region229 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION230.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region230 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION230.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region230
cpu1.IDAU_REGION230.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region230 as exempt
cpu1.IDAU_REGION230.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region230 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION230.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region230 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION231.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region231 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION231.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region231
cpu1.IDAU_REGION231.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region231 as exempt
cpu1.IDAU_REGION231.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region231 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION231.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region231 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION232.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region232 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION232.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region232
cpu1.IDAU_REGION232.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region232 as exempt
cpu1.IDAU_REGION232.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region232 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION232.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region232 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION233.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region233 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION233.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region233
cpu1.IDAU_REGION233.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region233 as exempt
cpu1.IDAU_REGION233.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region233 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION233.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region233 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION234.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region234 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION234.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region234
cpu1.IDAU_REGION234.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region234 as exempt
cpu1.IDAU_REGION234.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region234 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION234.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region234 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION235.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region235 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION235.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region235
cpu1.IDAU_REGION235.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region235 as exempt
cpu1.IDAU_REGION235.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region235 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION235.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region235 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION236.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region236 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION236.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region236
cpu1.IDAU_REGION236.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region236 as exempt
cpu1.IDAU_REGION236.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region236 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION236.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region236 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION237.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region237 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION237.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region237
cpu1.IDAU_REGION237.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region237 as exempt
cpu1.IDAU_REGION237.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region237 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION237.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region237 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION238.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region238 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION238.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region238
cpu1.IDAU_REGION238.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region238 as exempt
cpu1.IDAU_REGION238.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region238 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION238.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region238 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION239.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region239 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION239.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region239
cpu1.IDAU_REGION239.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region239 as exempt
cpu1.IDAU_REGION239.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region239 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION239.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region239 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION240.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region240 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION240.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region240
cpu1.IDAU_REGION240.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region240 as exempt
cpu1.IDAU_REGION240.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region240 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION240.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region240 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION241.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region241 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION241.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region241
cpu1.IDAU_REGION241.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region241 as exempt
cpu1.IDAU_REGION241.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region241 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION241.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region241 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION242.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region242 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION242.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region242
cpu1.IDAU_REGION242.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region242 as exempt
cpu1.IDAU_REGION242.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region242 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION242.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region242 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION243.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region243 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION243.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region243
cpu1.IDAU_REGION243.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region243 as exempt
cpu1.IDAU_REGION243.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region243 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION243.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region243 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION244.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region244 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION244.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region244
cpu1.IDAU_REGION244.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region244 as exempt
cpu1.IDAU_REGION244.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region244 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION244.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region244 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION245.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region245 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION245.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region245
cpu1.IDAU_REGION245.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region245 as exempt
cpu1.IDAU_REGION245.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region245 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION245.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region245 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION246.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region246 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION246.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region246
cpu1.IDAU_REGION246.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region246 as exempt
cpu1.IDAU_REGION246.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region246 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION246.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region246 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION247.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region247 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION247.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region247
cpu1.IDAU_REGION247.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region247 as exempt
cpu1.IDAU_REGION247.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region247 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION247.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region247 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION248.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region248 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION248.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region248
cpu1.IDAU_REGION248.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region248 as exempt
cpu1.IDAU_REGION248.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region248 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION248.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region248 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION249.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region249 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION249.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region249
cpu1.IDAU_REGION249.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region249 as exempt
cpu1.IDAU_REGION249.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region249 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION249.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region249 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION250.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region250 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION250.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region250
cpu1.IDAU_REGION250.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region250 as exempt
cpu1.IDAU_REGION250.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region250 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION250.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region250 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION251.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region251 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION251.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region251
cpu1.IDAU_REGION251.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region251 as exempt
cpu1.IDAU_REGION251.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region251 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION251.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region251 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION252.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region252 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION252.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region252
cpu1.IDAU_REGION252.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region252 as exempt
cpu1.IDAU_REGION252.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region252 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION252.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region252 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION253.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region253 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION253.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region253
cpu1.IDAU_REGION253.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region253 as exempt
cpu1.IDAU_REGION253.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region253 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION253.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region253 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION254.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region254 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION254.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region254
cpu1.IDAU_REGION254.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region254 as exempt
cpu1.IDAU_REGION254.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region254 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION254.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region254 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION255.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region255 is S (absent if LADDR=0), 1 => NS or NSC or exempt.
cpu1.IDAU_REGION255.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region255
cpu1.IDAU_REGION255.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region255 as exempt
cpu1.IDAU_REGION255.BADDR=0x0 # (int , init-time) default = '0x0' : Base address of IDAU region255 : [0x0..0xFFFFFFFF]
cpu1.IDAU_REGION255.LADDR=0x0 # (int , init-time) default = '0x0' : Limit address of IDAU region255 : [0x0..0xFFFFFFFF]
cpu1.CPUID=0x0 # (int , init-time) default = '0x0' : Set SCS CPUID Base Register. If set to zero, a default CPUID is used. : [0x0..0xFFFFFFFF]
cpu1.supports_unprivileged=1 # (bool , init-time) default = '1' : Enable support for Unprivileged/Privileged Extension
cpu1.SYST=0x2 # (int , init-time) default = '0x2' : Include SysTick timer functionality (0=Absent, 1=Secure only, 2=Secure and NS) : [0x0..0x2]
cpu1.baseline=0 # (bool , init-time) default = '1' : When in v8-M mode, use the baseline profile (if false, use mainline)
cpu1.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu1.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu1.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu1.CPSPRESENT=0xFFFF # (int , init-time) default = '0xFFFF' : Bit N means external coprocessor N (CP15:CP0) is accessible in Secure state : [0x0..0xFFFF]
cpu1.CPNSPRESENT=0xFFFF # (int , init-time) default = '0xFFFF' : Bit N means external coprocessor N (CP15:CP0) is accessible in Non-Secure state : [0x0..0xFFFF]
cpu1.WIC=1 # (bool , init-time) default = '1' : Include support for WIC-mode deep sleep
cpu1.IRQDIS0=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+0] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS1=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+32] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS2=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+64] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS3=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+96] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS4=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+128] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS5=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+160] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS6=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+192] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS7=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+224] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS8=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+256] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS9=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+288] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS10=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+320] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS11=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+352] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS12=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+384] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS13=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+416] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS14=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+448] : [0x0..0xFFFFFFFF]
cpu1.IRQDIS15=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+480] : [0x0..0xFFFFFFFF]
cpu1.NVIC_ITNS0="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS1="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS2="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS3="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS4="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS5="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS6="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS7="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS8="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS9="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS10="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS11="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS12="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS13="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS14="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.NVIC_ITNS15="" # (string, init-time) default = '' : Each character fixes a security state target for a given external interrupt. 'N' implies NS; 'S' implies S; anything else is ignored. The largest bit is first, e.g. 'S-NN' sets external interrupts 0 and 1 to non-secure, 2 remains settable via the NVIC_ITNS register and 3 always targets secure
cpu1.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu1.cpu_can_access_debug_regs=1 # (bool , init-time) default = '1' : The DWT, BPU, ROM table, DCB, and the SHCSR and DFSR registers access from the processor
cpu1.stack_limit_check=0x3 # (int , init-time) default = '0x3' : Support Stack limit Check on Load instructions (0:Only v6M, 1:Exclusives from ARMv7-M, 2:Semaphores and atomics from ARMv8-A/R, 3:Both #1 and #2 : [0x0..0x3]
cpu1.stack_limit_check_optimization=1 # (bool , init-time) default = '1' : Stack limit check optimization (0: limit check done for each word on the stack, 1: limit check done only on stack pointer
cpu1.sequential_security_transitions=0x1 # (int , init-time) default = '0x1' : Allow transition of security state in sequential instruction fetches that cross from non-secure to secure memory with SG instruction 0: never, 1: always, 2: 32-bit instrs, 3: ISB. : [0x0..0x3]
cpu1.bp_on_2nd_halfword=1 # (bool , init-time) default = '1' : Respect DWT/BPU breakpoint-hit on 2nd halfword of 32-bit instruction
cpu1.condition_flags_reset=0x0 # (int , init-time) default = '0x0' : Reset Value of condition flags in APSR : [0x0..0xF]
cpu1.ID_ISAR0.coproc_instrs=0x4 # (int , init-time) default = '0x4' : Supported Coprocessor instructions 0: None 1: CDP, LDC, MCR, MRC, and STC instructions 2: As for 1, and CDP2, LDC2, MCR2, MRC2, and STC2 instructions 3: As for 2, and MCRR and MRRC instructions 4: As for 2, and MCRR and MRRC instructions : [0x0..0x4]
cpu1.ID_ISAR1.interwork_instrs=0x3 # (int , init-time) default = '0x3' : level of support for Interworking instructions : [0x0..0x3]
cpu1.ID_ISAR1.extend_instrs=0x2 # (int , init-time) default = '0x2' : level of support for extend instructions, under the control of support_dsp_ext : [0x0..0x2]
cpu1.ID_ISAR2.multU_instrs=0x2 # (int , init-time) default = '0x2' : level of support for advanced unsigned Multiply instructions, under the control of support_dsp_ext : [0x0..0x2]
cpu1.ID_ISAR2.multS_instrs=0x3 # (int , init-time) default = '0x3' : level of support for advanced signed Multiply instructions, under the control of support_dsp_ext : [0x0..0x3]
cpu1.ID_ISAR3.SIMD_instrs=0x3 # (int , init-time) default = '0x3' : level of support for SIMD instructions, under the control of support_dsp_ext : [0x0..0x3]
cpu1.ID_ISAR3.saturate_instrs=0x1 # (int , init-time) default = '0x1' : level of support for saturate instructions, under the control of support_dsp_ext : [0x0..0x1]
cpu1.ID_ISAR3.synchprim_instrs=0x2 # (int , init-time) default = '0x2' : level of support for synchronization primitives ID_ISAR3 : [0x0..0x2]
cpu1.ID_ISAR4.unpriv_instrs=0x2 # (int , init-time) default = '0x2' : supported unprivileged instructions 0: None 1: LDRBT, LDRT, STRBT, and STRT instructions 2: As for 1, and LDRHT, LDRSBT, LDRSHT, and STRHT instructions : [0x0..0x2]
cpu1.ID_ISAR4.withshifts_instrs=0x4 # (int , init-time) default = '0x4' : level of support for instructions with shifts : [0x0..0x4]
cpu1.ID_ISAR4.synchPrim_instrs_frac=0x0 # (int , init-time) default = '0x0' : level of support for synchronization primitives ID_ISAR4 : [0x0..0x3]
cpu1.MVFR1.fp_hpfp=0x2 # (int , init-time) default = '0x2' : FP extension implements half-precision and double-precision floating-point conversion instructions; 0x1: half-precision and single precision 1: As for 0x1, and also supports conversion between half-precision and double-precision : [0x1..0x2]
cpu1.tail_chain=1 # (bool , init-time) default = '1' : Enable tail-chaining optimisation
cpu1.late_arrival=1 # (bool , init-time) default = '1' : Enable late arrival support
cpu1.IOP=0 # (bool , init-time) default = '0' : Send all d-side transactions to the port, io_port_out. Transactions which do not match should be returned to the port, io_port_in
cpu1.ID_MMFR0.Auxiliary_registers=1 # (bool , init-time) default = '1' : Auxiliary registers bits in ID_MMFR0, indicate the support for Auxiliary registers
cpu1.ID_MMFR0.Outermost_shareability=0x0 # (int , init-time) default = '0x0' : Outermost shareability bits in ID_MMFR0, indicate the outermost shareability domain implemented : [0x0..0xF]
cpu1.AIRCR.PRIS_writable=1 # (bool , init-time) default = '1' : Is AIRCR.BFHFNMINS bit[13] writeable
cpu1.AIRCR.BFHFNMINS_writable=1 # (bool , init-time) default = '1' : Is AIRCR.PRIS bit[14] writeable
cpu1.AIRCR.VECTCLRACTIVE_changes_mode=1 # (bool , init-time) default = '1' : Asserting AIRCR.VECTCLRACTIVE clears IPSR and any active exceptions. The mode is also changed to thread if this flag is true. Ignored for v8-M
cpu1.vector_fetch_as_wpt_event=0 # (bool , init-time) default = '0' : Watchpoint on exception vector fetch
cpu1.vector_fetch_on_iside=1 # (bool , init-time) default = '1' : Perform vector fetch on I-side
cpu1.CCR.BP=1 # (bool , init-time) default = '1' : Reset value of the Configuration and Control Register's branch prediction enable bit
cpu1.CCR.BP_writable=0 # (bool , init-time) default = '0' : Whether it is possible to modify the Configuration and Control Register's branch prediction enable bit
cpu1.ignore-SCR.SLEEPONEXIT=0 # (bool , init-time) default = '0' : Never sleep on exit from handler to thread mode.
cpu1.register_reset_data=0x0 # (int , init-time) default = '0x0' : Data used to fill register bits when they become UNKNOWN at reset. : [0x0..0xFFFFFFFF]
cpu1.write_unknown_regs_at_exception=0 # (bool , init-time) default = '0' : Do we write registers when they become UNKNOWN at exception or exception-return.
cpu1.unknown_regs_at_exception_value=0x0 # (int , init-time) default = '0x0' : Data used to fill registers when they become UNKNOWN at exception and exception-return. : [0x0..0xFFFFFFFF]
cpu1.ignore_unpred_SBZSBO=0 # (bool , init-time) default = '0' : Use smaller decoder does not UNDEF some unpredicable SBZ/SBO fields.
cpu1.ignore_unpred_ZeroRegistersInList=0 # (bool , init-time) default = '0' : VLDM,VSTM,STM,LDM with no registers NOP instead of UNDEF.
cpu1.unpred_msr_psr_with_zero_mask_is_nop=0 # (bool , init-time) default = '0' : If true, MSR to *PSR with a zero mask does nothing.
cpu1.unpred_msr_psr_with_one_mask_and_nodsp_is_nop=1 # (bool , init-time) default = '1' : If true, MSR to *PSR with a one mask and no DSP does nothing.
cpu1.abort_unaligned_nonNormal=1 # (bool , init-time) default = '1' : If true, UNPREDICTABLE accesses of device and strongly ordered memory abort; if false they are allowed.
cpu1.has_ahbp=1 # (bool , init-time) default = '1' : Are Vendor-Sys accesses sent to a separate bus (AHBP on CM7).
cpu1.has_separate_etm_reset=0 # (bool , init-time) default = '0' : If true, signal 'etmreset' resets the core, else the core power-on-reset does
cpu1.share_fault_address_reg=0 # (bool , init-time) default = '0' : If true, Fault Address Register is shared
cpu1.clear_non_secure_EXC_RETURN.ES_on_tailchain=1 # (bool , init-time) default = '1' : Clear EXC_RETURN.ES in LR value on entry to a tail-chained exception when returning from Non-secure state
fvp_mps2.SCC_ID.AN=0x0 # (int , init-time) default = '0x0' : SCC_ID[15:4], Primary part number i.e. Application Note number : [0x0..0xFFF]
fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu0 in reset at boot
fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.IDAU_REGION10.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION10.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION10.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION10.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION11.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION11.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION11.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION11.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION12.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION12.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION12.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION12.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION13.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION13.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION13.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION13.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION14.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION14.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION14.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION14.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION15.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION15.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION15.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION15.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION16.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION16.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION16.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION16.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION17.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION17.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION17.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION17.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION18.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION18.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION18.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION18.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION19.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION19.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION19.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION19.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION20.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION20.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION20.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION20.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION21.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION21.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION21.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION21.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION22.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION22.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION22.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION22.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION23.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION23.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION23.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION23.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION24.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION24.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION24.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION24.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION25.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION25.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION25.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION25.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION26.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION26.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION26.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION26.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION27.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION27.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION27.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION27.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION28.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION28.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION28.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION28.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION29.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION29.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION29.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION29.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION30.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION30.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION30.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION30.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION31.ENABLE=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION31.NSC=0 # (bool , init-time) default = '0' :
fvp_mps2.IDAU_REGION31.BADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.IDAU_REGION31.LADDR=0x0 # (int , init-time) default = '0x0' :
fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address
fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
aborting_warning_memory.read_data=0x0 # (int , init-time) default = '0x0' : Data to return on reads, if not aborting
#----------------------------------------------------------------------------------------------
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