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92 lines
3.3 KiB
C
92 lines
3.3 KiB
C
/*
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* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* This file is derivative of CMSIS system_ARMCM85.c
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* Git SHA: 61ad1303bc50450130cfb540caa384875a260b91
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*/
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#include "SSE310MPS3.h"
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define XTAL (32000000UL)
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#define SYSTEM_CLOCK (XTAL)
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#define PERIPHERAL_CLOCK (25000000UL)
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/*----------------------------------------------------------------------------
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Exception / Interrupt Vector table
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*----------------------------------------------------------------------------*/
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extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
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/*----------------------------------------------------------------------------
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System Core Clock Variable
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = SYSTEM_CLOCK;
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uint32_t PeripheralClock = PERIPHERAL_CLOCK;
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/*----------------------------------------------------------------------------
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System Core Clock update function
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void)
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{
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SystemCoreClock = SYSTEM_CLOCK;
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PeripheralClock = PERIPHERAL_CLOCK;
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}
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/*----------------------------------------------------------------------------
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System initialization function
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*----------------------------------------------------------------------------*/
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void SystemInit (void)
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{
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#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
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SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
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#endif
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/* Set CPDLPSTATE.RLPSTATE to 0
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Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.
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Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */
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PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |
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PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |
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PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk );
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#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
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(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
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SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
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(3U << 11U*2U) ); /* enable CP11 Full Access */
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/* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
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/* PDEPU ON, Clock OFF */
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PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
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#endif
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#ifdef UNALIGNED_SUPPORT_DISABLE
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SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
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#endif
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/* Enable Loop and branch info cache */
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SCB->CCR |= SCB_CCR_LOB_Msk;
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/* Enable Branch Prediction */
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SCB->CCR |= SCB_CCR_BP_Msk;
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__DSB();
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__ISB();
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}
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