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443 lines
18 KiB
ArmAsm
443 lines
18 KiB
ArmAsm
/******************************************************************************
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* @file startup_ARMCR8.c
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* @brief Unvalidated Startup File for a Cortex-R8 Device
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******************************************************************************/
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/*
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* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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// MPU region defines
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// Protection Base Address Register
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#define Execute_Never 0b1 // Bit 0
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#define RW_Access 0b01 // AP[2:1]
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#define RO_Access 0b11
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#define Non_Shareable 0b00 // SH[1:0]
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#define Outer_Shareable 0x10
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#define Inner_Shareable 0b11
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// Protection Limit Address Register
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#define ENable 0b1 // Bit 0
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#define AttrIndx0 0b000 // AttrIndx[2:0]
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#define AttrIndx1 0b001
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#define AttrIndx2 0b010
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#define AttrIndx3 0b011
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#define AttrIndx4 0b100
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#define AttrIndx5 0b101
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#define AttrIndx6 0b110
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#define AttrIndx7 0b111
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//----------------------------------------------------------------
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// Define some values
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#define Mode_USR 0x10
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#define Mode_FIQ 0x11
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#define Mode_IRQ 0x12
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#define Mode_SVC 0x13
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#define Mode_MON 0x16
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#define Mode_ABT 0x17
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#define Mode_UND 0x1B
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#define Mode_SYS 0x1F
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#define Mode_HYP 0x1A
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#define I_Bit 0x80 // when I bit is set, IRQ is disabled
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#define F_Bit 0x40 // when F bit is set, FIQ is disabled
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// Initial Setup & Entry point
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//----------------------------------------------------------------
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.eabi_attribute Tag_ABI_align8_preserved,1
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.section VECTORS,"ax"
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.align 3
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.global Reset_Handler
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Reset_Handler:
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// Reset Handlers (EL1 and EL2)
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//----------------------------------------------------------------
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EL2_Reset_Handler:
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.global Image$$ARM_LIB_STACKHEAP$$ZI$$Limit
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LDR SP, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit
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//----------------------------------------------------------------
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// Disable MPU and caches
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//----------------------------------------------------------------
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// Disable MPU and cache in case it was left enabled from an earlier run
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// This does not need to be done from a cold reset
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MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
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BIC r0, r0, #0x05 // Disable MPU (M bit) and data cache (C bit)
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BIC r0, r0, #0x1000 // Disable instruction cache (I bit)
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DSB // Ensure all previous loads/stores have completed
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MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
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ISB // Ensure subsequent insts execute wrt new MPU settings
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//----------------------------------------------------------------
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// Cache invalidation. However Cortex-R52 provides CFG signals to
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// invalidate cache automatically out of reset (CFGL1CACHEINVDISx)
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//----------------------------------------------------------------
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DSB // Complete all outstanding explicit memory operations
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MOV r0, #0
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MCR p15, 0, r0, c7, c5, 0 // Invalidate entire instruction cache
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// Invalidate Data/Unified Caches
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MRC p15, 1, r0, c0, c0, 1 // Read CLIDR
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ANDS r3, r0, #0x07000000 // Extract coherency level
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MOV r3, r3, LSR #23 // Total cache levels << 1
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BEQ Finished // If 0, no need to clean
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MOV r10, #0 // R10 holds current cache level << 1
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Loop1: ADD r2, r10, r10, LSR #1 // R2 holds cache "Set" position
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MOV r1, r0, LSR r2 // Bottom 3 bits are the Cache-type for this level
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AND r1, r1, #7 // Isolate those lower 3 bits
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CMP r1, #2
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BLT Skip // No cache or only instruction cache at this level
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MCR p15, 2, r10, c0, c0, 0 // Write the Cache Size selection register
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ISB // ISB to sync the change to the CacheSizeID reg
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MRC p15, 1, r1, c0, c0, 0 // Reads current Cache Size ID register
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AND r2, r1, #7 // Extract the line length field
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ADD r2, r2, #4 // Add 4 for the line length offset (log2 16 bytes)
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LDR r4, =0x3FF
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ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned)
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CLZ r5, r4 // R5 is the bit position of the way size increment
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LDR r7, =0x7FFF
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ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned)
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Loop2: MOV r9, r4 // R9 working copy of the max way size (right aligned)
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#ifdef __THUMB__
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Loop3: LSL r12, r9, r5
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ORR r11, r10, r12 // Factor in the Way number and cache number into R11
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LSL r12, r7, r2
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ORR r11, r11, r12 // Factor in the Set number
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#else
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Loop3: ORR r11, r10, r9, LSL r5 // Factor in the Way number and cache number into R11
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ORR r11, r11, r7, LSL r2 // Factor in the Set number
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#endif
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MCR p15, 0, r11, c7, c6, 2 // Invalidate by Set/Way
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SUBS r9, r9, #1 // Decrement the Way number
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BGE Loop3
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SUBS r7, r7, #1 // Decrement the Set number
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BGE Loop2
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Skip: ADD r10, r10, #2 // Increment the cache number
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CMP r3, r10
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BGT Loop1
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Finished:
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//----------------------------------------------------------------
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// TCM Configuration
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//----------------------------------------------------------------
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// Cortex-R52 optionally provides three Tightly-Coupled Memory (TCM) blocks (ATCM, BTCM and CTCM)
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// for fast access to code or data.
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// The following illustrates basic TCM configuration, as the basis for exploration by the user
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#ifdef TCM
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MRC p15, 0, r0, c0, c0, 2 // Read TCM Type Register
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// r0 now contains TCM availability
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MRC p15, 0, r0, c9, c1, 0 // Read ATCM Region Register
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// r0 now contains ATCM size in bits [5:2]
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LDR r0, =Image$$CODE$$Base // Set ATCM base address
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ORR r0, r0, #3 // Enable it
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MCR p15, 0, r0, c9, c1, 0 // Write ATCM Region Register
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MRC p15, 0, r0, c9, c1, 1 // Read BTCM Region Register
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// r0 now contains BTCM size in bits [5:2]
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LDR r0, =Image$$DATA$$Base // Set BTCM base address
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ORR r0, r0, #3 // Enable it
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MCR p15, 0, r0, c9, c1, 1 // Write BTCM Region Register
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MRC p15, 0, r0, c9, c1, 2 // Read CTCM Region Register
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// r0 now contains CTCM size in bits [5:2]
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LDR r0, =Image$$CTCM$$Base // Set CTCM base address
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ORR r0, r0, #1 // Enable it
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MCR p15, 0, r0, c9, c1, 2 // Write CTCM Region Register
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#endif
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//----------------------------------------------------------------
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// MPU Configuration
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//----------------------------------------------------------------
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// Notes:
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// * Regions apply to both instruction and data accesses.
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// * Each region base address must be a multiple of its size
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// * Any address range not covered by an enabled region will abort
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// * The region at 0x0 over the Vector table is needed to support semihosting
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// Region 0: Code Base = See scatter file Limit = Based on usage Normal Non-shared Read-only Executable
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// Region 1: Data Base = See scatter file Limit = Based on usage Normal Non-shared Full access Not Executable
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// Region 2: Stack/Heap Base = See scatter file Limit = Based on usage Normal Non-shared Full access Not Executable
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// Region 3: Peripherals Base = 0xB0000000 Limit = 0xBFFFFFC0 Device Full access Not Executable
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// Region 4: ATCM Base = Configurable Limit = Based on usage Normal Non-shared Full access Executable
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// Region 5: BTCM Base = Configurable Limit = Based on usage Normal Non-shared Full access Executable
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// Region 6: CTCM Base = Configurable Limit = Based on usage Normal Non-shared Full access Executable
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LDR r0, =64
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// Region 0 - Code
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REG0:
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LDR r1, =Image$$CODE$$Base
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LDR r2, =((Non_Shareable<<3) | (RO_Access<<1))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c8, 0 // write PRBAR0
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LDR r1, =Image$$CODE$$Limit
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ADD r1, r1, #63
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BFC r1, #0, #6 // align Limit to 64bytes
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LDR r2, =((AttrIndx0<<1) | (ENable))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c8, 1 // write PRLAR0
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// Region 1 - Data
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REG1:
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LDR r1, =Image$$DATA$$Base
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LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c8, 4 // write PRBAR1
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LDR r1, =Image$$DATA$$ZI$$Limit
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ADD r1, r1, #63
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BFC r1, #0, #6 // align Limit to 64bytes
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LDR r2, =((AttrIndx0<<1) | (ENable))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c8, 5 // write PRLAR1
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// Region 2 - Stack-Heap
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REG2:
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LDR r1, =Image$$ARM_LIB_STACKHEAP$$Base
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LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c9, 0 // write PRBAR2
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LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit
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ADD r1, r1, #63
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BFC r1, #0, #6 // align Limit to 64bytes
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LDR r2, =((AttrIndx0<<1) | (ENable))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c9, 1 // write PRLAR2
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// Region 3 - Peripherals
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REG3:
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LDR r1, =0xAA000000
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LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c9, 4 // write PRBAR3
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LDR r1, =0xBFFFFFC0
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ADD r1, r1, #63
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BFC r1, #0, #6 // align Limit to 64bytes
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LDR r2, =((AttrIndx0<<1) | (ENable))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c9, 5 // write PRLAR3
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#ifdef TCM
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// Region 4 - ATCM
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LDR r1, =Image$$ATCM$$Base
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LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c10, 0 // write PRBAR4
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LDR r1, =Image$$ATCM$$Limit
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ADD r1, r1, #63
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BFC r1, #0, #6 // align Limit to 64bytes
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LDR r2, =((AttrIndx1<<1) | (ENable))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c10, 1 // write PRLAR4
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// Region 5 - BTCM
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LDR r1, =Image$$BTCM$$Base
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LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c10, 4 // write PRBAR5
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LDR r1, =Image$$BTCM$$Limit
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ADD r1, r1, #63
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BFC r1, #0, #6 // align Limit to 64bytes
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LDR r2, =((AttrIndx0<<1) | (ENable))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c10, 5 // write PRLAR5
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// Region 6 - CTCM
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LDR r1, =Image$$CTCM$$Base
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LDR r2, =((Non_Shareable<<3) | (RW_Access<<1))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c11, 0 // write PRBAR6
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LDR r1, =Image$$CTCM$$Limit
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ADD r1, r1, #63
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BFC r1, #0, #6 // align Limit to 64bytes
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LDR r2, =((AttrIndx0<<1) | (ENable))
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ORR r1, r1, r2
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MCR p15, 0, r1, c6, c11, 1 // write PRLAR6
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#endif
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other_mems_en:
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// Enable PERIPHREGIONR (LLPP)
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mrc p15, 0, r1, c15, c0, 0 // PERIPHREGIONR
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orr r1, r1, #(0x1 << 1) // Enable PERIPHREGIONR EL2
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orr r1, r1, #(0x1) // Enable PERIPHREGIONR EL10
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mcr p15, 0, r1, c15, c0, 0 // PERIPHREGIONR
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//#ifdef __ARM_FP
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//----------------------------------------------------------------
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// Enable access to VFP by enabling access to Coprocessors 10 and 11.
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// Enables Full Access i.e. in both privileged and non privileged modes
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//----------------------------------------------------------------
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MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR)
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ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11
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MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR)
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ISB
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//----------------------------------------------------------------
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// Switch on the VFP hardware
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//----------------------------------------------------------------
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MOV r0, #0x40000000
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VMSR FPEXC, r0 // Write FPEXC register, EN bit set
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//#endif
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//----------------------------------------------------------------
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// Enable MPU and branch to C library init
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// Leaving the caches disabled until after scatter loading.
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//----------------------------------------------------------------
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MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
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ORR r0, r0, #0x01 // Set M bit to enable MPU
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DSB // Ensure all previous loads/stores have completed
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MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
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ISB // Ensure subsequent insts execute wrt new MPU settings
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//Check which CPU I am
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MRC p15, 0, r0, c0, c0, 5 // Read MPIDR
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ANDS r0, r0, 0xF
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BEQ cpu0 // If CPU0 then initialise C runtime
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CMP r0, #1
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BEQ loop_wfi // If CPU1 then jump to loop_wfi
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CMP r0, #2
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BEQ loop_wfi // If CPU2 then jump to loop_wfi
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CMP r0, #3
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BEQ loop_wfi // If CPU3 then jump to loop_wfi
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error:
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B error // else.. something is wrong
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loop_wfi:
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DSB SY // Clear all pending data accesses
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WFI // Go to sleep
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B loop_wfi
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cpu0:
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// Branch to __main
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//------------------------
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.global __main
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B __main
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//----------------------------------------------------------------
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// Global Enable for Instruction and Data Caching
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//----------------------------------------------------------------
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.global enable_caches
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.type enable_caches, "function"
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.cfi_startproc
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enable_caches:
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MRC p15, 4, r0, c1, c0, 0 // read System Control Register
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ORR r0, r0, #(0x1 << 12) // Set I bit 12 to enable I Cache
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ORR r0, r0, #(0x1 << 2) // Set C bit 2 to enable D Cache
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MCR p15, 4, r0, c1, c0, 0 // write System Control Register
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ISB
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BX lr
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.cfi_endproc
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.size enable_caches, . - enable_caches
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// Exception Vector Table & Handlers
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//----------------------------------------------------------------
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EL2_Vectors:
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LDR PC, EL2_Reset_Addr
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LDR PC, EL2_Undefined_Addr
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LDR PC, EL2_HVC_Addr
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LDR PC, EL2_Prefetch_Addr
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LDR PC, EL2_Abort_Addr
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LDR PC, EL2_HypModeEntry_Addr
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LDR PC, EL2_IRQ_Addr
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LDR PC, EL2_FIQ_Addr
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EL2_Reset_Addr: .word EL2_Reset_Handler
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EL2_Undefined_Addr: .word EL2_Undefined_Handler
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EL2_HVC_Addr: .word EL2_HVC_Handler
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EL2_Prefetch_Addr: .word EL2_Prefetch_Handler
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EL2_Abort_Addr: .word EL2_Abort_Handler
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EL2_HypModeEntry_Addr: .word EL2_HypModeEntry_Handler
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EL2_IRQ_Addr: .word EL2_IRQ_Handler
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EL2_FIQ_Addr: .word EL2_FIQ_Handler
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EL2_Undefined_Handler: B EL2_Undefined_Handler
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EL2_HVC_Handler: B EL2_HVC_Handler
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EL2_Prefetch_Handler: B EL2_Prefetch_Handler
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EL2_Abort_Handler: B EL2_Abort_Handler
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EL2_HypModeEntry_Handler: B EL2_HypModeEntry_Handler
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EL2_IRQ_Handler: B EL2_IRQ_Handler
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EL2_FIQ_Handler: B EL2_FIQ_Handler
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EL1_Vectors:
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LDR PC, EL1_Reset_Addr
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LDR PC, EL1_Undefined_Addr
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LDR PC, EL1_SVC_Addr
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LDR PC, EL1_Prefetch_Addr
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LDR PC, EL1_Abort_Addr
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LDR PC, EL1_Reserved
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LDR PC, EL1_IRQ_Addr
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LDR PC, EL1_FIQ_Addr
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EL1_Reset_Addr: .word EL1_Reset_Handler
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EL1_Undefined_Addr: .word EL1_Undefined_Handler
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EL1_SVC_Addr: .word EL1_SVC_Handler
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EL1_Prefetch_Addr: .word EL1_Prefetch_Handler
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EL1_Abort_Addr: .word EL1_Abort_Handler
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EL1_Reserved_Addr: .word EL1_Reserved
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EL1_IRQ_Addr: .word EL1_IRQ_Handler
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EL1_FIQ_Addr: .word EL1_FIQ_Handler
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EL1_Reset_Handler: B EL1_Reset_Handler
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EL1_Undefined_Handler: B EL1_Undefined_Handler
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EL1_SVC_Handler: B EL1_SVC_Handler
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EL1_Prefetch_Handler: B EL1_Prefetch_Handler
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EL1_Abort_Handler: B EL1_Abort_Handler
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EL1_Reserved: B EL1_Reserved
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EL1_IRQ_Handler: B EL1_IRQ_Handler
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EL1_FIQ_Handler: B EL1_FIQ_Handler |