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423 lines
17 KiB
C
423 lines
17 KiB
C
/**
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******************************************************************************
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* @file py32f403_hal_ctc.h
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* @author MCU Application Team
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* @brief Header file of CTC HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2023 Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by Puya under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef PY32F403_HAL_CTC_H
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#define PY32F403_HAL_CTC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "py32f403_hal_def.h"
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/** @addtogroup PY32F403_HAL_Driver
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* @{
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*/
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/** @addtogroup CTC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup CTC_Exported_Types CTC Exported Types
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* @{
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*/
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/**
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* @brief CTC Init Structure definition
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*/
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typedef struct
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{
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uint32_t AutoTrim; /*!< CTC Auto Trim Mode
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This parameter can be a value of @ref CTC_AUTO_TRIM */
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uint32_t LimitValue; /*!< Base time limit for clock calibration
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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uint32_t ReloadValue; /*!< CTC counter overload value
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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uint32_t RefCLKSource; /*!< CTC Input Reference Clock
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This parameter can be a value of @ref CTC_Ref_Clock_Source */
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uint32_t RefCLKDivider; /*!< The Reference Clock divider
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This parameter can be a value of @ref CTC_Ref_Clock_Divider */
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uint32_t RefCLKPolarity; /*!< The Reference Clock steady state
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This parameter can be a value of @ref CTC_Ref_Clock_Polarity */
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} CTC_InitTypeDef;
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/**
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* @brief HAL CTC Callback ID structure definition
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*/
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typedef enum
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{
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HAL_CTC_CKOK_CB_ID = 0x00U, /*!< clock trim OK */
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HAL_CTC_CKWARN_CB_ID = 0x01U, /*!< clock trim warning */
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HAL_CTC_ERR_CB_ID = 0x02U, /*!< clock trim error */
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HAL_CTC_EREF_CB_ID = 0x03U, /*!< clock trim expect reference */
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}HAL_CTC_CallbackIDTypeDef;
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/**
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* @brief HAL State structures definition
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*/
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typedef enum
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{
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HAL_CTC_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
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HAL_CTC_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
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HAL_CTC_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
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HAL_CTC_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
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HAL_CTC_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
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} HAL_CTC_StateTypeDef;
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/**
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* @brief CTC handle Structure definition
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*/
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typedef struct __CTC_HandleTypeDef
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{
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CTC_TypeDef *Instance; /*!< Register base address */
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CTC_InitTypeDef Init; /*!< CTC communication parameters */
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HAL_LockTypeDef Lock; /*!< CTC locking object */
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__IO HAL_CTC_StateTypeDef State; /*!< CTC operation state */
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#if (USE_HAL_CTC_REGISTER_CALLBACKS == 1U)
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void (* MspInitCallback)(struct __CTC_HandleTypeDef * hctc); /*!< CTC Msp Init Callback */
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void (* MspDeInitCallback)(struct __CTC_HandleTypeDef * hctc); /*!< CTC Msp DeInit Callback */
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void (* CKOKCallback)(struct __CTC_HandleTypeDef * hctc); /*!< CTC clock trim OK callback */
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void (* CKWARNCallback)(struct __CTC_HandleTypeDef * hctc); /*!< CTC clock trim warning callback */
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void (* ERRCallback)(struct __CTC_HandleTypeDef * hctc); /*!< CTC clock trim error callback */
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void (* EREFCallback)(struct __CTC_HandleTypeDef * hctc); /*!< CTC clock trim expect reference callback */
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#endif /* USE_HAL_CTC_REGISTER_CALLBACKS */
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} CTC_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CTC_Exported_Constants CTC Exported Constants
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* @{
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*/
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/** @defgroup CTC_AUTO_TRIM CTC Trim Mode Config
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* @{
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*/
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#define CTC_AUTO_TRIM_DISABLE 0x00000000U /*!< hardware automatically trim mode disable*/
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#define CTC_AUTO_TRIM_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
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/**
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* @}
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*/
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/** @defgroup CTC_Ref_Clock_Source CTC Input Reference Clock
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* @{
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*/
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#define CTC_REF_CLOCK_SOURCE_GPIO 0x00000000U /*!< GPIO is selected */
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#define CTC_REF_CLOCK_SOURCE_LSE CTC_CTL1_REFSEL_0 /*!< LSE is selected */
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#define CTC_REF_CLOCK_SOURCE_USBD_SOF CTC_CTL1_REFSEL_1 /*!< USBD_SOF is selected */
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/**
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* @}
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*/
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/** @defgroup CTC_Ref_Clock_Divider CTC Input Reference Clock divider
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* @{
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*/
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#define CTC_REF_CLOCK_DIV1 0x00000000U /*!< reference clock not divided */
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#define CTC_REF_CLOCK_DIV2 (CTC_CTL1_REFPSC_0) /*!< reference clock divided by 2 */
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#define CTC_REF_CLOCK_DIV4 (CTC_CTL1_REFPSC_1) /*!< reference clock divided by 4 */
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#define CTC_REF_CLOCK_DIV8 (CTC_CTL1_REFPSC_0 | CTC_CTL1_REFPSC_1) /*!< reference clock divided by 8 */
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#define CTC_REF_CLOCK_DIV16 (CTC_CTL1_REFPSC_2) /*!< reference clock divided by 16 */
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#define CTC_REF_CLOCK_DIV32 (CTC_CTL1_REFPSC_0 | CTC_CTL1_REFPSC_2) /*!< reference clock divided by 32 */
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#define CTC_REF_CLOCK_DIV64 (CTC_CTL1_REFPSC_1 | CTC_CTL1_REFPSC_2) /*!< reference clock divided by 64 */
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#define CTC_REF_CLOCK_DIV128 (CTC_CTL1_REFPSC_0 |CTC_CTL1_REFPSC_1 | CTC_CTL1_REFPSC_2) /*!< reference clock divided by 128 */
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/**
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* @}
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*/
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/** @defgroup CTC_Ref_Clock_Polarity CTC Reference Clock steady state
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* @{
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*/
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#define CTC_REF_CLOCK_POLARITY_RISING 0x00000000U /*!< reference clock source polarity is rising edge */
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#define CTC_REF_CLOCK_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference clock source polarity is falling edge */
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/**
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* @}
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*/
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/** @defgroup CTC_Counter_Direction CTC counter direction.
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* @{
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*/
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#define CTC_CNT_DIRECTION_UP 0x00000000U /*!< CTC trim count up */
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#define CTC_CNT_DIRECTION_DOWN CTC_SR_REFDIR /*!< CTC trim count down */
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/**
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* @}
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*/
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/** @defgroup CTC_interrupt_definitions CTC Interrupt Definitions
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* @{
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*/
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#define CTC_IT_CKOK ((uint32_t)CTC_CTL0_CKOKIE) /*!< clock trim OK interrupt */
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#define CTC_IT_CKWARN ((uint32_t)CTC_CTL0_CKWARNIE) /*!< clock trim warning interrupt */
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#define CTC_IT_ERR ((uint32_t)CTC_CTL0_ERRIE) /*!< error interrupt */
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#define CTC_IT_EREF ((uint32_t)CTC_CTL0_EREFIE) /*!< expect reference interrupt */
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/**
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* @}
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*/
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/** @defgroup UART_IT_CLEAR_Flags CTC Interruption Clear Flags
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* @{
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*/
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#define CTC_CLEAR_CKOK CTC_INTC_CKOKIC /*!< clock trim OK Clear Flag */
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#define CTC_CLEAR_CKWARN CTC_INTC_CKWARNIC /*!< clock trim warning Clear Flag */
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#define CTC_CLEAR_ERR CTC_INTC_ERRIC /*!< error Clear Flag */
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#define CTC_CLEAR_EREF CTC_INTC_EREFIC /*!< expect reference Clear Flag */
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/**
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* @}
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*/
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/** @defgroup CTC_flags_definition CTC flags definition
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* @{
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*/
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#define CTC_FLAG_TRIMERR CTC_SR_TRIMERR /*!< Trim Value Error flag */
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#define CTC_FLAG_REFMISS CTC_SR_REFMISS /*!< Synchronous Reference Pulse Signal Loss Flag */
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#define CTC_FLAG_CKERR CTC_SR_CKERR /*!< Clock Calibration Error Flag */
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#define CTC_FLAG_EREF CTC_SR_EREFIF /*!< Expect Reference Interrupt Flag */
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#define CTC_FLAG_ERR CTC_SR_ERRIF /*!< Error Interrupt Flag */
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#define CTC_FLAG_CKWARN CTC_SR_CKWARNIF /*!< Clock Trim Warning Flag */
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#define CTC_FLAG_CKOK CTC_SR_CKOKIF /*!< Clock Trim OK Flag */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup CTC_Exported_Macros CTC Exported Macros
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* @{
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*/
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/** @brief Enable CTC count.
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* @param __HANDLE__ specifies the CTC Handle.
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* @retval None
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*/
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#define __HAL_CTC_COUNT_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CTL0,CTC_CTL0_CNTEN))
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/** @brief Disable CTC count.
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* @param __HANDLE__ specifies the CTC Handle.
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* @retval None
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*/
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#define __HAL_CTC_COUNT_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CTL0,CTC_CTL0_CNTEN))
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/** @brief Read CTC counter capture value when reference sync pulse occurred.
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* @param __HANDLE__ specifies the CTC Handle.
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* @retval Capture value
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*/
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#define __HAL_CTC_GET_CAPVALUE(__HANDLE__) ((READ_BIT((__HANDLE__)->Instance->SR,CTC_SR_REFCAP))>>CTC_SR_REFCAP_Pos)
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/** @brief Read CTC trim counter direction when reference sync pulse occurred.
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* @param __HANDLE__ specifies the CTC Handle.
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* @retval The counter direction can be one of the following values:
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* @arg CTC_CNT_DIRECTION_UP
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* @arg CTC_CNT_DIRECTION_DOWN
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*/
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#define __HAL_CTC_GET_DIRECTION(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->SR,CTC_SR_REFDIR))
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/** @brief Enable CTC interrupt
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* @param __HANDLE__: CTC handle
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* @param __INTERRUPT__: specifies the CTC interrupt sources to be enabled.
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* This parameter can be any combination of the following values:
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* @arg CTC_IT_CKOK
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* @arg CTC_IT_CKWARN
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* @arg CTC_IT_ERR
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* @arg CTC_IT_EREF
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* @retval None
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*/
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#define __HAL_CTC_ENABLE_IT(__HANDLE__,__INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CTL0, (__INTERRUPT__)))
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/** @brief Disable CTC interrupt
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* @param __HANDLE__: CTC handle
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* @param __INTERRUPT__: specifies the CTC interrupt sources to be Disable.
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* This parameter can be any combination of the following values:
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* @arg CTC_IT_CKOK
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* @arg CTC_IT_CKWARN
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* @arg CTC_IT_ERR
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* @arg CTC_IT_EREF
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* @retval None
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*/
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#define __HAL_CTC_DISABLE_IT(__HANDLE__,__INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CTL0, (__INTERRUPT__)))
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/** @brief Check whether the specified CTC interrupt source is enabled or not.
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* @param __HANDLE__: CTC handle
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* @param __INTERRUPT__: specifies the CTC interrupt sources to be enabled.
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* This parameter can be any combination of the following values:
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* @arg CTC_IT_CKOK
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* @arg CTC_IT_CKWARN
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* @arg CTC_IT_ERR
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* @arg CTC_IT_EREF
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* @retval None
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*/
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#define __HAL_CTC_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CTL0 & (__INTERRUPT__)) \
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== (__INTERRUPT__)) ? SET : RESET)
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/** @brief Clear the CTC's interrupt flags
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* @param __HANDLE__: CTC handle
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* @param __FLAG__: CTC interrupt clear flag
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* This parameter can be any combination of the following values:
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* @arg CTC_CLEAR_CKOK
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* @arg CTC_CLEAR_CKWARN
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* @arg CTC_CLEAR_ERR
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* @arg CTC_CLEAR_EREF
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* @retval None
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*/
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#define __HAL_CTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->INTC, (__FLAG__)))
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/** @brief
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* @param __HANDLE__: CTC handle
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* @param __FLAG__: CTC interrupt clear flag
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* This parameter can be any combination of the following values:
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* @arg CTC_FLAG_TRIMERR
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* @arg CTC_FLAG_REFMISS
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* @arg CTC_FLAG_CKERR
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* @arg CTC_FLAG_EREF
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* @arg CTC_FLAG_ERR
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* @arg CTC_FLAG_CKWARN
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* @arg CTC_FLAG_CKOK
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* @retval None
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*/
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#define __HAL_CTC_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)))
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup CTC_Exported_Functions CTC Exported Functions
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* @{
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*/
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/** @addtogroup CTC_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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* @{
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*/
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/* Initialization/de-initialization functions ********************************/
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HAL_StatusTypeDef HAL_CTC_Init(CTC_HandleTypeDef *hctc);
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HAL_StatusTypeDef HAL_CTC_DeInit(CTC_HandleTypeDef *hctc);
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void HAL_CTC_MspInit(CTC_HandleTypeDef *hctc);
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void HAL_CTC_MspDeInit(CTC_HandleTypeDef *hctc);
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#if (USE_HAL_CTC_REGISTER_CALLBACKS == 1U)
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HAL_StatusTypeDef HAL_CTC_RegisterCallback(CTC_HandleTypeDef *hctc, HAL_CTC_CallbackIDTypeDef CallbackID, void (* pCallback)( CTC_HandleTypeDef * _hctc));
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HAL_StatusTypeDef HAL_CTC_UnRegisterCallback(CTC_HandleTypeDef *hctc, HAL_CTC_CallbackIDTypeDef CallbackID);
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void CTC_ResetCallback(CTC_HandleTypeDef *hctc);
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#endif /* USE_HAL_CTC_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/** @addtogroup CTC_Exported_Functions_Group2 Start and Stop operation functions
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* @brief CTC Start/Stop functions
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* @{
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*/
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HAL_StatusTypeDef HAL_CTC_Start(CTC_HandleTypeDef *hctc);
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HAL_StatusTypeDef HAL_CTC_Start_IT(CTC_HandleTypeDef *hctc);
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HAL_StatusTypeDef HAL_CTC_Stop(CTC_HandleTypeDef *hctc);
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HAL_StatusTypeDef HAL_CTC_Stop_IT(CTC_HandleTypeDef *hctc);
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HAL_StatusTypeDef HAL_CTC_Abort(CTC_HandleTypeDef *hctc);
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HAL_StatusTypeDef HAL_CTC_Abort_IT(CTC_HandleTypeDef *hctc);
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HAL_StatusTypeDef HAL_CTC_ConfigTrimValue(CTC_HandleTypeDef *hctc, uint8_t Trimvalue);
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uint32_t HAL_CTC_GetTrimValue(CTC_HandleTypeDef *hctc);
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void HAL_CTC_GenerateSynchronousPulses(CTC_HandleTypeDef *hctc);
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void HAL_CTC_IRQHandler(CTC_HandleTypeDef *hctc);
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void HAL_CTC_CKOKCallback(CTC_HandleTypeDef *hctc);
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void HAL_CTC_CKWARNCallback(CTC_HandleTypeDef *hctc);
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void HAL_CTC_ERRCallback(CTC_HandleTypeDef *hctc);
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void HAL_CTC_EREFCallback(CTC_HandleTypeDef *hctc);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup CTC_Private_Macros CTC Private Macros
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* @{
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*/
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#define IS_CTC_AUTO_TRIM(ALIGN) (((ALIGN) == CTC_AUTO_TRIM_DISABLE) || \
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((ALIGN) == CTC_AUTO_TRIM_ENABLE))
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#define IS_CTC_REF_CLOCK(ALIGN) (((ALIGN) == CTC_REF_CLOCK_SOURCE_GPIO) || \
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((ALIGN) == CTC_REF_CLOCK_SOURCE_LSE) || \
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((ALIGN) == CTC_REF_CLOCK_SOURCE_USBD_SOF))
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#define IS_CTC_REF_CLOCK_DIV(ALIGN) (((ALIGN) == CTC_REF_CLOCK_DIV1) || \
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((ALIGN) == CTC_REF_CLOCK_DIV2) || \
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((ALIGN) == CTC_REF_CLOCK_DIV4) || \
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((ALIGN) == CTC_REF_CLOCK_DIV8) || \
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((ALIGN) == CTC_REF_CLOCK_DIV16) || \
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((ALIGN) == CTC_REF_CLOCK_DIV32) || \
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((ALIGN) == CTC_REF_CLOCK_DIV64) || \
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((ALIGN) == CTC_REF_CLOCK_DIV128))
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#define IS_CTC_REF_CLOCK_POLARITY(ALIGN) (((ALIGN) == CTC_REF_CLOCK_POLARITY_RISING) || \
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((ALIGN) == CTC_REF_CLOCK_POLARITY_FALLING))
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#define IS_CTC_RELOAD_VALUE(VALUE) ((VALUE) <= 0xFFFF)
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#define IS_CTC_LIMIT_VALUE(VALUE) ((VALUE) <= 0xFF)
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#define IS_CTC_TRIMVALUE(VALUE) ((VALUE) <= 0x7F)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PY32F403_HAL_RCC_H */
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/************************ (C) COPYRIGHT Puya *****END OF FILE******************/
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