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659 lines
20 KiB
C
659 lines
20 KiB
C
/**
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******************************************************************************
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* @file py32f403_ll_ctc.h
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* @author MCU Application Team
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* @brief Header file of CTC LL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2023 Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by Puya under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __PY32F403_LL_CTC_H
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#define __PY32F403_LL_CTC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "py32f4xx.h"
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/** @addtogroup PY32F403_LL_Driver
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* @{
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*/
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#if defined (CTC)
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/** @defgroup CTC_LL CTC
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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#if defined(USE_FULL_LL_DRIVER)
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/** @defgroup CTC_LL_ES_INIT CTC Exported Init structure
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* @{
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*/
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/**
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* @brief CTC Init structures definition
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*/
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typedef struct
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{
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uint32_t AutoTrim; /*!< CTC Auto Trim Mode
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This parameter can be a value of @ref CTC_LL_EC_AUTO_TRIM */
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uint32_t LimitValue; /*!< Base time limit for clock calibration
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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uint32_t ReloadValue; /*!< CTC counter overload value
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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uint32_t RefCLKSource; /*!< CTC Input Reference Clock
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This parameter can be a value of @ref CTC_LL_EC_Ref_Clock_Source */
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uint32_t RefCLKDivider; /*!< The Reference Clock divider
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This parameter can be a value of @ref CTC_LL_EC_Ref_Clock_Divider */
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uint32_t RefCLKPolarity; /*!< The Reference Clock steady state
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This parameter can be a value of @ref CTC_LL_EC_Ref_Clock_Polarity */
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} LL_CTC_InitTypeDef;
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CTC_LL_Exported_Constants CTC Exported Constants
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* @{
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*/
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/** @defgroup CTC_LL_EC_AUTO_TRIM CTC Trim Mode Defines
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* @{
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*/
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#define LL_CTC_AUTO_TRIM_DISABLE 0x00000000U /*!< hardware automatically trim mode disable*/
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#define LL_CTC_AUTO_TRIM_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
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/**
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* @}
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*/
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/** @defgroup CTC_LL_EC_Ref_Clock_Source CTC Input Reference Clock
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* @{
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*/
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#define LL_CTC_REF_CLOCK_SOURCE_GPIO 0x00000000U /*!< GPIO is selected */
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#define LL_CTC_REF_CLOCK_SOURCE_LSE CTC_CTL1_REFSEL_0 /*!< LSE is selected */
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#define LL_CTC_REF_CLOCK_SOURCE_USBD_SOF CTC_CTL1_REFSEL_1 /*!< USBD_SOF is selected */
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/**
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* @}
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*/
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/** @defgroup CTC_LL_EC_Ref_Clock_Divider CTC Input Reference Clock divider
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* @{
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*/
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#define LL_CTC_REF_CLOCK_DIV1 0x00000000U /*!< reference clock not divided */
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#define LL_CTC_REF_CLOCK_DIV2 (CTC_CTL1_REFPSC_0) /*!< reference clock divided by 2 */
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#define LL_CTC_REF_CLOCK_DIV4 (CTC_CTL1_REFPSC_1) /*!< reference clock divided by 4 */
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#define LL_CTC_REF_CLOCK_DIV8 (CTC_CTL1_REFPSC_0 | CTC_CTL1_REFPSC_1) /*!< reference clock divided by 8 */
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#define LL_CTC_REF_CLOCK_DIV16 (CTC_CTL1_REFPSC_2) /*!< reference clock divided by 16 */
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#define LL_CTC_REF_CLOCK_DIV32 (CTC_CTL1_REFPSC_0 | CTC_CTL1_REFPSC_2) /*!< reference clock divided by 32 */
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#define LL_CTC_REF_CLOCK_DIV64 (CTC_CTL1_REFPSC_1 | CTC_CTL1_REFPSC_2) /*!< reference clock divided by 64 */
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#define LL_CTC_REF_CLOCK_DIV128 (CTC_CTL1_REFPSC_0 |CTC_CTL1_REFPSC_1 | CTC_CTL1_REFPSC_2) /*!< reference clock divided by 128 */
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/**
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* @}
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*/
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/** @defgroup CTC_LL_EC_Ref_Clock_Polarity CTC Reference Clock Polarity
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* @{
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*/
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#define LL_CTC_REF_CLOCK_POLARITY_RISING 0x00000000U /*!< reference clock source polarity is rising edge */
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#define LL_CTC_REF_CLOCK_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference clock source polarity is falling edge */
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/**
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* @}
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*/
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/** @defgroup CTC_LL_EC_Counter_Direction CTC counter direction
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* @{
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*/
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#define LL_CTC_CNT_DIRECTION_UP 0x00000000U /*!< CTC trim count up */
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#define LL_CTC_CNT_DIRECTION_DOWN CTC_SR_REFDIR /*!< CTC trim count down */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup CTC_LL_Exported_Functions CTC Exported Functions
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* @{
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*/
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/**
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* @brief Enable clock calibration completion interrupt.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_EnableIT_CKOK(CTC_TypeDef *CTCx)
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{
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SET_BIT(CTCx->CTL0, CTC_CTL0_CKOKIE);
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}
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/**
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* @brief Disable clock calibration completion interrupt.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_DisableIT_CKOK(CTC_TypeDef *CTCx)
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{
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CLEAR_BIT(CTCx->CTL0, CTC_CTL0_CKOKIE);
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}
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/**
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* @brief Check if clock calibration completion interrupt is enabled.
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* @param CTCx CTC Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CTC_IsEnabledIT_CKOK(CTC_TypeDef *CTCx)
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{
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return ((READ_BIT(CTCx->CTL0, CTC_CTL0_CKOKIE) == (CTC_CTL0_CKOKIE)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable clock calibration warning interrupt.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_EnableIT_CKWARN(CTC_TypeDef *CTCx)
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{
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SET_BIT(CTCx->CTL0, CTC_CTL0_CKWARNIE);
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}
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/**
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* @brief Disable clock calibration warning interrupt.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_DisableIT_CKWARN(CTC_TypeDef *CTCx)
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{
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CLEAR_BIT(CTCx->CTL0, CTC_CTL0_CKWARNIE);
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}
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/**
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* @brief Check if clock calibration warning interrupt is enabled.
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* @param CTCx CTC Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CTC_IsEnabledIT_CKWARN(CTC_TypeDef *CTCx)
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{
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return ((READ_BIT(CTCx->CTL0, CTC_CTL0_CKWARNIE) == (CTC_CTL0_CKWARNIE)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable error interrupt.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_EnableIT_ERR(CTC_TypeDef *CTCx)
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{
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SET_BIT(CTCx->CTL0, CTC_CTL0_ERRIE);
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}
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/**
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* @brief Disable error interrupt.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_DisableIT_ERR(CTC_TypeDef *CTCx)
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{
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CLEAR_BIT(CTCx->CTL0, CTC_CTL0_ERRIE);
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}
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/**
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* @brief Check if error interrupt is enabled.
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* @param CTCx CTC Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CTC_IsEnabledIT_ERR(CTC_TypeDef *CTCx)
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{
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return ((READ_BIT(CTCx->CTL0, CTC_CTL0_ERRIE) == (CTC_CTL0_ERRIE)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable expected reference signal interrupt.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_EnableIT_EREF(CTC_TypeDef *CTCx)
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{
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SET_BIT(CTCx->CTL0, CTC_CTL0_EREFIE);
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}
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/**
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* @brief Disable expected reference signal interrupt.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_DisableIT_EREF(CTC_TypeDef *CTCx)
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{
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CLEAR_BIT(CTCx->CTL0, CTC_CTL0_EREFIE);
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}
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/**
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* @brief Check if expected reference signal interrupt is enabled.
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* @param CTCx CTC Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CTC_IsEnabledIT_EREF(CTC_TypeDef *CTCx)
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{
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return ((READ_BIT(CTCx->CTL0, CTC_CTL0_EREFIE) == (CTC_CTL0_EREFIE)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable CTC counter.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_EnableCount(CTC_TypeDef *CTCx)
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{
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SET_BIT(CTCx->CTL0, CTC_CTL0_CNTEN);
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}
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/**
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* @brief Disable CTC counter.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_DisableCount(CTC_TypeDef *CTCx)
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{
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CLEAR_BIT(CTCx->CTL0, CTC_CTL0_CNTEN);
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}
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/**
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* @brief Check if CTC counter is enabled.
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* @param CTCx CTC Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CTC_IsEnabledCount(CTC_TypeDef *CTCx)
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{
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return ((READ_BIT(CTCx->CTL0, CTC_CTL0_CNTEN) == (CTC_CTL0_CNTEN)) ? 1UL : 0UL);
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}
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/**
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* @brief Set CTC hardware automatically trim mode.
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* @param CTCx CTC Instance
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* @param Mode This parameter can be one of the following values:
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* @arg @ref LL_CTC_AUTO_TRIM_DISABLE
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* @arg @ref LL_CTC_AUTO_TRIM_ENABLE
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_SetAutoTrimMode(CTC_TypeDef *CTCx, uint32_t Mode)
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{
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MODIFY_REG(CTCx->CTL0, CTC_CTL0_AUTOTRIM, Mode);
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}
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/**
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* @brief Get CTC hardware automatically trim mode.
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* @param CTCx CTC Instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_CTC_AUTO_TRIM_DISABLE
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* @arg @ref LL_CTC_AUTO_TRIM_ENABLE
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*/
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__STATIC_INLINE uint32_t LL_CTC_GetAutoTrimMode(CTC_TypeDef *CTCx)
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{
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return (uint32_t)(READ_BIT(CTCx->CTL0, CTC_CTL0_AUTOTRIM));
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}
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/**
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* @brief Software generates synchronous reference signal pulses.
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* @param CTCx CTC Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_GenerateSoftRefClk(CTC_TypeDef *CTCx)
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{
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SET_BIT(CTCx->CTL0, CTC_CTL0_SWREFPUL);
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}
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/**
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* @brief Set CTC trim value.
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* @param CTCx CTC Instance
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* @param Value This parameter must be a number between Min_Data = 0x0 and Max_Data = 0x7F
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_SetTrimValue(CTC_TypeDef *CTCx, uint32_t Value)
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{
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MODIFY_REG(CTCx->CTL0, CTC_CTL0_TRIMVALUE, (Value << CTC_CTL0_TRIMVALUE_Pos));
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}
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/**
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* @brief Get CTC trim value.
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* @param CTCx CTC Instance
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* @retval Returned value is a number between Min_Data = 0x0 and Max_Data = 0x7F
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*/
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__STATIC_INLINE uint32_t LL_CTC_GetTrimValue(CTC_TypeDef *CTCx)
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{
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return (uint32_t)(READ_BIT(CTCx->CTL0, CTC_CTL0_TRIMVALUE) >> CTC_CTL0_TRIMVALUE_Pos);
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}
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/**
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* @brief Set CTC counter reload value.
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* @param CTCx CTC Instance
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* @param Value This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_SetReloadValue(CTC_TypeDef *CTCx, uint32_t Value)
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{
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MODIFY_REG(CTCx->CTL1, CTC_CTL1_RLVALUE, (Value << CTC_CTL1_RLVALUE_Pos));
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}
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/**
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* @brief Get CTC counter reload value.
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* @param CTCx CTC Instance
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* @retval Returned value is a number between Min_Data = 0 and Max_Data = 0xFFFF
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*/
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__STATIC_INLINE uint32_t LL_CTC_GetReloadValue(CTC_TypeDef *CTCx)
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{
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return (uint32_t)(READ_BIT(CTCx->CTL1, CTC_CTL1_RLVALUE) >> CTC_CTL1_RLVALUE_Pos);
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}
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/**
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* @brief Set clock calibration time base limit.
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* @param CTCx CTC Instance
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* @param Value This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_SetClkCalLimit(CTC_TypeDef *CTCx, uint32_t Value)
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{
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MODIFY_REG(CTCx->CTL1, CTC_CTL1_CKLIM, (Value << CTC_CTL1_CKLIM_Pos));
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}
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/**
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* @brief Get clock calibration time base limit.
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* @param CTCx CTC Instance
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* @retval Returned value is a number between Min_Data = 0 and Max_Data = 0xFF
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*/
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__STATIC_INLINE uint32_t LL_CTC_GetClkCalLimit(CTC_TypeDef *CTCx)
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{
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return (uint32_t)(READ_BIT(CTCx->CTL1, CTC_CTL1_CKLIM) >> CTC_CTL1_CKLIM_Pos);
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}
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/**
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* @brief Set CTC Input Reference Clock divider.
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* @param CTCx CTC Instance
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* @param Divider This parameter can be one of the following values:
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* @arg @ref LL_CTC_REF_CLOCK_DIV1
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* @arg @ref LL_CTC_REF_CLOCK_DIV2
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* @arg @ref LL_CTC_REF_CLOCK_DIV4
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* @arg @ref LL_CTC_REF_CLOCK_DIV8
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* @arg @ref LL_CTC_REF_CLOCK_DIV16
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* @arg @ref LL_CTC_REF_CLOCK_DIV32
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* @arg @ref LL_CTC_REF_CLOCK_DIV64
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* @arg @ref LL_CTC_REF_CLOCK_DIV128
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_SetRefClkDiv(CTC_TypeDef *CTCx, uint32_t Divider)
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{
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MODIFY_REG(CTCx->CTL1, CTC_CTL1_REFPSC, Divider);
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}
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/**
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* @brief Get CTC Input Reference Clock divider.
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* @param CTCx CTC Instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_CTC_REF_CLOCK_DIV1
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* @arg @ref LL_CTC_REF_CLOCK_DIV2
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* @arg @ref LL_CTC_REF_CLOCK_DIV4
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* @arg @ref LL_CTC_REF_CLOCK_DIV8
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* @arg @ref LL_CTC_REF_CLOCK_DIV16
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* @arg @ref LL_CTC_REF_CLOCK_DIV32
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* @arg @ref LL_CTC_REF_CLOCK_DIV64
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* @arg @ref LL_CTC_REF_CLOCK_DIV128
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*/
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__STATIC_INLINE uint32_t LL_CTC_GetRefClkDiv(CTC_TypeDef *CTCx)
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{
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return (uint32_t)(READ_BIT(CTCx->CTL1, CTC_CTL1_REFPSC));
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}
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/**
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* @brief Set CTC input reference clock.
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* @param CTCx CTC Instance
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* @param Source This parameter can be one of the following values:
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* @arg @ref LL_CTC_REF_CLOCK_SOURCE_GPIO
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* @arg @ref LL_CTC_REF_CLOCK_SOURCE_LSE
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* @arg @ref LL_CTC_REF_CLOCK_SOURCE_USBD_SOF
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_SetRefClkSrc(CTC_TypeDef *CTCx, uint32_t Source)
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{
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MODIFY_REG(CTCx->CTL1, CTC_CTL1_REFSEL, Source);
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}
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/**
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* @brief Get CTC input reference clock.
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* @param CTCx CTC Instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_CTC_REF_CLOCK_SOURCE_GPIO
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* @arg @ref LL_CTC_REF_CLOCK_SOURCE_LSE
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* @arg @ref LL_CTC_REF_CLOCK_SOURCE_USBD_SOF
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*/
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__STATIC_INLINE uint32_t LL_CTC_GetRefClkSrc(CTC_TypeDef *CTCx)
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{
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return (uint32_t)(READ_BIT(CTCx->CTL1, CTC_CTL1_REFSEL));
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}
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/**
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* @brief Set CTC reference clock polarity.
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* @param CTCx CTC Instance
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* @param Polarity This parameter can be one of the following values:
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* @arg @ref LL_CTC_REF_CLOCK_POLARITY_RISING
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* @arg @ref LL_CTC_REF_CLOCK_POLARITY_FALLING
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* @retval None
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*/
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__STATIC_INLINE void LL_CTC_SetRefClkPol(CTC_TypeDef *CTCx, uint32_t Polarity)
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{
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MODIFY_REG(CTCx->CTL1, CTC_CTL1_REFPOL, Polarity);
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}
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/**
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* @brief Get CTC reference clock polarity.
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* @param CTCx CTC Instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_CTC_REF_CLOCK_POLARITY_RISING
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* @arg @ref LL_CTC_REF_CLOCK_POLARITY_FALLING
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*/
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__STATIC_INLINE uint32_t LL_CTC_GetRefClkPol(CTC_TypeDef *CTCx)
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|
{
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return (uint32_t)(READ_BIT(CTCx->CTL1, CTC_CTL1_REFPOL));
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}
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/**
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* @brief Check if clock calibration successful interrupt flag bit is set.
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* @param CTCx CTC Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CTC_IsActiveFlag_CKOK(CTC_TypeDef *CTCx)
|
|
{
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return ((READ_BIT(CTCx->SR, CTC_SR_CKOKIF) == (CTC_SR_CKOKIF)) ? 1UL : 0UL);
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}
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|
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/**
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|
* @brief Check if clock calibration warning interrupt flag bit is set.
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|
* @param CTCx CTC Instance
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* @retval State of bit (1 or 0).
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|
*/
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__STATIC_INLINE uint32_t LL_CTC_IsActiveFlag_CKWARN(CTC_TypeDef *CTCx)
|
|
{
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|
return ((READ_BIT(CTCx->SR, CTC_SR_CKWARNIF) == (CTC_SR_CKWARNIF)) ? 1UL : 0UL);
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}
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|
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|
/**
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|
* @brief Check if error interrupt flag bit is set.
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|
* @param CTCx CTC Instance
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|
* @retval State of bit (1 or 0).
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|
*/
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__STATIC_INLINE uint32_t LL_CTC_IsActiveFlag_ERR(CTC_TypeDef *CTCx)
|
|
{
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|
return ((READ_BIT(CTCx->SR, CTC_SR_ERRIF) == (CTC_SR_ERRIF)) ? 1UL : 0UL);
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}
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|
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|
/**
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|
* @brief Check if expected reference interrupt flag bit is set.
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|
* @param CTCx CTC Instance
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|
* @retval State of bit (1 or 0).
|
|
*/
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|
__STATIC_INLINE uint32_t LL_CTC_IsActiveFlag_EREF(CTC_TypeDef *CTCx)
|
|
{
|
|
return ((READ_BIT(CTCx->SR, CTC_SR_EREFIF) == (CTC_SR_EREFIF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if clock calibration error flag bit is set.
|
|
* @param CTCx CTC Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CTC_IsActiveFlag_CKERR(CTC_TypeDef *CTCx)
|
|
{
|
|
return ((READ_BIT(CTCx->SR, CTC_SR_CKERR) == (CTC_SR_CKERR)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Loss of synchronous reference pulse signal flag is set.
|
|
* @param CTCx CTC Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CTC_IsActiveFlag_REFMISS(CTC_TypeDef *CTCx)
|
|
{
|
|
return ((READ_BIT(CTCx->SR, CTC_SR_REFMISS) == (CTC_SR_REFMISS)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if calibration value error flag is set.
|
|
* @param CTCx CTC Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CTC_IsActiveFlag_TRIMERR(CTC_TypeDef *CTCx)
|
|
{
|
|
return ((READ_BIT(CTCx->SR, CTC_SR_TRIMERR) == (CTC_SR_TRIMERR)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get CTC calibration clock counting direction.
|
|
* @param CTCx CTC Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_CTC_CNT_DIRECTION_UP
|
|
* @arg @ref LL_CTC_CNT_DIRECTION_DOWN
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CTC_GetCounterDir(CTC_TypeDef *CTCx)
|
|
{
|
|
return (uint32_t)(READ_BIT(CTCx->SR, CTC_SR_REFDIR));
|
|
}
|
|
|
|
/**
|
|
* @brief Get CTC counter capture value.
|
|
* @param CTCx CTC Instance
|
|
* @retval Returned value is a number between Min_Data = 0 and Max_Data = 0xFFFF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CTC_GetCounterCapValue(CTC_TypeDef *CTCx)
|
|
{
|
|
return (uint32_t)(READ_BIT(CTCx->SR, CTC_SR_REFCAP) >> CTC_SR_REFCAP_Pos);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear clock calibration successful interrupt flag.
|
|
* @param CTCx CTC Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CTC_ClearFlag_CKOK(CTC_TypeDef *CTCx)
|
|
{
|
|
SET_BIT(CTCx->INTC, CTC_INTC_CKOKIC);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear clock calibration warning interrupt flag.
|
|
* @param CTCx CTC Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CTC_ClearFlag_CKWARN(CTC_TypeDef *CTCx)
|
|
{
|
|
SET_BIT(CTCx->INTC, CTC_INTC_CKWARNIC);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear error interrupt flag.
|
|
* @param CTCx CTC Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CTC_ClearFlag_ERR(CTC_TypeDef *CTCx)
|
|
{
|
|
SET_BIT(CTCx->INTC, CTC_INTC_ERRIC);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear expected reference interrupt flag.
|
|
* @param CTCx CTC Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CTC_ClearFlag_EREF(CTC_TypeDef *CTCx)
|
|
{
|
|
SET_BIT(CTCx->INTC, CTC_INTC_EREFIC);
|
|
}
|
|
|
|
#if defined(USE_FULL_LL_DRIVER)
|
|
/** @defgroup CTC_LL_EF_Init Initialization and de-initialization functions
|
|
* @{
|
|
*/
|
|
|
|
ErrorStatus LL_CTC_DeInit(CTC_TypeDef *CTCx);
|
|
ErrorStatus LL_CTC_Init(CTC_TypeDef *CTCx, LL_CTC_InitTypeDef *CTC_InitStruct);
|
|
void LL_CTC_StructInit(LL_CTC_InitTypeDef *CTC_InitStruct);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* defined (CTC)*/
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __PY32F403_LL_CTC_H */
|
|
|
|
/************************ (C) COPYRIGHT Puya *****END OF FILE****/
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