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627 lines
21 KiB
C
627 lines
21 KiB
C
/**
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******************************************************************************
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* @file py32f403_ll_utils.c
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* @author MCU Application Team
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* @brief UTILS LL module driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2023 Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by Puya under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "py32f403_ll_utils.h"
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#include "py32f403_ll_rcc.h"
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#include "py32f403_ll_system.h"
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#ifdef USE_FULL_ASSERT
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#include "py32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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/** @addtogroup PY32F403_LL_Driver
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* @{
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*/
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/** @addtogroup UTILS_LL
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @addtogroup UTILS_LL_Private_Constants
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* @{
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*/
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#if defined(RCC_PLL_SUPPORT)
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#define UTILS_PLL_OUTPUT_MIN 48000000U /*!< Frequency max for PLL output, in Hz */
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#define UTILS_PLL_OUTPUT_MAX 144000000U /*!< Frequency max for PLL output, in Hz */
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/* Defines used for HSE range */
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#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
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#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */
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/* Defines used for PLL input range */
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#define LL_RCC_PLLINPUT_FREQ_MIN 8000000U /*!< Frequency min for PLL input frequency, in Hz */
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#define LL_RCC_PLLINPUT_FREQ_MAX 25000000U /*!< Frequency max for PLL input frequency, in Hz */
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#endif
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/* Defines used for FLASH latency according to HCLK Frequency */
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#define UTILS_SCALE1_LATENCY1_FREQ 28000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
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#define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
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#define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
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#define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
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#define UTILS_SCALE1_LATENCY5_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup UTILS_LL_Private_Macros
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* @{
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*/
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#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
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#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
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|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
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|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
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|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
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|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
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#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
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|| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
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|| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
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|| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
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|| ((__VALUE__) == LL_RCC_APB2_DIV_16))
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#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
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|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
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#if defined(RCC_PLL_SUPPORT)
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#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
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#define IS_LL_UTILS_PLL_INPUT_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= LL_RCC_PLLINPUT_FREQ_MIN) && ((__FREQUENCY__) <= LL_RCC_PLLINPUT_FREQ_MAX))
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#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) (((__VALUE__) >= UTILS_PLL_OUTPUT_MIN) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX))
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#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) ((__VALUE__) <= LL_RCC_PLLMUL_21)
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#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
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#endif
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/**
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* @}
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*/
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#if defined(RCC_PLL_SUPPORT)
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
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* @{
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*/
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static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
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static ErrorStatus UTILS_PLL_IsBusy(void);
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/**
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* @}
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*/
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#endif
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup UTILS_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup UTILS_LL_EF_DELAY
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* @{
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*/
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/**
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* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
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* @note When a RTOS is used, it is recommended to avoid changing the Systick
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* configuration by calling this function, for a delay use rather osDelay RTOS service.
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* @param HCLKFrequency HCLK frequency in Hz
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* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
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* @retval None
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*/
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void LL_Init1msTick(uint32_t HCLKFrequency)
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{
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/* Use frequency provided in argument */
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LL_InitTick(HCLKFrequency, 1000U);
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}
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/**
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* @brief This function provides accurate delay (in milliseconds) based
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* on SysTick counter flag
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* @note When a RTOS is used, it is recommended to avoid using blocking delay
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* and use rather osDelay service.
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* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
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* will configure Systick to 1ms
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* @param Delay specifies the delay time length, in milliseconds.
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* @retval None
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*/
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void LL_mDelay(uint32_t Delay)
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{
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__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
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uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
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/* Add this code to indicate that local variable is not used */
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((void)tmp);
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tmpDelay = Delay;
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/* Add a period to guaranty minimum wait */
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if (tmpDelay < LL_MAX_DELAY)
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{
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tmpDelay ++;
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}
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while (tmpDelay != 0U)
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{
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if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
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{
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tmpDelay --;
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}
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}
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}
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/**
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* @}
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*/
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/** @addtogroup UTILS_EF_SYSTEM
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* @brief System Configuration functions
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*
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@verbatim
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===============================================================================
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##### System Configuration functions #####
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===============================================================================
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[..]
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System, AHB and APB1 buses clocks configuration
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@endverbatim
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@internal
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Depending on the device voltage range, the maximum frequency should be
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adapted accordingly:
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(++) Table 1. HCLK clock frequency.
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(++) +-----------------------------------------------+
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(++) | Latency | HCLK clock frequency (MHz) |
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(++) |---------------|-------------------------------|
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(++) |0WS(1CPU cycle)| HCLK <= 28 |
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(++) |---------------|-------------------------------|
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(++) |1WS(2CPU cycle)| 28 < HCLK <= 60 |
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(++) |---------------|-------------------------------|
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(++) |3WS(4CPU cycle)| 60 < HCLK <= 90 |
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(++) |---------------|-------------------------------|
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(++) |4WS(5CPU cycle)| 90 < HCLK <= 120 |
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(++) |---------------|-------------------------------|
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(++) |5WS(6CPU cycle)| 120 < HCLK <= 140 |
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(++) |---------------|-------------------------------|
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(++) |6WS(7CPU cycle)| 140 < HCLK |
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(++) +-----------------------------------------------+
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@endinternal
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* @{
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*/
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/**
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* @brief This function sets directly SystemCoreClock CMSIS variable.
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* @note Variable can be calculated also through SystemCoreClockUpdate function.
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* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
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* @retval None
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*/
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void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
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{
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/* HCLK clock frequency */
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SystemCoreClock = HCLKFrequency;
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}
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#if defined(RCC_PLL_SUPPORT)
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/**
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* @brief This function configures system clock with HSI as clock source of the PLL
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* @note The application need to ensure that PLL is disabled.
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* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
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* the configuration information for the PLL.
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* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
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* the configuration information for the BUS prescalers.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: frequency configuration done
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* - ERROR: frequency configuration not done
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*/
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ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
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{
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ErrorStatus status = SUCCESS;
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uint32_t pllfreq = 0U;
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uint32_t hpre = LL_RCC_SYSCLK_DIV_1;
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/* Check if one of the PLL is enabled */
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if (UTILS_PLL_IsBusy() == SUCCESS)
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{
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/* Check the parameters */
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assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
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pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(HSI_VALUE, UTILS_PLLInitStruct->PLLMul);
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assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
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/* Enable HSI if not enabled */
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if (LL_RCC_HSI_IsReady() != 1U)
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{
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() != 1U)
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{
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/* Wait for HSI ready */
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}
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}
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/* Configure PLL */
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LL_RCC_PLL_SetMainSource(LL_RCC_PLLSOURCE_HSI);
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/* Configure PLLMUL */
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LL_RCC_PLL_SetMulFactor(UTILS_PLLInitStruct->PLLMul);
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/* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
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if(pllfreq > 80000000U)
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{
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if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
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{
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UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
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hpre = LL_RCC_SYSCLK_DIV_2;
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}
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}
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/* Enable PLL and switch system clock to PLL */
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status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
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/* Apply definitive AHB prescaler value if necessary */
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if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
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{
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/* Set FLASH latency to highest latency */
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status = LL_SetFlashLatency(pllfreq);
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if (status == SUCCESS)
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{
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UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
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LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
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LL_SetSystemCoreClock(pllfreq);
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}
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}
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}
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else
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{
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/* Current PLL configuration cannot be modified */
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status = ERROR;
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}
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return status;
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}
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/**
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* @brief This function configures system clock with HSE as clock source of the PLL
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* @note The application need to ensure that PLL is disabled.
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* @param HSEFrequency HSE frequency
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* @param HSEBypass This parameter can be one of the following values:
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* @arg @ref LL_UTILS_HSEBYPASS_ON
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* @arg @ref LL_UTILS_HSEBYPASS_OFF
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* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
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* the configuration information for the PLL.
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* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
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* the configuration information for the BUS prescalers.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: frequency configuration done
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* - ERROR: frequency configuration not done
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*/
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ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
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LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
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{
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ErrorStatus status = SUCCESS;
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uint32_t pllfreq = 0U;
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uint32_t hpre = LL_RCC_SYSCLK_DIV_1;
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/* Check the parameters */
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assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
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assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
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/* Check if one of the PLL is enabled */
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if (UTILS_PLL_IsBusy() == SUCCESS)
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{
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assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
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assert_param(IS_LL_UTILS_PLL_INPUT_FREQUENCY(HSEFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U)));
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assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
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pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(HSEFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
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assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
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/* Enable HSE if not enabled */
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if (LL_RCC_HSE_IsReady() != 1U)
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{
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/* Check if need to enable HSE bypass feature or not */
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if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
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{
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LL_RCC_HSE_EnableBypass();
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}
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else
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{
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LL_RCC_HSE_DisableBypass();
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if(HSEFrequency < 16000000U)
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{
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/* Set frequency range of the HSE */
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LL_RCC_HSE_SetFreqRegion(LL_RCC_HSE_8_16MHz);
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}
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else
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{
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/* Set frequency range of the HSE */
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LL_RCC_HSE_SetFreqRegion(LL_RCC_HSE_16_32MHz);
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}
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}
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/* Enable HSE */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1U)
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{
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/* Wait for HSE ready */
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}
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}
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/* Configure PLL */
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MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLXTPRE, UTILS_PLLInitStruct->Prediv);
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LL_RCC_PLL_SetMainSource(LL_RCC_PLLSOURCE_HSE);
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/* Configure PLLMUL */
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LL_RCC_PLL_SetMulFactor(UTILS_PLLInitStruct->PLLMul);
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/* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
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if(pllfreq > 80000000U)
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{
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if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
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{
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UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
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hpre = LL_RCC_SYSCLK_DIV_2;
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}
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}
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/* Enable PLL and switch system clock to PLL */
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status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
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/* Apply definitive AHB prescaler value if necessary */
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if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
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{
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/* Set FLASH latency to highest latency */
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status = LL_SetFlashLatency(pllfreq);
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if (status == SUCCESS)
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{
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UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
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LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
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LL_SetSystemCoreClock(pllfreq);
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}
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}
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}
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else
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{
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/* Current PLL configuration cannot be modified */
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status = ERROR;
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}
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return status;
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}
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#endif
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/**
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* @brief Update number of Flash wait states in line with new frequency and current
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* voltage range.
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* @param HCLKFrequency HCLK frequency
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: Latency has been modified
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* - ERROR: Latency cannot be modified
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*/
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ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
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{
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uint32_t timeout;
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uint32_t getlatency;
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uint32_t latency;
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ErrorStatus status;
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/* Frequency cannot be equal to 0 or greater than max clock */
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if (HCLKFrequency == 0U)
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{
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status = ERROR;
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return status;
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}
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else
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{
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if (HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ)
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{
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/* 140 < HCLK => 6WS (7 CPU cycles) */
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latency = LL_FLASH_LATENCY_6;
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}
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else if (HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
|
|
{
|
|
/* 120 < HCLK <= 140 => 5WS (6 CPU cycles) */
|
|
latency = LL_FLASH_LATENCY_5;
|
|
}
|
|
else if (HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
|
|
{
|
|
/* 90 < HCLK <= 120 => 4WS (5 CPU cycles) */
|
|
latency = LL_FLASH_LATENCY_4;
|
|
}
|
|
else if (HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
|
|
{
|
|
/* 60 < HCLK <= 90 => 3WS (4 CPU cycles) */
|
|
latency = LL_FLASH_LATENCY_3;
|
|
}
|
|
else if (HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
|
|
{
|
|
/* 28 < HCLK <= 60 => 1WS (2 CPU cycles) */
|
|
latency = LL_FLASH_LATENCY_1;
|
|
}
|
|
else
|
|
{
|
|
/* HCLK <= 28 => 0WS (1 CPU cycles) */
|
|
latency = LL_FLASH_LATENCY_0;
|
|
}
|
|
}
|
|
|
|
LL_FLASH_SetLatency(latency);
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
timeout = 2u;
|
|
do
|
|
{
|
|
/* Wait for Flash latency to be updated */
|
|
getlatency = LL_FLASH_GetLatency();
|
|
timeout--;
|
|
}
|
|
while ((getlatency != latency) && (timeout > 0u));
|
|
|
|
if (getlatency != latency)
|
|
{
|
|
status = ERROR;
|
|
}
|
|
else
|
|
{
|
|
status = SUCCESS;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#if defined(RCC_PLL_SUPPORT)
|
|
/** @addtogroup UTILS_LL_Private_Functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Function to check that PLL can be modified
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: PLL modification can be done
|
|
* - ERROR: PLL is busy
|
|
*/
|
|
static ErrorStatus UTILS_PLL_IsBusy(void)
|
|
{
|
|
ErrorStatus status = SUCCESS;
|
|
|
|
/* Check if PLL is busy*/
|
|
if (LL_RCC_PLL_IsReady() != 0U)
|
|
{
|
|
/* PLL configuration cannot be modified */
|
|
status = ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Function to enable PLL and switch system clock to PLL
|
|
* @param SYSCLK_Frequency SYSCLK frequency
|
|
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
|
* the configuration information for the BUS prescalers.
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: No problem to switch system to PLL
|
|
* - ERROR: Problem to switch system to PLL
|
|
*/
|
|
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
|
{
|
|
ErrorStatus status = SUCCESS;
|
|
uint32_t hclk_frequency = 0U;
|
|
|
|
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
|
|
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
|
|
assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
|
|
|
|
/* Calculate HCLK frequency */
|
|
hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (SystemCoreClock < hclk_frequency)
|
|
{
|
|
/* Set FLASH latency to highest latency */
|
|
status = LL_SetFlashLatency(hclk_frequency);
|
|
}
|
|
|
|
/* Update system clock configuration */
|
|
if (status == SUCCESS)
|
|
{
|
|
/* Enable PLL */
|
|
LL_RCC_PLL_Enable();
|
|
while (LL_RCC_PLL_IsReady() != 1U)
|
|
{
|
|
/* Wait for PLL ready */
|
|
}
|
|
|
|
/* Sysclk activation on the main PLL */
|
|
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
|
{
|
|
/* Wait for system clock switch to PLL */
|
|
}
|
|
|
|
/* Set APB1 prescaler*/
|
|
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
|
|
|
|
/* Set APB2 prescaler*/
|
|
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (SystemCoreClock > hclk_frequency)
|
|
{
|
|
/* Set FLASH latency to lowest latency */
|
|
status = LL_SetFlashLatency(hclk_frequency);
|
|
}
|
|
|
|
/* Update SystemCoreClock variable */
|
|
if (status == SUCCESS)
|
|
{
|
|
LL_SetSystemCoreClock(hclk_frequency);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT Puya *****END OF FILE****/
|