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338 lines
11 KiB
C
338 lines
11 KiB
C
/**
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******************************************************************************
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* @file system_py32f403.c
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* @author MCU Application Team
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2023 Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by Puya under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup py32f403_system
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* @{
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*/
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/** @addtogroup py32f403_System_Private_Includes
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* @{
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*/
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#include "py32f4xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)24000000) /*!< Default value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/** @addtogroup PY32F403_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = HSI_VALUE;//HSI_VALUE;//((uint32_t)96000000);
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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/**
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* @}
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*/
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/** @addtogroup PY32F403_System_Private_Functions
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* @{
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*/
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void APP_ErrorProc(void)
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{
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HAL_NVIC_SystemReset();
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}
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/**
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* @brief Load trim.
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* @param None
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* @retval None
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*/
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void APP_LoadTrim(void)
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{
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uint32_t OPTAddr[]={0x1FFF5110,0x1FFF5114,0x1FFF5118,0x1FFF5148,0x1FFF514C,0x1FFF5600,0x1FFF5604,0x1FFF5200,0x1FFF5204,\
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0x1FFF5140,0x1FFF5144,0x1FFF5208,0x1FFF5120,0x1FFF5124,0x1FFF5128,0x1FFF512C,0x1FFF5130,0x1FFF5134};
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uint32_t OPTValue[18] = {0};
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uint32_t RegAddr[]={0x40022208,0x4002220C,0x40022220,0x40022228,0x40022224,0x4002221C,0x4002222C,0x40022210,0x40022214,0x40022218};
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uint32_t RegMask[]={0x0FFF0FFF,0x000000FF,0x001F000F,0x1FFF07FF,0x07FF07FF,0x003F003F,0x0000003F,0xFFFFFFFF,0xFFFFFFFF,0x0FFF0FFF};
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uint32_t RegValue[10] = {0};
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uint32_t i = 0;
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uint32_t j = 0;
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uint32_t temp = 0;
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/* Enable FLASH_KEYR */
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*((__IO uint32_t *)(0x40022008)) = 0x45670123;
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*((__IO uint32_t *)(0x40022008)) = 0xcdef89ab;
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/* Enable FLASH_OPTKEYR */
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*((__IO uint32_t *)(0x4002200c)) = 0x08192A3B;
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*((__IO uint32_t *)(0x4002200c)) = 0x4C5D6E7F;
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/* Enable FLASH_TESTKEYR */
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*((__IO uint32_t *)(0x4002228c)) = 0x5D7F4051;
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*((__IO uint32_t *)(0x4002228c)) = 0x46CE2763;
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/*********************************************/
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for (i=0; i < 18; i++)
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{
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j=3;
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do
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{
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temp = READ_REG(*((__IO uint32_t *)(OPTAddr[i])));
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if ((temp >> 16U) == ((~temp) & 0xFFFFU))
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{
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OPTValue[i] = temp;
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break;
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}
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}while(--j);
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if(j == 0)
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{
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APP_ErrorProc();
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}
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}
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/*(1) 0x40022208*/
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RegValue[0] = (OPTValue[0] & 0x0FFF) | ((OPTValue[1] & 0x0FFF) << 16);
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/*(2) 0x4002220C*/
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RegValue[1] = (OPTValue[2] & 0x00FF);
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/*(3) 0x40022220*/
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RegValue[2] = (OPTValue[3] & 0x000F) | ((OPTValue[4] & 0x001F) << 16);
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/*(4) 0x40022228*/
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RegValue[3] = (OPTValue[5] & 0x07FF) | ((OPTValue[6] & 0x1FFF) << 16);
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/*(5) 0x40022224*/
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RegValue[4] = (OPTValue[7] & 0x07FF) | ((OPTValue[8] & 0x07FF) << 16);
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/*(6) 0x4002221C*/
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RegValue[5] = (OPTValue[9] & 0x003F) | ((OPTValue[10] & 0x003F) << 16);
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/*(7) 0x4002222C*/
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RegValue[6] = (OPTValue[11] & 0x003F);
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/*(8) 0x40022210*/
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RegValue[7] = (OPTValue[12] & 0xFFFF) | ((OPTValue[13] & 0xFFFF) << 16);
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/*(9) 0x40022214*/
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RegValue[8] = (OPTValue[14] & 0xFFFF) | ((OPTValue[15] & 0xFFFF) << 16);
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/*(10) 0x40022218*/
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RegValue[9] = (OPTValue[16] & 0x0FFF) | ((OPTValue[17] & 0x0FFF) << 16);
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for(i=0; i < 10;i++)
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{
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temp = READ_REG(*((__IO uint32_t *)(RegAddr[i])));
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if (RegValue[i] != (temp & RegMask[i]))
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{
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MODIFY_REG(*((__IO uint32_t *)(RegAddr[i])), RegMask[i], RegValue[i]);
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}
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}
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/*********************************************/
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/* Enable TRIM update */
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*((__IO uint32_t *)(0x40022200)) |= 0x01;
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/* Wait ten nop delays */
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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/* Disable TRIM update */
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*((__IO uint32_t *)(0x40022200)) &= (~0x01);
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for(i=0; i < 10;i++)
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{
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temp = READ_REG(*((__IO uint32_t *)(RegAddr[i])));
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if (RegValue[i] != (temp & RegMask[i]))
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{
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APP_ErrorProc();
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}
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}
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/* Disable FLASH_OPTKEYR、FLASH_TESTKEYR */
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*((__IO uint32_t *)(0x40022014)) |= 0x40000000;
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/* Disable FLASH_KEYR、FLASH_TESTKEYR */
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*((__IO uint32_t *)(0x40022014)) |= 0x80000000;
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}
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/**
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* @brief Setup the microcontroller system
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* Initialize the FPU setting, vector table location and External memory
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* configuration.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Load trim */
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APP_LoadTrim();
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in py32f403_hal_conf.h file (default value
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* 8 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in py32f403_hal_conf.h file (its value
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* depends on the application requirements), user has to ensure that HSE_VALUE
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* is same as the real frequency of the crystal used. Otherwise, this function
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* may have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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const uint8_t aPLLMULFactorTable[64] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, \
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18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, \
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34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
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50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 63, 63};
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const uint8_t aPredivFactorTable[2] = {1, 2};
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uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
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uint32_t tmp = 0;
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tmpreg = RCC->CFGR;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (tmpreg & RCC_CFGR_SWS)
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{
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case 0x00: /* HSI used as system clock source */
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{
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SystemCoreClock = HSI_VALUE;
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break;
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}
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case 0x04: /* HSE used as system clock */
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{
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SystemCoreClock = HSE_VALUE;
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break;
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}
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case 0x08: /* PLL used as system clock */
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{
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pllmul = aPLLMULFactorTable[(((tmpreg&(RCC_CFGR_PLLMULL_4|RCC_CFGR_PLLMULL_5))>>7) | (tmpreg&(RCC_CFGR_PLLMULL_0| \
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RCC_CFGR_PLLMULL_1|RCC_CFGR_PLLMULL_2|RCC_CFGR_PLLMULL_3)))>>RCC_CFGR_PLLMULL_Pos];
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if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC)
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{
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prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
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/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
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pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
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}
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else
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{
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/* HSI used as PLL clock source : PLLCLK = HSI * PLLMUL */
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pllclk = (uint32_t)(HSI_VALUE * pllmul);
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}
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SystemCoreClock = pllclk;
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break;
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}
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default:
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{
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break;
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}
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}
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
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SystemCoreClock >>= tmp;
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}
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT Puya *****END OF FILE******************/
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