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CMSIS-DSP: Corrected some headers to use right date and versions.

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Added a new option to test framework.
pull/19/head
Christophe Favergeon 5 years ago
parent 9133c874e0
commit 0a5a96d904
18 changed files with 70 additions and 56 deletions
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7
Include/arm_common_tables.h
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@ -3,13 +3,12 @@
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
* @version V1.9.0
* @date 17. March 2021
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

7
Include/arm_common_tables_f16.h
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@ -3,13 +3,12 @@
* Title: arm_common_tables_f16.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
* @version V1.9.0
* @date 17. March 2021
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

7
Include/arm_const_structs.h
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@ -4,13 +4,12 @@
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
* @version V1.9.0
* @date 17. March 2021
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

7
Include/arm_const_structs_f16.h
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@ -4,13 +4,12 @@
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f16() function.
*
* $Date: 20. April 2020
* $Revision: V.1.5.1
* @version V1.9.0
* @date 17. March 2021
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

6
Include/arm_helium_utils.h
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@ -3,13 +3,13 @@
* Title: arm_helium_utils.h
* Description: Utility functions for Helium development
*
* $Date: 09. September 2019
* $Revision: V.1.5.1
* @version V1.9.0
* @date 17. March 2021
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

6
Include/arm_math.h
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@ -1,11 +1,11 @@
/******************************************************************************
* @file arm_math.h
* @brief Public header file for CMSIS DSP Library
* @version V1.7.0
* @date 18. March 2019
* @version V1.9.0
* @date 17. March 2021
******************************************************************************/
/*
* Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

6
Include/arm_math_f16.h
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@ -1,11 +1,11 @@
/******************************************************************************
* @file arm_math_f16.h
* @brief Public header file for f16 function of the CMSIS DSP Library
* @version V1.8.1
* @date 20. April 2020
* @version V1.9.0
* @date 17. March 2021
******************************************************************************/
/*
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

4
Include/arm_math_memory.h
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@ -2,10 +2,10 @@
* @file arm_math_memory.h
* @brief Public header file for CMSIS DSP Library
* @version V1.9.0
* @date 20. July 2020
* @date 17. March 2021
******************************************************************************/
/*
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

4
Include/arm_math_types.h
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@ -2,10 +2,10 @@
* @file arm_math_types.h
* @brief Public header file for CMSIS DSP Library
* @version V1.9.0
* @date 20. July 2020
* @date 17. March 2021
******************************************************************************/
/*
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

4
Include/arm_math_types_f16.h
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@ -2,10 +2,10 @@
* @file arm_math_types_f16.h
* @brief Public header file for f16 function of the CMSIS DSP Library
* @version V1.9.0
* @date 20. July 2020
* @date 17. March 2021
******************************************************************************/
/*
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

5
Include/arm_mve_tables.h
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@ -4,12 +4,13 @@
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
* used for MVE implementation only
*
* $Date: 14. April 2020
* @version V1.9.0
* @date 17. March 2021
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

5
Include/arm_mve_tables_f16.h
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@ -4,12 +4,13 @@
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
* used for MVE implementation only
*
* $Date: 14. April 2020
* @version V1.9.0
* @date 17. March 2021
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

6
Include/arm_vec_math.h
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@ -1,11 +1,11 @@
/******************************************************************************
* @file arm_vec_math.h
* @brief Public header file for CMSIS DSP Library
* @version V1.7.0
* @date 15. October 2019
* @version V1.9.0
* @date 17. March 2021
******************************************************************************/
/*
* Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

4
Include/arm_vec_math_f16.h
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@ -1,9 +1,11 @@
/******************************************************************************
* @file arm_vec_math_f16.h
* @brief Public header file for CMSIS DSP Library
* @version V1.9.0
* @date 17. March 2021
******************************************************************************/
/*
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*

5
Testing/CMakeLists.txt
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@ -84,6 +84,7 @@ option(EMBEDDED "Embedded Mode" ON)
option(FLOAT16TESTS "Float16 tests" OFF)
option(MICROBENCH "Micro benchmarks" OFF)
option(EXTERNAL "External benchmarks or tests" OFF)
option(CACHEANALYSIS "Build with cache analysis mode enabled" OFF)
option(DISTINCT "Different generated folder for benchmarking and tests" OFF)
@ -121,6 +122,10 @@ if (AUTOVECTORIZE)
target_compile_definitions(TestingLib PRIVATE ARM_MATH_AUTOVECTORIZE)
endif()
if (CACHEANALYSIS)
target_compile_definitions(FrameworkLib PRIVATE CACHEANALYSIS)
endif()
if (BENCHMARK)

2
Testing/FrameworkInclude/Timing.h
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@ -11,7 +11,7 @@ void cycleMeasurementStop();
Testing::cycles_t getCycles();
#ifdef EXTBENCH
#if defined(EXTBENCH) || defined(CACHEANALYSIS)
extern unsigned long sectionCounter;
#if defined ( __CC_ARM )

39
Testing/FrameworkSource/IORunner.cpp
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@ -82,18 +82,7 @@ a C++ function pointer from the cycle measurements.
Client::test t = (Client::test)&Calibrate::empty;
calibration = 0;
/*
EXTBENCH is set when benchmarking is done through external traces
instead of using internal counters.
Currently the post-processing scripts are only supporting traces generated from
fast models.
*/
#ifdef EXTBENCH
startSection();
#endif
/*
@ -152,6 +141,20 @@ the code not in cache.
While for the code itself we have the value for the code in cache.
*/
/*
EXTBENCH is set when benchmarking is done through external traces
instead of using internal counters.
Currently the post-processing scripts are only supporting traces generated from
fast models.
*/
#if defined(EXTBENCH) || defined(CACHEANALYSIS)
startSection();
#endif
for(int i=0;i < CALIBNB;i++)
{
cycleMeasurementStart();
@ -165,7 +168,7 @@ While for the code itself we have the value for the code in cache.
calibration += current;
cycleMeasurementStop();
}
#ifdef EXTBENCH
#if defined(EXTBENCH) || defined(CACHEANALYSIS)
stopSection();
#endif
@ -275,6 +278,9 @@ While for the code itself we have the value for the code in cache.
__DSB();
__ISB();
#endif
/* If cache analysis mode, we don't force the code to be in cache. */
#if !defined(CACHEANALYSIS)
if (s->isForcedInCache())
{
if (!m_mgr->HasMemError())
@ -282,19 +288,22 @@ While for the code itself we have the value for the code in cache.
(s->*t)();
}
}
#endif
// Run the test
cycleMeasurementStart();
#ifdef EXTBENCH
#if defined(EXTBENCH) || defined(CACHEANALYSIS)
startSection();
#endif
if (!m_mgr->HasMemError())
{
(s->*t)();
}
#ifdef EXTBENCH
#if defined(EXTBENCH) || defined(CACHEANALYSIS)
stopSection();
#endif
#ifndef EXTBENCH
cycles=getCycles();
cycles=cycles-calibration;

2
Testing/FrameworkSource/Timing.cpp
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@ -62,7 +62,7 @@ unsigned int startCycles;
#define ENABLE_DIVIDER 0
#endif
#ifdef EXTBENCH
#if defined(EXTBENCH) || defined(CACHEANALYSIS)
unsigned long sectionCounter=0;
#endif

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