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Updated CMSIS DSP because of wrong macro ARM_MATH_CM0_FAMILY_FAMILY.

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pull/19/head
Martin Günther 9 years ago
parent 65a0fde9d4
commit 147cb4e37a
2 changed files with 116 additions and 116 deletions
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102
Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
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@ -1,25 +1,25 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
* *
* $Date: 19. March 2015 * $Date: 19. March 2015
* $Revision: V.1.4.5 * $Revision: V.1.4.5 a
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_q31.c * Title: arm_biquad_cascade_df1_q31.c
* *
* Description: Processing function for the * Description: Processing function for the
* Q31 Biquad cascade filter * Q31 Biquad cascade filter
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* - Redistributions of source code must retain the above copyright * - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright * - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in * notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the * the documentation and/or other materials provided with the
* distribution. * distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors * - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this * may be used to endorse or promote products derived from this
@ -28,7 +28,7 @@
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
@ -36,39 +36,39 @@
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
/** /**
* @ingroup groupFilters * @ingroup groupFilters
*/ */
/** /**
* @addtogroup BiquadCascadeDF1 * @addtogroup BiquadCascadeDF1
* @{ * @{
*/ */
/** /**
* @brief Processing function for the Q31 Biquad cascade filter. * @brief Processing function for the Q31 Biquad cascade filter.
* @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
* @param[in] *pSrc points to the block of input data. * @param[in] *pSrc points to the block of input data.
* @param[out] *pDst points to the block of output data. * @param[out] *pDst points to the block of output data.
* @param[in] blockSize number of samples to process per call. * @param[in] blockSize number of samples to process per call.
* @return none. * @return none.
* *
* <b>Scaling and Overflow Behavior:</b> * <b>Scaling and Overflow Behavior:</b>
* \par * \par
* The function is implemented using an internal 64-bit accumulator. * The function is implemented using an internal 64-bit accumulator.
* The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
* Thus, if the accumulator result overflows it wraps around rather than clip. * Thus, if the accumulator result overflows it wraps around rather than clip.
* In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
* After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to
* 1.31 format by discarding the low 32 bits. * 1.31 format by discarding the low 32 bits.
* *
* \par * \par
* Refer to the function <code>arm_biquad_cascade_df1_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. * Refer to the function <code>arm_biquad_cascade_df1_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
*/ */
void arm_biquad_cascade_df1_q31( void arm_biquad_cascade_df1_q31(
@ -90,7 +90,7 @@ void arm_biquad_cascade_df1_q31(
uint32_t sample, stage = S->numStages; /* loop counters */ uint32_t sample, stage = S->numStages; /* loop counters */
#ifndef ARM_MATH_CM0_FAMILY_FAMILY #ifndef ARM_MATH_CM0_FAMILY
q31_t acc_l, acc_h; /* temporary output variables */ q31_t acc_l, acc_h; /* temporary output variables */
@ -112,14 +112,14 @@ void arm_biquad_cascade_df1_q31(
Yn2 = pState[3]; Yn2 = pState[3];
/* Apply loop unrolling and compute 4 output values simultaneously. */ /* Apply loop unrolling and compute 4 output values simultaneously. */
/* The variable acc hold output values that are being computed: /* The variable acc hold output values that are being computed:
* *
* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
*/ */
sample = blockSize >> 2u; sample = blockSize >> 2u;
/* First part of the processing with loop unrolling. Compute 4 outputs at a time. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
** a second loop below computes the remaining 1 to 3 samples. */ ** a second loop below computes the remaining 1 to 3 samples. */
while(sample > 0u) while(sample > 0u)
{ {
@ -257,7 +257,7 @@ void arm_biquad_cascade_df1_q31(
sample--; sample--;
} }
/* If the blockSize is not a multiple of 4, compute any remaining output samples here. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
** No loop unrolling is used. */ ** No loop unrolling is used. */
sample = (blockSize & 0x3u); sample = (blockSize & 0x3u);
@ -334,8 +334,8 @@ void arm_biquad_cascade_df1_q31(
Yn1 = pState[2]; Yn1 = pState[2];
Yn2 = pState[3]; Yn2 = pState[3];
/* The variables acc holds the output value that is computed: /* The variables acc holds the output value that is computed:
* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
*/ */
sample = blockSize; sample = blockSize;
@ -394,12 +394,12 @@ void arm_biquad_cascade_df1_q31(
} while(--stage); } while(--stage);
#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }
/** /**
* @} end of BiquadCascadeDF1 group * @} end of BiquadCascadeDF1 group
*/ */

130
Source/TransformFunctions/arm_cfft_radix4_f32.c
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@ -1,25 +1,25 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
* *
* $Date: 19. March 2015 * $Date: 19. March 2015
* $Revision: V.1.4.5 * $Revision: V.1.4.5 a
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cfft_radix4_f32.c * Title: arm_cfft_radix4_f32.c
* *
* Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function
* *
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* - Redistributions of source code must retain the above copyright * - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright * - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in * notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the * the documentation and/or other materials provided with the
* distribution. * distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors * - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this * may be used to endorse or promote products derived from this
@ -28,7 +28,7 @@
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
@ -36,7 +36,7 @@
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -47,21 +47,21 @@ uint16_t fftSize,
uint16_t bitRevFactor, uint16_t bitRevFactor,
uint16_t * pBitRevTab); uint16_t * pBitRevTab);
/** /**
* @ingroup groupTransforms * @ingroup groupTransforms
*/ */
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
** Internal helper function used by the FFTs ** Internal helper function used by the FFTs
** ------------------------------------------------------------------- */ ** ------------------------------------------------------------------- */
/* /*
* @brief Core function for the floating-point CFFT butterfly process. * @brief Core function for the floating-point CFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
* @param[in] fftLen length of the FFT. * @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to the twiddle coefficient buffer. * @param[in] *pCoef points to the twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none. * @return none.
*/ */
void arm_radix4_butterfly_f32( void arm_radix4_butterfly_f32(
@ -76,7 +76,7 @@ uint16_t twidCoefModifier)
uint32_t i0, i1, i2, i3; uint32_t i0, i1, i2, i3;
uint32_t n1, n2, j, k; uint32_t n1, n2, j, k;
#ifndef ARM_MATH_CM0_FAMILY_FAMILY #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -176,7 +176,7 @@ uint16_t twidCoefModifier)
Yc12_out = Yc12C_out * co2; Yc12_out = Yc12C_out * co2;
Xd12_out = Xd12C_out * co3; Xd12_out = Xd12C_out * co3;
Yd12_out = Yd12C_out * co3; Yd12_out = Yd12C_out * co3;
/* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
//Xb12_out -= Yb12C_out * si1; //Xb12_out -= Yb12C_out * si1;
p0 = Yb12C_out * si1; p0 = Yb12C_out * si1;
@ -195,7 +195,7 @@ uint16_t twidCoefModifier)
/* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
//Yd12_out += Xd12C_out * si3; //Yd12_out += Xd12C_out * si3;
p5 = Xd12C_out * si3; p5 = Xd12C_out * si3;
Xb12_out += p0; Xb12_out += p0;
Yb12_out -= p1; Yb12_out -= p1;
Xc12_out += p2; Xc12_out += p2;
@ -256,7 +256,7 @@ uint16_t twidCoefModifier)
/* Twiddle coefficients index modifier */ /* Twiddle coefficients index modifier */
ia1 += twidCoefModifier; ia1 += twidCoefModifier;
i0 = j; i0 = j;
do do
{ {
@ -318,7 +318,7 @@ uint16_t twidCoefModifier)
Yc12_out = Yc12C_out * co2; Yc12_out = Yc12C_out * co2;
Xd12_out = Xd12C_out * co3; Xd12_out = Xd12C_out * co3;
Yd12_out = Yd12C_out * co3; Yd12_out = Yd12C_out * co3;
/* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
//Xb12_out -= Yb12C_out * si1; //Xb12_out -= Yb12C_out * si1;
p0 = Yb12C_out * si1; p0 = Yb12C_out * si1;
@ -337,7 +337,7 @@ uint16_t twidCoefModifier)
/* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
//Yd12_out += Xd12C_out * si3; //Yd12_out += Xd12C_out * si3;
p5 = Xd12C_out * si3; p5 = Xd12C_out * si3;
Xb12_out += p0; Xb12_out += p0;
Yb12_out -= p1; Yb12_out -= p1;
Xc12_out += p2; Xc12_out += p2;
@ -425,7 +425,7 @@ uint16_t twidCoefModifier)
a6 = (Xaminusc - Ybminusd); a6 = (Xaminusc - Ybminusd);
/* yd' = (ya+xb-yc-xd) */ /* yd' = (ya+xb-yc-xd) */
a7 = (Xbminusd + Yaminusc); a7 = (Xbminusd + Yaminusc);
ptr1[0] = a0; ptr1[0] = a0;
ptr1[1] = a1; ptr1[1] = a1;
ptr1[2] = a2; ptr1[2] = a2;
@ -546,7 +546,7 @@ uint16_t twidCoefModifier)
/* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3); pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
i0 += n1; i0 += n1;
} while( i0 < fftLen); } while( i0 < fftLen);
j++; j++;
@ -554,18 +554,18 @@ uint16_t twidCoefModifier)
twidCoefModifier <<= 2u; twidCoefModifier <<= 2u;
} }
#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }
/* /*
* @brief Core function for the floating-point CIFFT butterfly process. * @brief Core function for the floating-point CIFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
* @param[in] fftLen length of the FFT. * @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to twiddle coefficient buffer. * @param[in] *pCoef points to twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @param[in] onebyfftLen value of 1/fftLen. * @param[in] onebyfftLen value of 1/fftLen.
* @return none. * @return none.
*/ */
void arm_radix4_butterfly_inverse_f32( void arm_radix4_butterfly_inverse_f32(
@ -580,7 +580,7 @@ float32_t onebyfftLen)
uint32_t i0, i1, i2, i3; uint32_t i0, i1, i2, i3;
uint32_t n1, n2, j, k; uint32_t n1, n2, j, k;
#ifndef ARM_MATH_CM0_FAMILY_FAMILY #ifndef ARM_MATH_CM0_FAMILY
float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
@ -681,7 +681,7 @@ float32_t onebyfftLen)
Yc12_out = Yc12C_out * co2; Yc12_out = Yc12C_out * co2;
Xd12_out = Xd12C_out * co3; Xd12_out = Xd12C_out * co3;
Yd12_out = Yd12C_out * co3; Yd12_out = Yd12C_out * co3;
/* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
//Xb12_out -= Yb12C_out * si1; //Xb12_out -= Yb12C_out * si1;
p0 = Yb12C_out * si1; p0 = Yb12C_out * si1;
@ -700,7 +700,7 @@ float32_t onebyfftLen)
/* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
//Yd12_out += Xd12C_out * si3; //Yd12_out += Xd12C_out * si3;
p5 = Xd12C_out * si3; p5 = Xd12C_out * si3;
Xb12_out -= p0; Xb12_out -= p0;
Yb12_out += p1; Yb12_out += p1;
Xc12_out -= p2; Xc12_out -= p2;
@ -841,7 +841,7 @@ float32_t onebyfftLen)
/* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
//Yd12_out += Xd12C_out * si3; //Yd12_out += Xd12C_out * si3;
p5 = Xd12C_out * si3; p5 = Xd12C_out * si3;
Xb12_out -= p0; Xb12_out -= p0;
Yb12_out += p1; Yb12_out += p1;
Xc12_out -= p2; Xc12_out -= p2;
@ -914,7 +914,7 @@ float32_t onebyfftLen)
/* (yb-yd) */ /* (yb-yd) */
Ybminusd = ybIn - ydIn; Ybminusd = ybIn - ydIn;
/* xa' = (xa+xb+xc+xd) * onebyfftLen */ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
a0 = (Xaplusc + Xbplusd); a0 = (Xaplusc + Xbplusd);
/* ya' = (ya+yb+yc+yd) * onebyfftLen */ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
@ -931,7 +931,7 @@ float32_t onebyfftLen)
a6 = (Xaminusc + Ybminusd); a6 = (Xaminusc + Ybminusd);
/* yd' = (ya-xb-yc+xd) * onebyfftLen */ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
a7 = (Yaminusc - Xbminusd); a7 = (Yaminusc - Xbminusd);
p0 = a0 * onebyfftLen; p0 = a0 * onebyfftLen;
p1 = a1 * onebyfftLen; p1 = a1 * onebyfftLen;
p2 = a2 * onebyfftLen; p2 = a2 * onebyfftLen;
@ -940,7 +940,7 @@ float32_t onebyfftLen)
p5 = a5 * onebyfftLen; p5 = a5 * onebyfftLen;
p6 = a6 * onebyfftLen; p6 = a6 * onebyfftLen;
p7 = a7 * onebyfftLen; p7 = a7 * onebyfftLen;
/* xa' = (xa+xb+xc+xd) * onebyfftLen */ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
ptr1[0] = p0; ptr1[0] = p0;
/* ya' = (ya+yb+yc+yd) * onebyfftLen */ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
@ -1072,7 +1072,7 @@ float32_t onebyfftLen)
/* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3); pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
i0 += n1; i0 += n1;
} while( i0 < fftLen); } while( i0 < fftLen);
j++; j++;
@ -1160,22 +1160,22 @@ float32_t onebyfftLen)
pSrc[(2u * i3) + 1u] = s2 * onebyfftLen; pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
} }
#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }
/** /**
* @addtogroup ComplexFFT * @addtogroup ComplexFFT
* @{ * @{
*/ */
/** /**
* @details * @details
* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. * @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.
* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed * @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed
* in the future. * in the future.
* @param[in] *S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure. * @param[in] *S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.
* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place. * @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
* @return none. * @return none.
*/ */
void arm_cfft_radix4_f32( void arm_cfft_radix4_f32(
@ -1204,7 +1204,7 @@ float32_t * pSrc)
} }
/** /**
* @} end of ComplexFFT group * @} end of ComplexFFT group
*/ */

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