CMSIS-DSP: Corrected compilation warnings
More compilation tests done with AC5pull/19/head
Christophe Favergeon
7 years ago
parent
dc0be10d4e
commit
2e12da1043
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc
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;**************************************************
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; Copyright (c) 2017 ARM Ltd. All rights reserved.
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;**************************************************
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; Scatter-file for RTX Example on Versatile Express
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; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
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; This platform has 2GB SDRAM starting at 0x80000000.
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#include "mem_ARMCA5.h"
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SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
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{
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VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
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{
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* (RESET, +FIRST) ; Vector table and other startup code
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* (InRoot$$Sections) ; All (library) code that must be in a root region
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* (+RO-CODE) ; Application RO code (.text)
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* (+RO-DATA) ; Application RO data (.constdata)
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}
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RW_DATA __RAM_BASE __RW_DATA_SIZE
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{ * (+RW) } ; Application RW data (.data)
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ZI_DATA (__RAM_BASE+
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__RW_DATA_SIZE) __ZI_DATA_SIZE
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{ * (+ZI) } ; Application ZI data (.bss)
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ARM_LIB_HEAP (__RAM_BASE
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+__RW_DATA_SIZE
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+__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
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{ }
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ARM_LIB_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE
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-__IRQ_STACK_SIZE
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-__SVC_STACK_SIZE
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-__ABT_STACK_SIZE
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-__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
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{ }
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UND_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE
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-__IRQ_STACK_SIZE
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-__SVC_STACK_SIZE
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-__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
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{ }
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ABT_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE
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-__IRQ_STACK_SIZE
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-__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
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{ }
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SVC_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE
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-__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
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{ }
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IRQ_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
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{ }
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FIQ_STACK (__RAM_BASE
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+__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
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{ }
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TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
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{ }
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}
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@ -0,0 +1,101 @@
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/**************************************************************************//**
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* @file mem_ARMCA5.h
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* @brief Memory base and size definitions (used in scatter file)
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* @version V1.1.0
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* @date 15. May 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __MEM_ARMCA5_H
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#define __MEM_ARMCA5_H
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/*----------------------------------------------------------------------------
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User Stack & Heap size definition
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*----------------------------------------------------------------------------*/
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- ROM Configuration ------------------------------------
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//
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// <h> ROM Configuration
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// <i> For compatibility with MMU config the sections must be multiple of 1MB
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// <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
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// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __ROM_BASE 0x80000000
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#define __ROM_SIZE 0x00400000
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/*--------------------- RAM Configuration -----------------------------------
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// <h> RAM Configuration
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// <i> For compatibility with MMU config the sections must be multiple of 1MB
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// <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000>
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// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
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// <h> Data Sections
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// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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// <h> Stack / Heap Configuration
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// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <h> Exceptional Modes
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// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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// </h>
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// </h>
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*----------------------------------------------------------------------------*/
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//#define __RAM_BASE 0x80200000#
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#define __RAM_BASE 0x80600000
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#define __RAM_SIZE 0x00700000
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#define __RW_DATA_SIZE 0x00200000
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#define __ZI_DATA_SIZE 0x00200000
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#define __STACK_SIZE 0x00007000
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#define __HEAP_SIZE 0x00200000
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#define __UND_STACK_SIZE 0x00000100
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#define __ABT_STACK_SIZE 0x00000100
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#define __SVC_STACK_SIZE 0x00000100
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#define __IRQ_STACK_SIZE 0x00000100
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#define __FIQ_STACK_SIZE 0x00000100
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/*----------------------------------------------------------------------------*/
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/*--------------------- TTB Configuration ------------------------------------
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//
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// <h> TTB Configuration
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// <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
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// <i> The TLB L2 entries are placed after the L1 in the MMU config
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// <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
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// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __TTB_BASE 0x80500000
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#define __TTB_SIZE 0x00005000
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#endif /* __MEM_ARMCA5_H */
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@ -0,0 +1,65 @@
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/******************************************************************************
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* @file system_ARMCA5.h
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* @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
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* @version V1.00
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* @date 10. January 2018
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __SYSTEM_ARMCA5_H
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#define __SYSTEM_ARMCA5_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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\brief Setup the microcontroller system.
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Initialize the System and update the SystemCoreClock variable.
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*/
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extern void SystemInit (void);
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/**
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\brief Update SystemCoreClock variable.
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Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate (void);
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/**
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\brief Create Translation Table.
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Creates Memory Management Unit Translation Table.
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*/
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extern void MMU_CreateTranslationTable(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_ARMCA5_H */
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@ -0,0 +1,138 @@
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/******************************************************************************
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* @file startup_ARMCA5.c
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* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
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* @version V1.00
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* @date 10. January 2018
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <ARMCA5.h>
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/*----------------------------------------------------------------------------
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Definitions
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*----------------------------------------------------------------------------*/
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#define USR_MODE 0x10 // User mode
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#define FIQ_MODE 0x11 // Fast Interrupt Request mode
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#define IRQ_MODE 0x12 // Interrupt Request mode
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#define SVC_MODE 0x13 // Supervisor mode
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#define ABT_MODE 0x17 // Abort mode
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#define UND_MODE 0x1B // Undefined Instruction mode
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#define SYS_MODE 0x1F // System mode
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/*----------------------------------------------------------------------------
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Internal References
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*----------------------------------------------------------------------------*/
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void Vectors (void) __attribute__ ((naked, section("RESET")));
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void Reset_Handler (void) __attribute__ ((naked));
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/*----------------------------------------------------------------------------
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Exception / Interrupt Handler
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*----------------------------------------------------------------------------*/
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void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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/*----------------------------------------------------------------------------
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Exception / Interrupt Vector Table
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*----------------------------------------------------------------------------*/
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void Vectors(void) {
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__ASM volatile(
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"LDR PC, =Reset_Handler \n"
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"LDR PC, =Undef_Handler \n"
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"LDR PC, =SVC_Handler \n"
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"LDR PC, =PAbt_Handler \n"
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"LDR PC, =DAbt_Handler \n"
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"NOP \n"
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"LDR PC, =IRQ_Handler \n"
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"LDR PC, =FIQ_Handler \n"
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);
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}
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/*----------------------------------------------------------------------------
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Reset Handler called on controller reset
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*----------------------------------------------------------------------------*/
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void Reset_Handler(void) {
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__ASM volatile(
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// Mask interrupts
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"CPSID if \n"
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// Put any cores other than 0 to sleep
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"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
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"ANDS R0, R0, #3 \n"
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"goToSleep: \n"
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"WFINE \n"
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"BNE goToSleep \n"
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// Reset SCTLR Settings
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"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
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"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
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"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
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"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
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"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
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"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
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"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
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"ISB \n"
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// Configure ACTLR
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"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
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"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
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"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
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// Set Vector Base Address Register (VBAR) to point to this application's vector table
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"LDR R0, =Vectors \n"
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"MCR p15, 0, R0, c12, c0, 0 \n"
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// Setup Stack for each exceptional mode
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"CPS #0x11 \n"
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"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
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"CPS #0x12 \n"
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"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
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"CPS #0x13 \n"
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"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
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"CPS #0x17 \n"
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"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
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"CPS #0x1B \n"
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"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
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"CPS #0x1F \n"
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"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
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// Call SystemInit
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"BL SystemInit \n"
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// Unmask interrupts
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"CPSIE if \n"
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// Call __main
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"BL __main \n"
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);
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}
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/*----------------------------------------------------------------------------
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Default Handler for Exceptions / Interrupts
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*----------------------------------------------------------------------------*/
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void Default_Handler(void) {
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while(1);
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}
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@ -0,0 +1,75 @@
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#! armcc -E
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; command above MUST be in first line (no comment above!)
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/*
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;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
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*/
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#include "mem_ARMCM0.h"
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/*--------------------- Flash Configuration ----------------------------------
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; <h> Flash Configuration
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; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
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; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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*----------------------------------------------------------------------------*/
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#define __ROM_BASE 0x00000000
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#define __ROM_SIZE 0x00200000
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/*--------------------- Embedded RAM Configuration ---------------------------
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; <h> RAM Configuration
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; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
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; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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*----------------------------------------------------------------------------*/
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#define __RAM_BASE 0x20000000
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#define __RAM_SIZE 0x00200000
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/*--------------------- Stack / Heap Configuration ---------------------------
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; <h> Stack / Heap Configuration
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; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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*----------------------------------------------------------------------------*/
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#define __STACK_SIZE STACK_SIZE
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#define __HEAP_SIZE HEAP_SIZE
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/*----------------------------------------------------------------------------
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User Stack & Heap boundery definition
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*----------------------------------------------------------------------------*/
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#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
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#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
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/*----------------------------------------------------------------------------
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Scatter File Definitions definition
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*----------------------------------------------------------------------------*/
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#define __RO_BASE __ROM_BASE
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#define __RO_SIZE __ROM_SIZE
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#define __RW_BASE (__RAM_BASE )
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#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
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LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
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ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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.ANY (+XO)
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}
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RW_RAM __RW_BASE __RW_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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#if __HEAP_SIZE > 0
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ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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}
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#endif
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ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
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}
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}
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@ -0,0 +1,38 @@
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/**************************************************************************//**
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* @file mem_ARMCM7.h
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* @brief Memory base and size definitions (used in scatter file)
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* @version V1.1.0
|
||||
* @date 15. May 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __MEM_ARMCM0_H
|
||||
#define __MEM_ARMCM0_H
|
||||
|
||||
|
||||
|
||||
#define STACK_SIZE 0x00003000
|
||||
#define HEAP_SIZE 0x00100000
|
||||
|
||||
|
||||
|
||||
#endif /* __MEM_ARMCM0_H */
|
||||
@ -0,0 +1,168 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM7.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM7 Device
|
||||
; * @version V5.4.0
|
||||
; * @date 12. December 2018
|
||||
; ******************************************************************************/
|
||||
;/*
|
||||
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
|
||||
#include "mem_ARMCM0.h"
|
||||
|
||||
;<h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;</h>
|
||||
|
||||
Stack_Size EQU STACK_SIZE
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
__stack_limit
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
;<h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;</h>
|
||||
|
||||
Heap_Size EQU HEAP_SIZE
|
||||
|
||||
IF Heap_Size != 0 ; Heap is provided
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
ENDIF
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; -14 NMI Handler
|
||||
DCD HardFault_Handler ; -13 Hard Fault Handler
|
||||
DCD MemManage_Handler ; -12 MPU Fault Handler
|
||||
DCD BusFault_Handler ; -11 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; -10 Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; -5 SVCall Handler
|
||||
DCD DebugMon_Handler ; -4 Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; -2 PendSV Handler
|
||||
DCD SysTick_Handler ; -1 SysTick Handler
|
||||
|
||||
; Interrupts
|
||||
DCD Interrupt0_Handler ; 0 Interrupt 0
|
||||
DCD Interrupt1_Handler ; 1 Interrupt 1
|
||||
DCD Interrupt2_Handler ; 2 Interrupt 2
|
||||
DCD Interrupt3_Handler ; 3 Interrupt 3
|
||||
DCD Interrupt4_Handler ; 4 Interrupt 4
|
||||
DCD Interrupt5_Handler ; 5 Interrupt 5
|
||||
DCD Interrupt6_Handler ; 6 Interrupt 6
|
||||
DCD Interrupt7_Handler ; 7 Interrupt 7
|
||||
DCD Interrupt8_Handler ; 8 Interrupt 8
|
||||
DCD Interrupt9_Handler ; 9 Interrupt 9
|
||||
|
||||
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
|
||||
__Vectors_End
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Macro to define default exception/interrupt handlers.
|
||||
; Default handler are weak symbols with an endless loop.
|
||||
; They can be overwritten by real handlers.
|
||||
MACRO
|
||||
Set_Default_Handler $Handler_Name
|
||||
$Handler_Name PROC
|
||||
EXPORT $Handler_Name [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MEND
|
||||
|
||||
|
||||
; Default exception/interrupt handler
|
||||
|
||||
Set_Default_Handler NMI_Handler
|
||||
Set_Default_Handler HardFault_Handler
|
||||
Set_Default_Handler MemManage_Handler
|
||||
Set_Default_Handler BusFault_Handler
|
||||
Set_Default_Handler UsageFault_Handler
|
||||
Set_Default_Handler SVC_Handler
|
||||
Set_Default_Handler DebugMon_Handler
|
||||
Set_Default_Handler PendSV_Handler
|
||||
Set_Default_Handler SysTick_Handler
|
||||
|
||||
Set_Default_Handler Interrupt0_Handler
|
||||
Set_Default_Handler Interrupt1_Handler
|
||||
Set_Default_Handler Interrupt2_Handler
|
||||
Set_Default_Handler Interrupt3_Handler
|
||||
Set_Default_Handler Interrupt4_Handler
|
||||
Set_Default_Handler Interrupt5_Handler
|
||||
Set_Default_Handler Interrupt6_Handler
|
||||
Set_Default_Handler Interrupt7_Handler
|
||||
Set_Default_Handler Interrupt8_Handler
|
||||
Set_Default_Handler Interrupt9_Handler
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User setup Stack & Heap
|
||||
|
||||
IF :LNOT::DEF:__MICROLIB
|
||||
IMPORT __use_two_region_memory
|
||||
ENDIF
|
||||
|
||||
EXPORT __stack_limit
|
||||
EXPORT __initial_sp
|
||||
IF Heap_Size != 0 ; Heap is provided
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
ENDIF
|
||||
|
||||
END
|
||||
Loading…
Reference in New Issue