CMSIS-DSP: Added SVM Functions and tests

Added more tests for BasicMathFunctions
Added script to postprocess result of benchmarks.

ComputeLibrary/Include/NEMath.h

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+/*
+ * Copyright (c) 2016, 2019 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef __ARM_COMPUTE_NEMATH_H__
+#define __ARM_COMPUTE_NEMATH_H__
+
+
+#if defined(ARM_MATH_NEON)
+/** Calculate floor of a vector.
+ *
+ * @param[in] val Input vector value in F32 format.
+ *
+ * @return The calculated floor vector.
+ */
+static inline float32x4_t vfloorq_f32(float32x4_t val);
+
+/** Calculate inverse square root.
+ *
+ * @param[in] x Input value.
+ *
+ * @return The calculated inverse square root.
+ */
+static inline float32x2_t vinvsqrt_f32(float32x2_t x);
+
+/** Calculate inverse square root.
+ *
+ * @param[in] x Input value.
+ *
+ * @return The calculated inverse square root.
+ */
+static inline float32x4_t vinvsqrtq_f32(float32x4_t x);
+
+/** Calculate reciprocal.
+ *
+ * @param[in] x Input value.
+ *
+ * @return The calculated reciprocal.
+ */
+static inline float32x2_t vinv_f32(float32x2_t x);
+
+/** Calculate reciprocal.
+ *
+ * @param[in] x Input value.
+ *
+ * @return The calculated reciprocal.
+ */
+static inline float32x4_t vinvq_f32(float32x4_t x);
+
+/** Perform a 7th degree polynomial approximation using Estrin's method.
+ *
+ * @param[in] x      Input vector value in F32 format.
+ * @param[in] coeffs Polynomial coefficients table.
+ *
+ * @return The calculated approximation.
+ */
+static inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32x4_t *coeffs);
+
+/** Calculate exponential
+ *
+ * @param[in] x Input vector value in F32 format.
+ *
+ * @return The calculated exponent.
+ */
+static inline float32x4_t vexpq_f32(float32x4_t x);
+
+/** Calculate logarithm
+ *
+ * @param[in] x Input vector value in F32 format.
+ *
+ * @return The calculated logarithm.
+ */
+static inline float32x4_t vlogq_f32(float32x4_t x);
+
+/** Calculate hyperbolic tangent.
+ *
+ * tanh(x) = (e^2x - 1)/(e^2x + 1)
+ *
+ * @note We clamp x to [-5,5] to avoid overflowing issues.
+ *
+ * @param[in] val Input vector value in F32 format.
+ *
+ * @return The calculated Hyperbolic Tangent.
+ */
+static inline float32x4_t vtanhq_f32(float32x4_t val);
+
+/** Calculate n power of a number.
+ *
+ * pow(x,n) = e^(n*log(x))
+ *
+ * @param[in] val Input vector value in F32 format.
+ * @param[in] n   Powers to raise the input to.
+ *
+ * @return The calculated power.
+ */
+static inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n);
+
+#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
+/** Calculate hyperbolic tangent.
+ *
+ * tanh(x) = (e^2x - 1)/(e^2x + 1)
+ *
+ * @note We clamp x to [-5,5] to avoid overflowing issues.
+ *
+ * @param[in] val Input vector value in F32 format.
+ *
+ * @return The calculated Hyperbolic Tangent.
+ */
+static inline float16x8_t vtanhq_f16(float16x8_t val);
+
+/** Calculate reciprocal.
+ *
+ * @param[in] x Input value.
+ *
+ * @return The calculated reciprocal.
+ */
+static inline float16x4_t vinv_f16(float16x4_t x);
+
+/** Calculate reciprocal.
+ *
+ * @param[in] x Input value.
+ *
+ * @return The calculated reciprocal.
+ */
+static inline float16x8_t vinvq_f16(float16x8_t x);
+
+/** Calculate inverse square root.
+ *
+ * @param[in] x Input value.
+ *
+ * @return The calculated inverse square root.
+ */
+static inline float16x4_t vinvsqrt_f16(float16x4_t x);
+
+/** Calculate inverse square root.
+ *
+ * @param[in] x Input value.
+ *
+ * @return The calculated inverse square root.
+ */
+static inline float16x8_t vinvsqrtq_f16(float16x8_t x);
+
+/** Calculate exponential
+ *
+ * @param[in] x Input vector value in F16 format.
+ *
+ * @return The calculated exponent.
+ */
+static inline float16x8_t vexpq_f16(float16x8_t x);
+
+/** Calculate n power of a number.
+ *
+ * pow(x,n) = e^(n*log(x))
+ *
+ * @param[in] val Input vector value in F16 format.
+ * @param[in] n   Powers to raise the input to.
+ *
+ * @return The calculated power.
+ */
+static inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n);
+#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
+
+/** Exponent polynomial coefficients */
+extern const float32x4_t exp_tab[8];
+
+
+/** Logarithm polynomial coefficients */
+extern const float32x4_t log_tab[8];
+
+#ifndef DOXYGEN_SKIP_THIS
+inline float32x4_t vfloorq_f32(float32x4_t val)
+{
+    static const float32x4_t CONST_1 = {1.f,1.f,1.f,1.f};
+
+    const int32x4_t   z = vcvtq_s32_f32(val);
+    const float32x4_t r = vcvtq_f32_s32(z);
+
+    return vbslq_f32(vcgtq_f32(r, val), vsubq_f32(r, CONST_1), r);
+}
+
+inline float32x2_t vinvsqrt_f32(float32x2_t x)
+{
+    float32x2_t sqrt_reciprocal = vrsqrte_f32(x);
+    sqrt_reciprocal             = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
+    sqrt_reciprocal             = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
+
+    return sqrt_reciprocal;
+}
+
+inline float32x4_t vinvsqrtq_f32(float32x4_t x)
+{
+    float32x4_t sqrt_reciprocal = vrsqrteq_f32(x);
+    sqrt_reciprocal             = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
+    sqrt_reciprocal             = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
+
+    return sqrt_reciprocal;
+}
+
+inline float32x2_t vinv_f32(float32x2_t x)
+{
+    float32x2_t recip = vrecpe_f32(x);
+    recip             = vmul_f32(vrecps_f32(x, recip), recip);
+    recip             = vmul_f32(vrecps_f32(x, recip), recip);
+    return recip;
+}
+
+inline float32x4_t vinvq_f32(float32x4_t x)
+{
+    float32x4_t recip = vrecpeq_f32(x);
+    recip             = vmulq_f32(vrecpsq_f32(x, recip), recip);
+    recip             = vmulq_f32(vrecpsq_f32(x, recip), recip);
+    return recip;
+}
+
+inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32x4_t *coeffs)
+{
+    float32x4_t A   = vmlaq_f32(coeffs[0], coeffs[4], x);
+    float32x4_t B   = vmlaq_f32(coeffs[2], coeffs[6], x);
+    float32x4_t C   = vmlaq_f32(coeffs[1], coeffs[5], x);
+    float32x4_t D   = vmlaq_f32(coeffs[3], coeffs[7], x);
+    float32x4_t x2  = vmulq_f32(x, x);
+    float32x4_t x4  = vmulq_f32(x2, x2);
+    float32x4_t res = vmlaq_f32(vmlaq_f32(A, B, x2), vmlaq_f32(C, D, x2), x4);
+    return res;
+}
+
+inline float32x4_t vexpq_f32(float32x4_t x)
+{
+    static const float32x4_t CONST_LN2          = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2)
+    static const float32x4_t CONST_INV_LN2      = {1.4426950408f,1.4426950408f,1.4426950408f,1.4426950408f}; // 1/ln(2)
+    static const float32x4_t CONST_0            = {0.f,0.f,0.f,0.f};
+    static const int32x4_t   CONST_NEGATIVE_126 = {-126,-126,-126,-126};
+
+    // Perform range reduction [-log(2),log(2)]
+    int32x4_t   m   = vcvtq_s32_f32(vmulq_f32(x, CONST_INV_LN2));
+    float32x4_t val = vmlsq_f32(x, vcvtq_f32_s32(m), CONST_LN2);
+
+    // Polynomial Approximation
+    float32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
+
+    // Reconstruct
+    poly = vreinterpretq_f32_s32(vqaddq_s32(vreinterpretq_s32_f32(poly), vqshlq_n_s32(m, 23)));
+    poly = vbslq_f32(vcltq_s32(m, CONST_NEGATIVE_126), CONST_0, poly);
+
+    return poly;
+}
+
+inline float32x4_t vlogq_f32(float32x4_t x)
+{
+    static const int32x4_t   CONST_127 = {127,127,127,127};           // 127
+    static const float32x4_t CONST_LN2 = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2)
+
+    // Extract exponent
+    int32x4_t   m   = vsubq_s32(vreinterpretq_s32_u32(vshrq_n_u32(vreinterpretq_u32_f32(x), 23)), CONST_127);
+    float32x4_t val = vreinterpretq_f32_s32(vsubq_s32(vreinterpretq_s32_f32(x), vshlq_n_s32(m, 23)));
+
+    // Polynomial Approximation
+    float32x4_t poly = vtaylor_polyq_f32(val, log_tab);
+
+    // Reconstruct
+    poly = vmlaq_f32(poly, vcvtq_f32_s32(m), CONST_LN2);
+
+    return poly;
+}
+
+inline float32x4_t vtanhq_f32(float32x4_t val)
+{
+    static const float32x4_t CONST_1        = {1.f,1.f,1.f,1.f};
+    static const float32x4_t CONST_2        = {2.f,2.f,2.f,2.f};
+    static const float32x4_t CONST_MIN_TANH = {-10.f,-10.f,-10.f,-10.f};
+    static const float32x4_t CONST_MAX_TANH = {10.f,10.f,10.f,10.f};
+
+    float32x4_t x     = vminq_f32(vmaxq_f32(val, CONST_MIN_TANH), CONST_MAX_TANH);
+    float32x4_t exp2x = vexpq_f32(vmulq_f32(CONST_2, x));
+    float32x4_t num   = vsubq_f32(exp2x, CONST_1);
+    float32x4_t den   = vaddq_f32(exp2x, CONST_1);
+    float32x4_t tanh  = vmulq_f32(num, vinvq_f32(den));
+    return tanh;
+}
+
+inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n)
+{
+    return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
+}
+#endif /* DOXYGEN_SKIP_THIS */
+
+#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
+/** Exponent polynomial coefficients */
+/** Logarithm polynomial coefficients */
+#ifndef DOXYGEN_SKIP_THIS
+inline float16x8_t vfloorq_f16(float16x8_t val)
+{
+    static const float16x8_t CONST_1 = {1.f,1.f,1.f,1.f};
+
+    const int16x8_t   z = vcvtq_s16_f16(val);
+    const float16x8_t r = vcvtq_f16_s16(z);
+
+    return vbslq_f16(vcgtq_f16(r, val), vsubq_f16(r, CONST_1), r);
+}
+inline float16x4_t vinvsqrt_f16(float16x4_t x)
+{
+    float16x4_t sqrt_reciprocal = vrsqrte_f16(x);
+    sqrt_reciprocal             = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
+    sqrt_reciprocal             = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
+    return sqrt_reciprocal;
+}
+
+inline float16x8_t vinvsqrtq_f16(float16x8_t x)
+{
+    float16x8_t sqrt_reciprocal = vrsqrteq_f16(x);
+    sqrt_reciprocal             = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
+    sqrt_reciprocal             = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
+    return sqrt_reciprocal;
+}
+
+inline float16x4_t vinv_f16(float16x4_t x)
+{
+    float16x4_t recip = vrecpe_f16(x);
+    recip             = vmul_f16(vrecps_f16(x, recip), recip);
+    recip             = vmul_f16(vrecps_f16(x, recip), recip);
+    return recip;
+}
+
+inline float16x8_t vinvq_f16(float16x8_t x)
+{
+    float16x8_t recip = vrecpeq_f16(x);
+    recip             = vmulq_f16(vrecpsq_f16(x, recip), recip);
+    recip             = vmulq_f16(vrecpsq_f16(x, recip), recip);
+    return recip;
+}
+
+inline float16x8_t vtanhq_f16(float16x8_t val)
+{
+    const float16x8_t CONST_1        = {1.f,1.f,1.f,1.f};
+    const float16x8_t CONST_2        = {2.f,2.f,2.f,2.f};
+    const float16x8_t CONST_MIN_TANH = {-10.f,-10.f,-10.f,-10.f};
+    const float16x8_t CONST_MAX_TANH = {10.f,10.f,10.f,10.f};
+
+    const float16x8_t x     = vminq_f16(vmaxq_f16(val, CONST_MIN_TANH), CONST_MAX_TANH);
+    const float16x8_t exp2x = vexpq_f16(vmulq_f16(CONST_2, x));
+    const float16x8_t num   = vsubq_f16(exp2x, CONST_1);
+    const float16x8_t den   = vaddq_f16(exp2x, CONST_1);
+    const float16x8_t tanh  = vmulq_f16(num, vinvq_f16(den));
+    return tanh;
+}
+
+inline float16x8_t vtaylor_polyq_f16(float16x8_t x, const std::array<float16x8_t, 8> &coeffs)
+{
+    const float16x8_t A   = vaddq_f16(coeffs[0], vmulq_f16(coeffs[4], x));
+    const float16x8_t B   = vaddq_f16(coeffs[2], vmulq_f16(coeffs[6], x));
+    const float16x8_t C   = vaddq_f16(coeffs[1], vmulq_f16(coeffs[5], x));
+    const float16x8_t D   = vaddq_f16(coeffs[3], vmulq_f16(coeffs[7], x));
+    const float16x8_t x2  = vmulq_f16(x, x);
+    const float16x8_t x4  = vmulq_f16(x2, x2);
+    const float16x8_t res = vaddq_f16(vaddq_f16(A, vmulq_f16(B, x2)), vmulq_f16(vaddq_f16(C, vmulq_f16(D, x2)), x4));
+    return res;
+}
+
+inline float16x8_t vexpq_f16(float16x8_t x)
+{
+    // TODO (COMPMID-1535) : Revisit FP16 approximations
+    const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x));
+    const float32x4_t x_low  = vcvt_f32_f16(vget_low_f16(x));
+
+    const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vexpq_f32(x_low)), vexpq_f32(x_high));
+    return res;
+}
+
+inline float16x8_t vlogq_f16(float16x8_t x)
+{
+    // TODO (COMPMID-1535) : Revisit FP16 approximations
+    const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x));
+    const float32x4_t x_low  = vcvt_f32_f16(vget_low_f16(x));
+
+    const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vlogq_f32(x_low)), vlogq_f32(x_high));
+    return res;
+}
+
+inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n)
+{
+    // TODO (giaiod01) - COMPMID-1535
+    float32x4_t n0_f32   = vcvt_f32_f16(vget_low_f16(n));
+    float32x4_t n1_f32   = vcvt_f32_f16(vget_high_f16(n));
+    float32x4_t val0_f32 = vcvt_f32_f16(vget_low_f16(val));
+    float32x4_t val1_f32 = vcvt_f32_f16(vget_high_f16(val));
+
+    float32x4_t res0_f32 = vexpq_f32(vmulq_f32(n0_f32, vlogq_f32(val0_f32)));
+    float32x4_t res1_f32 = vexpq_f32(vmulq_f32(n1_f32, vlogq_f32(val1_f32)));
+
+    return vcombine_f16(vcvt_f16_f32(res0_f32), vcvt_f16_f32(res1_f32));
+}
+#endif /* DOXYGEN_SKIP_THIS */
+#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
+#endif
+#endif /* __ARM_COMPUTE_NEMATH_H__ */

ComputeLibrary/LICENSE.txt

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2017-2019 ARM Software
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

ComputeLibrary/README.md

@@ -0,0 +1,19 @@
+README
+======
+
+This folder is containing two files imported, and slightly modified, from the ComputeLibrary:
+
+    NEMath.h and arm_cl_tables.c 
+
+In the original compute library, there are instead two other files:
+
+    NEMath.h and NEMath.inl
+
+NEMath.inl is included from NEMath.h whereas in this CMSIS DSP implementation, there is no NEMath.inl and its content is copied into NEMath.h
+
+The tables contained in NEMath.inl have been moved to arm_cl_tables.c and finally the files are in C for the CMSIS DSP library and in C++ in the original Compute Library.
+
+Otherwise, the features and implementations are the same : a few optimized Neon functions.
+
+The license covering those files is different : It is a MIT license.
+Other parts of the CMSIS-DSP are covered with an Apache-2.0 license.

ComputeLibrary/Source/arm_cl_tables.c

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016, 2019 ARM Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "arm_math.h"
+#include "NEMath.h"
+
+#if defined(ARM_MATH_NEON)
+
+/** Exponent polynomial coefficients */
+const float32x4_t exp_tab[8] =
+{
+        {1.f,1.f,1.f,1.f},
+        {0.0416598916054f,0.0416598916054f,0.0416598916054f,0.0416598916054f},
+        {0.500000596046f,0.500000596046f,0.500000596046f,0.500000596046f},
+        {0.0014122662833f,0.0014122662833f,0.0014122662833f,0.0014122662833f},
+        {1.00000011921f,1.00000011921f,1.00000011921f,1.00000011921f},
+        {0.00833693705499f,0.00833693705499f,0.00833693705499f,0.00833693705499f},
+        {0.166665703058f,0.166665703058f,0.166665703058f,0.166665703058f},
+        {0.000195780929062f,0.000195780929062f,0.000195780929062f,0.000195780929062f}
+};
+
+/** Logarithm polynomial coefficients */
+const float32x4_t log_tab[8] =
+{
+        {-2.29561495781f,-2.29561495781f,-2.29561495781f,-2.29561495781f},
+        {-2.47071170807f,-2.47071170807f,-2.47071170807f,-2.47071170807f},
+        {-5.68692588806f,-5.68692588806f,-5.68692588806f,-5.68692588806f},
+        {-0.165253549814f,-0.165253549814f,-0.165253549814f,-0.165253549814f},
+        {5.17591238022f,5.17591238022f,5.17591238022f,5.17591238022f},
+        {0.844007015228f,0.844007015228f,0.844007015228f,0.844007015228f},
+        {4.58445882797f,4.58445882797f,4.58445882797f,4.58445882797f},
+        {0.0141278216615f,0.0141278216615f,0.0141278216615f,0.0141278216615f},
+};
+
+#endif

Include/arm_math.h

@@ -275,6 +275,9 @@
  * @defgroup groupExamples Examples
  */
 
+/**
+ * @defgroup groupSVM SVM Functions
+ */
 
 #ifndef _ARM_MATH_H
 #define _ARM_MATH_H
@@ -446,6 +449,9 @@ extern "C"
 #define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE * )   (addr))
 #define __SIMD64(addr)        (*(      int64_t **) & (addr))
 
+#define STEP(x) (x) <= 0 ? 0 : 1
+#define SQ(x) ((x) * (x))
+
 /* SIMD replacement */
 
 
@@ -819,8 +825,47 @@ compiler file in Core or Core_A would not make sense.
     return (signBits + 1);
   }
 
+/**
+ * @brief Integer exponentiation
+ * @param[in]    x           value
+ * @param[in]    nb          integer exponent >= 1
+ * @return x^nb
+ *
+ */
+static inline float32_t arm_exponent_f32(float32_t x, int nb)
+{
+    float32_t r = x;
+    nb --;
+    while(nb > 0)
+    {
+        r = r * x;
+        nb--;
+    }
+    return(r);
+}
+
 #if defined(ARM_MATH_NEON)
 
+/**
+ * @brief Vectorized integer exponentiation
+ * @param[in]    x           value
+ * @param[in]    nb          integer exponent >= 1
+ * @return x^nb
+ *
+ */
+static inline  float32x4_t arm_vec_exponent_f32(float32x4_t x, int nb)
+{
+    float32x4_t r = x;
+    nb --;
+    while(nb > 0)
+    {
+        r = vmulq_f32(r , x);
+        nb--;
+    }
+    return(r);
+}
+
+
 static inline float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t  x)
 {
     float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
@@ -6866,6 +6911,233 @@ arm_status arm_sqrt_q15(
         q15_t * pDst,
         uint32_t blockSize);
 
+  /**
+ * @brief Struct for specifying SVM Kernel
+ *
+ */
+typedef enum
+{
+    ARM_ML_KERNEL_LINEAR = 0,
+             /**< Linear kernel */
+    ARM_ML_KERNEL_POLYNOMIAL = 1,
+             /**< Polynomial kernel */
+    ARM_ML_KERNEL_RBF = 2,
+             /**< Radial Basis Function kernel */
+    ARM_ML_KERNEL_SIGMOID = 3
+             /**< Sigmoid kernel */
+} arm_ml_kernel_type;
+
+
+
+/**
+ * @brief Instance structure for linear SVM prediction function.
+ */
+typedef struct
+{
+  uint32_t        nbOfSupportVectors;     /**< Number of support vectors */
+  uint32_t        vectorDimension;        /**< Dimension of vector space */
+  float32_t       intercept;              /**< Intercept */
+  const float32_t *dualCoefficients;      /**< Dual coefficients */
+  const float32_t *supportVectors;        /**< Support vectors */
+  const int32_t   *classes;               /**< The two SVM classes */
+} arm_svm_linear_instance_f32;
+
+
+/**
+ * @brief Instance structure for polynomial SVM prediction function.
+ */
+typedef struct
+{
+  uint32_t        nbOfSupportVectors;     /**< Number of support vectors */
+  uint32_t        vectorDimension;        /**< Dimension of vector space */
+  float32_t       intercept;              /**< Intercept */
+  const float32_t *dualCoefficients;      /**< Dual coefficients */
+  const float32_t *supportVectors;        /**< Support vectors */
+  const int32_t   *classes;               /**< The two SVM classes */
+  int             degree;                 /**< Polynomial degree */
+  float32_t       coef0;                  /**< Polynomial constant */
+  float32_t       gamma;                  /**< Gamma factor */
+} arm_svm_polynomial_instance_f32;
+
+/**
+ * @brief Instance structure for rbf SVM prediction function.
+ */
+typedef struct
+{
+  uint32_t        nbOfSupportVectors;     /**< Number of support vectors */
+  uint32_t        vectorDimension;        /**< Dimension of vector space */
+  float32_t       intercept;              /**< Intercept */
+  const float32_t *dualCoefficients;      /**< Dual coefficients */
+  const float32_t *supportVectors;        /**< Support vectors */
+  const int32_t   *classes;               /**< The two SVM classes */
+  float32_t       gamma;                  /**< Gamma factor */
+} arm_svm_rbf_instance_f32;
+
+/**
+ * @brief Instance structure for sigmoid SVM prediction function.
+ */
+typedef struct
+{
+  uint32_t        nbOfSupportVectors;     /**< Number of support vectors */
+  uint32_t        vectorDimension;        /**< Dimension of vector space */
+  float32_t       intercept;              /**< Intercept */
+  const float32_t *dualCoefficients;      /**< Dual coefficients */
+  const float32_t *supportVectors;        /**< Support vectors */
+  const int32_t   *classes;               /**< The two SVM classes */
+  float32_t       coef0;                  /**< Independant constant */
+  float32_t       gamma;                  /**< Gamma factor */
+} arm_svm_sigmoid_instance_f32;
+
+/**
+ * @brief        SVM linear instance init function
+ * @param[in]    nbOfSupportVectors     Number of support vectors
+ * @param[in]    vectorDimension        Dimension of vector space
+ * @param[in]    intercept              Intercept
+ * @param[in]    dualCoefficients       Array of dual coefficients
+ * @param[in]    supportVectors         Array of support vectors
+ * @param[in]    classes                Array of 2 classes ID
+ * @return none.
+ *
+ */
+
+
+void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, 
+  uint32_t nbOfSupportVectors,
+  uint32_t vectorDimension,
+  float32_t intercept,
+  const float32_t *dualCoefficients,
+  const float32_t *supportVectors,
+  const int32_t  *classes);
+
+/**
+ * @brief SVM linear prediction
+ * @param[in]    *S          points to an instance of the linear SVM structure.
+ * @param[in]    vec_in      pointer to input vector
+ * @param[out]   *pResult    decision value
+ * @return none.
+ *
+ */
+  
+void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, 
+   const float32_t * in, 
+   int * pResult);
+
+
+/**
+ * @brief        SVM polynomial instance init function
+ * @param[in]    nbOfSupportVectors     Number of support vectors
+ * @param[in]    vectorDimension        Dimension of vector space
+ * @param[in]    intercept              Intercept
+ * @param[in]    dualCoefficients       Array of dual coefficients
+ * @param[in]    supportVectors         Array of support vectors
+ * @param[in]    classes                Array of 2 classes ID
+ * @param[in]    degree                 Polynomial degree
+ * @param[in]    coef0                  coeff0 (scikit-learn terminology)
+ * @param[in]    gamma                  gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+
+void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, 
+  uint32_t nbOfSupportVectors,
+  uint32_t vectorDimension,
+  float32_t intercept,
+  const float32_t *dualCoefficients,
+  const float32_t *supportVectors,
+  const int32_t   *classes,
+  int      degree,
+  float32_t coef0,
+  float32_t gamma
+  );
+
+/**
+ * @brief SVM polynomial prediction
+ * @param[in]    *S          points to an instance of the polynomial SVM structure.
+ * @param[in]    vec_in      pointer to input vector
+ * @param[out]   *pResult    decision value
+ * @return none.
+ *
+ */
+  
+void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, 
+   const float32_t * in, 
+   int * pResult);
+
+
+/**
+ * @brief        SVM radial basis function instance init function
+ * @param[in]    nbOfSupportVectors     Number of support vectors
+ * @param[in]    vectorDimension        Dimension of vector space
+ * @param[in]    intercept              Intercept
+ * @param[in]    dualCoefficients       Array of dual coefficients
+ * @param[in]    supportVectors         Array of support vectors
+ * @param[in]    classes                Array of 2 classes ID
+ * @param[in]    gamma                  gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, 
+  uint32_t nbOfSupportVectors,
+  uint32_t vectorDimension,
+  float32_t intercept,
+  const float32_t *dualCoefficients,
+  const float32_t *supportVectors,
+  const int32_t   *classes,
+  float32_t gamma
+  );
+
+/**
+ * @brief SVM rbf prediction
+ * @param[in]    *S          points to an instance of the rbf SVM structure.
+ * @param[in]    vec_in      pointer to input vector
+ * @param[out]   *pResult    decision value
+ * @return none.
+ *
+ */
+  
+void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, 
+   const float32_t * in, 
+   int * pResult);
+
+/**
+ * @brief        SVM sigmoid instance init function
+ * @param[in]    nbOfSupportVectors     Number of support vectors
+ * @param[in]    vectorDimension        Dimension of vector space
+ * @param[in]    intercept              Intercept
+ * @param[in]    dualCoefficients       Array of dual coefficients
+ * @param[in]    supportVectors         Array of support vectors
+ * @param[in]    classes                Array of 2 classes ID
+ * @param[in]    coef0                  coeff0 (scikit-learn terminology)
+ * @param[in]    gamma                  gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, 
+  uint32_t nbOfSupportVectors,
+  uint32_t vectorDimension,
+  float32_t intercept,
+  const float32_t *dualCoefficients,
+  const float32_t *supportVectors,
+  const int32_t   *classes,
+  float32_t coef0,
+  float32_t gamma
+  );
+
+/**
+ * @brief SVM sigmoid prediction
+ * @param[in]    *S          points to an instance of the rbf SVM structure.
+ * @param[in]    vec_in      pointer to input vector
+ * @param[out]   *pResult    decision value
+ * @return none.
+ *
+ */
+void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, 
+   const float32_t * in, 
+   int * pResult);
+
 
   /**
    * @ingroup groupInterpolation

Platforms/FVP/ARMCM0/Include/ARMCM0.h

@@ -0,0 +1,126 @@
+/**************************************************************************//**
+ * @file     ARMCM0.h
+ * @brief    CMSIS Core Peripheral Access Layer Header File for
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMCM0_H
+#define ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/* -------------------  Processor Exceptions Numbers  ----------------------------- */
+  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */
+  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */
+
+
+
+  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */
+
+  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */
+  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */
+
+/* -------------------  Processor Interrupt Numbers  ------------------------------ */
+  Interrupt0_IRQn               =   0,
+  Interrupt1_IRQn               =   1,
+  Interrupt2_IRQn               =   2,
+  Interrupt3_IRQn               =   3,
+  Interrupt4_IRQn               =   4,
+  Interrupt5_IRQn               =   5,
+  Interrupt6_IRQn               =   6,
+  Interrupt7_IRQn               =   7,
+  Interrupt8_IRQn               =   8,
+  Interrupt9_IRQn               =   9
+  /* Interrupts 10 .. 31 are left out */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* -------  Start of section using anonymous unions and disabling warnings  ------- */
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* --------  Configuration of Core Peripherals  ----------------------------------- */
+#define __CM0_REV                 0x0000U   /* Core revision r0p0 */
+#define __MPU_PRESENT             0U        /* no MPU present */
+#define __VTOR_PRESENT            0U        /* no VTOR present */
+#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
+
+#include "core_cm0.h"                       /* Processor and core peripherals */
+#include "system_ARMCM0.h"                  /* System Header */
+
+
+/* --------  End of section using anonymous unions and disabling warnings  -------- */
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ARMCM0_H */

Platforms/FVP/ARMCM0/Include/system_ARMCM0.h

@@ -0,0 +1,55 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.h
+ * @brief    CMSIS Device System Header File for
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_ARMCM0_H
+#define SYSTEM_ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM0_H */

Platforms/FVP/ARMCM0/LinkScripts/AC6/lnk.sct

@@ -0,0 +1,75 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+#include "mem_ARMCM0.h"
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE     0x00000000
+#define __ROM_SIZE     0x00100000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE     0x20000000
+#define __RAM_SIZE     0x00200000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE       STACK_SIZE
+#define __HEAP_SIZE        HEAP_SIZE
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundery definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP        (__RAM_BASE + __RAM_SIZE)      /* starts at end of RAM */
+#define __HEAP_BASE        (AlignExpr(+0, 8))             /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE         __ROM_BASE
+#define __RO_SIZE         __ROM_SIZE
+
+#define __RW_BASE        (__RAM_BASE        )
+#define __RW_SIZE        (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+
+LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
+  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data
+   .ANY (+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+}

Platforms/FVP/ARMCM0/LinkScripts/AC6/mem_ARMCM0.h

@@ -0,0 +1,38 @@
+/**************************************************************************//**
+ * @file     mem_ARMCM7.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.1.0
+ * @date     15. May 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCM0_H
+#define __MEM_ARMCM0_H
+
+
+
+#define STACK_SIZE     0x00003000
+#define HEAP_SIZE      0x00100000
+
+
+
+#endif /* __MEM_ARMCM7_H */

Platforms/FVP/ARMCM0/Startup/AC6/startup_ARMCM0.s

@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0 Device
+; * @version  V5.4.0
+; * @date     12. December 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+#include "mem_ARMCM0.h"
+
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Stack_Size      EQU      STACK_SIZE
+
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
+__initial_sp
+
+
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Heap_Size       EQU      HEAP_SIZE
+
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE    Heap_Size
+__heap_limit
+                ENDIF
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out
+__Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
+
+
+                AREA     |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
+                ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
+                ENDP
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
+
+                ALIGN
+
+
+; User setup Stack & Heap
+
+                IF       :LNOT::DEF:__MICROLIB
+                IMPORT   __use_two_region_memory
+                ENDIF
+
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
+                ENDIF
+
+                END

Platforms/FVP/ARMCM0/system_ARMCM0.c

@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (XTAL / 2U)
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Source/CMakeLists.txt

@@ -27,6 +27,7 @@ option(MATRIX               "Matrix Functions"                  ON)
 option(STATISTICS           "Statistics Functions"              ON)
 option(SUPPORT              "Support Functions"                 ON)
 option(TRANSFORM            "Transform Functions"               ON)
+option(SVM                  "Support Vector Machine Functions"  ON)
 
 # When OFF it is the default behavior : all tables are included.
 option(CONFIGTABLE          "Configuration of table allowed"    OFF)
@@ -224,6 +225,11 @@ if (FILTERING OR CONTROLLER OR FASTMATH OR TRANSFORM)
   target_link_libraries(CMSISDSP INTERFACE CMSISDSPCommon)
 endif()
 
+if (SVM)
+  add_subdirectory(SVMFunctions)
+  target_link_libraries(CMSISDSP INTERFACE CMSISDSPSVM)
+endif()
+
 ### Includes
 target_include_directories(CMSISDSP INTERFACE "${DSP}/Include")
 

Source/SVMFunctions/CMakeLists.txt

@@ -0,0 +1,22 @@
+cmake_minimum_required (VERSION 3.6)
+
+project(CMSISDSPSVM)
+
+include(config)
+include(configDsp)
+
+file(GLOB SRC "./*_*.c")
+
+add_library(CMSISDSPSVM STATIC ${SRC})
+
+configLib(CMSISDSPSVM ${ROOT})
+configDsp(CMSISDSPSVM ${ROOT})
+
+### Includes
+target_include_directories(CMSISDSPSVM PUBLIC "${DSP}/Include")
+
+
+if (NEON OR NEONEXPERIMENTAL)
+    target_sources(CMSISDSPSVM PRIVATE "${DSP}/ComputeLibrary/Source/arm_cl_tables.c")
+endif()
+

Source/SVMFunctions/arm_svm_linear_init_f32.c

@@ -0,0 +1,81 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_svm_linear_init_f32.c
+ * Description:  SVM Linear Instance Initialization
+ *
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <limits.h>
+#include <math.h>
+
+/**
+ * @defgroup groupSVM SVM Functions
+ *
+ * Computes SVM predictions. 
+ *
+ * The SVM predictors in CMSIS-DSP are only working with 2 classes.
+ * Multi-class support must be built from the building blocks provided by CMSIS-DSP.
+ *
+ */
+
+
+/**
+ * @addtogroup groupSVM
+ * @{
+ */
+
+
+/**
+ * @brief        SVM linear instance init function
+ * @param[in]    nbOfSupportVectors     Number of support vectors
+ * @param[in]    vectorDimension        Dimension of vector space
+ * @param[in]    intercept              Intercept
+ * @param[in]    dualCoefficients       Array of dual coefficients
+ * @param[in]    supportVectors         Array of support vectors
+ * @param[in]    classes                Array of 2 classes ID
+ * @return none.
+ *
+ */
+
+
+void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, 
+  uint32_t nbOfSupportVectors,
+  uint32_t vectorDimension,
+  float32_t intercept,
+  const float32_t *dualCoefficients,
+  const float32_t *supportVectors,
+  const int32_t *classes)
+{
+   S->nbOfSupportVectors = nbOfSupportVectors;
+   S->vectorDimension = vectorDimension;
+   S->intercept = intercept;
+   S->dualCoefficients = dualCoefficients;
+   S->supportVectors = supportVectors;
+   S->classes = classes;
+}
+
+
+
+/**
+ * @} end of groupSVM group
+ */

Source/SVMFunctions/arm_svm_linear_predict_f32.c

@@ -0,0 +1,221 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_svm_linear_predict_f32.c
+ * Description:  SVM Linear Classifier
+ *
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <limits.h>
+#include <math.h>
+
+
+/**
+ * @addtogroup groupSVM
+ * @{
+ */
+
+
+/**
+ * @brief SVM linear prediction
+ * @param[in]    *S          points to an instance of the linear SVM structure.
+ * @param[in]    vec_in      pointer to input vector
+ * @param[out]   *pResult    decision value
+ * @return none.
+ *
+ */
+
+#if defined(ARM_MATH_NEON)
+void arm_svm_linear_predict_f32(
+    const arm_svm_linear_instance_f32 *S,
+    const float32_t * in,
+    int * pResult)
+{
+    float32_t sum = S->intercept;
+   
+    float32_t dot;
+    float32x4_t dotV; 
+
+    float32x4_t accuma,accumb,accumc,accumd,accum;
+    float32x2_t accum2;
+    float32x4_t vec1;
+
+    float32x4_t vec2,vec2a,vec2b,vec2c,vec2d;
+
+    uint32_t blkCnt;   
+    uint32_t vectorBlkCnt;   
+
+    const float32_t *pIn = in;
+
+    const float32_t *pSupport = S->supportVectors;
+
+    const float32_t *pSupporta = S->supportVectors;
+    const float32_t *pSupportb;
+    const float32_t *pSupportc;
+    const float32_t *pSupportd;
+
+    pSupportb = pSupporta + S->vectorDimension;
+    pSupportc = pSupportb + S->vectorDimension;
+    pSupportd = pSupportc + S->vectorDimension;
+
+    const float32_t *pDualCoefs = S->dualCoefficients;
+
+    vectorBlkCnt = S->nbOfSupportVectors >> 2;
+
+    while (vectorBlkCnt > 0U)
+    {
+        accuma = vdupq_n_f32(0);
+        accumb = vdupq_n_f32(0);
+        accumc = vdupq_n_f32(0);
+        accumd = vdupq_n_f32(0);
+
+        pIn = in;
+
+        blkCnt = S->vectorDimension >> 2;
+        while (blkCnt > 0U)
+        {
+        
+            vec1 = vld1q_f32(pIn);
+            vec2a = vld1q_f32(pSupporta);
+            vec2b = vld1q_f32(pSupportb);
+            vec2c = vld1q_f32(pSupportc);
+            vec2d = vld1q_f32(pSupportd);
+
+            pIn += 4;
+            pSupporta += 4;
+            pSupportb += 4;
+            pSupportc += 4;
+            pSupportd += 4;
+
+            accuma = vmlaq_f32(accuma, vec1,vec2a);
+            accumb = vmlaq_f32(accumb, vec1,vec2b);
+            accumc = vmlaq_f32(accumc, vec1,vec2c);
+            accumd = vmlaq_f32(accumd, vec1,vec2d);
+
+            blkCnt -- ;
+        }
+        accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma));
+        dotV[0] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb));
+        dotV[1] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc));
+        dotV[2] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd));
+        dotV[3] = accum2[0] + accum2[1];
+
+
+        blkCnt = S->vectorDimension & 3;
+        while (blkCnt > 0U)
+        {
+            dotV[0] = dotV[0] + *pIn * *pSupporta++;
+            dotV[1] = dotV[1] + *pIn * *pSupportb++;
+            dotV[2] = dotV[2] + *pIn * *pSupportc++;
+            dotV[3] = dotV[3] + *pIn * *pSupportd++;
+
+            pIn++;
+
+            blkCnt -- ;
+        }
+
+        vec1 = vld1q_f32(pDualCoefs);
+        pDualCoefs += 4; 
+
+        accum = vmulq_f32(vec1,dotV);
+        accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum));
+        sum += accum2[0] + accum2[1];
+
+        pSupporta += 3*S->vectorDimension;
+        pSupportb += 3*S->vectorDimension;
+        pSupportc += 3*S->vectorDimension;
+        pSupportd += 3*S->vectorDimension;
+
+        vectorBlkCnt -- ;
+    }
+
+    pSupport = pSupporta;
+    vectorBlkCnt = S->nbOfSupportVectors & 3;
+    while (vectorBlkCnt > 0U)
+    {
+        accum = vdupq_n_f32(0);
+        dot = 0.0;
+        pIn = in;
+
+        blkCnt = S->vectorDimension >> 2;
+        while (blkCnt > 0U)
+        {
+        
+            vec1 = vld1q_f32(pIn);
+            vec2 = vld1q_f32(pSupport);
+            pIn += 4;
+            pSupport += 4;
+
+            accum = vmlaq_f32(accum, vec1,vec2);
+
+            blkCnt -- ;
+        }
+        accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum));
+        dot = accum2[0] + accum2[1];
+
+
+        blkCnt = S->vectorDimension & 3;
+        while (blkCnt > 0U)
+        {
+            dot = dot + *pIn++ * *pSupport++;
+
+            blkCnt -- ;
+        }
+
+        sum += *pDualCoefs++ * dot;
+        vectorBlkCnt -- ;
+    }
+
+    *pResult=S->classes[STEP(sum)];
+}
+#else
+void arm_svm_linear_predict_f32(
+    const arm_svm_linear_instance_f32 *S,
+    const float32_t * in,
+    int * pResult)
+{
+    float32_t sum=S->intercept;
+    float32_t dot=0;
+    const float32_t *pSupport = S->supportVectors;
+
+    for(int i=0; i < S->nbOfSupportVectors; i++)
+    {
+        dot=0;
+        for(int j=0; j < S->vectorDimension; j++)
+        {
+            dot = dot + in[j]* *pSupport++;
+        }
+        sum += S->dualCoefficients[i] * dot;
+    }
+    *pResult=S->classes[STEP(sum)];
+}
+#endif
+
+/**
+ * @} end of groupSVM group
+ */

Source/SVMFunctions/arm_svm_polynomial_init_f32.c

@@ -0,0 +1,82 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_svm_polynomial_init_f32.c
+ * Description:  SVM Polynomial Instance Initialization
+ *
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <limits.h>
+#include <math.h>
+
+
+/**
+ * @addtogroup groupSVM
+ * @{
+ */
+
+
+
+/**
+ * @brief        SVM polynomial instance init function
+ * @param[in]    nbOfSupportVectors     Number of support vectors
+ * @param[in]    vectorDimension        Dimension of vector space
+ * @param[in]    intercept              Intercept
+ * @param[in]    dualCoefficients       Array of dual coefficients
+ * @param[in]    supportVectors         Array of support vectors
+ * @param[in]    classes                Array of 2 classes ID
+ * @param[in]    degree                 Polynomial degree
+ * @param[in]    coef0                  coeff0 (scikit-learn terminology)
+ * @param[in]    gamma                  gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+
+void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, 
+  uint32_t nbOfSupportVectors,
+  uint32_t vectorDimension,
+  float32_t intercept,
+  const float32_t *dualCoefficients,
+  const float32_t *supportVectors,
+  const int32_t *classes,
+  int      degree,
+  float32_t coef0,
+  float32_t gamma
+  )
+{
+   S->nbOfSupportVectors = nbOfSupportVectors;
+   S->vectorDimension = vectorDimension;
+   S->intercept = intercept;
+   S->dualCoefficients = dualCoefficients;
+   S->supportVectors = supportVectors;
+   S->classes = classes;
+   S->degree = degree;
+   S->coef0 = coef0;
+   S->gamma = gamma;
+}
+
+
+
+/**
+ * @} end of groupSVM group
+ */

Source/SVMFunctions/arm_svm_polynomial_predict_f32.c

@@ -0,0 +1,230 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_svm_polynomial_predict_f32.c
+ * Description:  SVM Polynomial Classifier
+ *
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <limits.h>
+#include <math.h>
+
+
+
+/**
+ * @addtogroup groupSVM
+ * @{
+ */
+
+
+/**
+ * @brief SVM polynomial prediction
+ * @param[in]    *S          points to an instance of the polynomial SVM structure.
+ * @param[in]    vec_in      pointer to input vector
+ * @param[out]   *pResult    decision value
+ * @return none.
+ *
+ */
+#if defined(ARM_MATH_NEON)
+void arm_svm_polynomial_predict_f32(
+    const arm_svm_polynomial_instance_f32 *S,
+    const float32_t * in,
+    int * pResult)
+{
+    float32_t sum = S->intercept;
+   
+    float32_t dot;
+    float32x4_t dotV; 
+
+    float32x4_t accuma,accumb,accumc,accumd,accum;
+    float32x2_t accum2;
+    float32x4_t vec1;
+    float32x4_t coef0 = vdupq_n_f32(S->coef0);
+
+    float32x4_t vec2,vec2a,vec2b,vec2c,vec2d;
+
+    uint32_t blkCnt;   
+    uint32_t vectorBlkCnt;   
+
+    const float32_t *pIn = in;
+
+    const float32_t *pSupport = S->supportVectors;
+
+    const float32_t *pSupporta = S->supportVectors;
+    const float32_t *pSupportb;
+    const float32_t *pSupportc;
+    const float32_t *pSupportd;
+
+    pSupportb = pSupporta + S->vectorDimension;
+    pSupportc = pSupportb + S->vectorDimension;
+    pSupportd = pSupportc + S->vectorDimension;
+
+    const float32_t *pDualCoefs = S->dualCoefficients;
+
+    vectorBlkCnt = S->nbOfSupportVectors >> 2;
+    while (vectorBlkCnt > 0U)
+    {
+        accuma = vdupq_n_f32(0);
+        accumb = vdupq_n_f32(0);
+        accumc = vdupq_n_f32(0);
+        accumd = vdupq_n_f32(0);
+
+        pIn = in;
+
+        blkCnt = S->vectorDimension >> 2;
+        while (blkCnt > 0U)
+        {
+        
+            vec1 = vld1q_f32(pIn);
+            vec2a = vld1q_f32(pSupporta);
+            vec2b = vld1q_f32(pSupportb);
+            vec2c = vld1q_f32(pSupportc);
+            vec2d = vld1q_f32(pSupportd);
+
+            pIn += 4;
+            pSupporta += 4;
+            pSupportb += 4;
+            pSupportc += 4;
+            pSupportd += 4;
+
+            accuma = vmlaq_f32(accuma, vec1,vec2a);
+            accumb = vmlaq_f32(accumb, vec1,vec2b);
+            accumc = vmlaq_f32(accumc, vec1,vec2c);
+            accumd = vmlaq_f32(accumd, vec1,vec2d);
+
+            blkCnt -- ;
+        }
+        accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma));
+        dotV[0] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb));
+        dotV[1] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc));
+        dotV[2] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd));
+        dotV[3] = accum2[0] + accum2[1];
+
+
+        blkCnt = S->vectorDimension & 3;
+        while (blkCnt > 0U)
+        {
+            dotV[0] = dotV[0] + *pIn * *pSupporta++;
+            dotV[1] = dotV[1] + *pIn * *pSupportb++;
+            dotV[2] = dotV[2] + *pIn * *pSupportc++;
+            dotV[3] = dotV[3] + *pIn * *pSupportd++;
+
+            pIn++;
+
+            blkCnt -- ;
+        }
+
+        vec1 = vld1q_f32(pDualCoefs);
+        pDualCoefs += 4; 
+
+        // To vectorize later
+        dotV = vmulq_n_f32(dotV, S->gamma);
+        dotV = vaddq_f32(dotV, coef0);
+
+        dotV = arm_vec_exponent_f32(dotV,S->degree);
+
+        accum = vmulq_f32(vec1,dotV);
+        accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum));
+        sum += accum2[0] + accum2[1];
+
+        pSupporta += 3*S->vectorDimension;
+        pSupportb += 3*S->vectorDimension;
+        pSupportc += 3*S->vectorDimension;
+        pSupportd += 3*S->vectorDimension;
+
+        vectorBlkCnt -- ;
+    }
+
+    pSupport = pSupporta;
+    vectorBlkCnt = S->nbOfSupportVectors & 3;
+
+    while (vectorBlkCnt > 0U)
+    {
+        accum = vdupq_n_f32(0);
+        dot = 0.0;
+        pIn = in;
+
+        blkCnt = S->vectorDimension >> 2;
+        while (blkCnt > 0U)
+        {
+        
+            vec1 = vld1q_f32(pIn);
+            vec2 = vld1q_f32(pSupport);
+            pIn += 4;
+            pSupport += 4;
+
+            accum = vmlaq_f32(accum, vec1,vec2);
+
+            blkCnt -- ;
+        }
+        accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum));
+        dot = accum2[0] + accum2[1];
+
+
+        blkCnt = S->vectorDimension & 3;
+        while (blkCnt > 0U)
+        {
+            dot = dot + *pIn++ * *pSupport++;
+
+            blkCnt -- ;
+        }
+
+        sum += *pDualCoefs++ * arm_exponent_f32(S->gamma * dot + S->coef0, S->degree);
+        vectorBlkCnt -- ;
+    }
+
+    *pResult=S->classes[STEP(sum)];
+}
+#else
+void arm_svm_polynomial_predict_f32(
+    const arm_svm_polynomial_instance_f32 *S,
+    const float32_t * in,
+    int * pResult)
+{
+    float32_t sum=S->intercept;
+    float32_t dot=0;
+    const float32_t *pSupport = S->supportVectors;
+
+    for(int i=0; i < S->nbOfSupportVectors; i++)
+    {
+        dot=0;
+        for(int j=0; j < S->vectorDimension; j++)
+        {
+            dot = dot + in[j]* *pSupport++;
+        }
+        sum += S->dualCoefficients[i] * arm_exponent_f32(S->gamma * dot + S->coef0, S->degree);
+    }
+
+    *pResult=S->classes[STEP(sum)];
+}
+#endif
+
+
+/**
+ * @} end of groupSVM group
+ */

Source/SVMFunctions/arm_svm_rbf_init_f32.c

@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_svm_rbf_init_f32.c
+ * Description:  SVM Radial Basis Function Instance Initialization
+ *
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <limits.h>
+#include <math.h>
+
+
+/**
+ * @addtogroup groupSVM
+ * @{
+ */
+
+
+/**
+ * @brief        SVM radial basis function instance init function
+ * @param[in]    nbOfSupportVectors     Number of support vectors
+ * @param[in]    vectorDimension        Dimension of vector space
+ * @param[in]    intercept              Intercept
+ * @param[in]    dualCoefficients       Array of dual coefficients
+ * @param[in]    supportVectors         Array of support vectors
+ * @param[in]    classes                Array of 2 classes ID
+ * @param[in]    gamma                  gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, 
+  uint32_t nbOfSupportVectors,
+  uint32_t vectorDimension,
+  float32_t intercept,
+  const float32_t *dualCoefficients,
+  const float32_t *supportVectors,
+  const int32_t *classes,
+  float32_t gamma
+  )
+{
+   S->nbOfSupportVectors = nbOfSupportVectors;
+   S->vectorDimension = vectorDimension;
+   S->intercept = intercept;
+   S->dualCoefficients = dualCoefficients;
+   S->supportVectors = supportVectors;
+   S->classes = classes;
+   S->gamma = gamma;
+}
+
+
+
+/**
+ * @} end of groupSVM group
+ */

Source/SVMFunctions/arm_svm_rbf_predict_f32.c

@@ -0,0 +1,246 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_svm_rbf_predict_f32.c
+ * Description:  SVM Radial Basis Function Classifier
+ *
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <limits.h>
+#include <math.h>
+
+
+/**
+ * @addtogroup groupSVM
+ * @{
+ */
+
+
+/**
+ * @brief SVM rbf prediction
+ * @param[in]    *S          points to an instance of the rbf SVM structure.
+ * @param[in]    vec_in      pointer to input vector
+ * @param[out]   *pResult    decision value
+ * @return none.
+ *
+ */
+#if defined(ARM_MATH_NEON)
+
+#include "NEMath.h"
+
+void arm_svm_rbf_predict_f32(
+    const arm_svm_rbf_instance_f32 *S,
+    const float32_t * in,
+    int * pResult)
+{
+    float32_t sum = S->intercept;
+   
+    float32_t dot;
+    float32x4_t dotV; 
+
+    float32x4_t accuma,accumb,accumc,accumd,accum;
+    float32x2_t accum2;
+    float32x4_t temp;
+    float32x4_t vec1;
+
+    float32x4_t vec2,vec2a,vec2b,vec2c,vec2d;
+
+    uint32_t blkCnt;   
+    uint32_t vectorBlkCnt;   
+
+    const float32_t *pIn = in;
+
+    const float32_t *pSupport = S->supportVectors;
+
+    const float32_t *pSupporta = S->supportVectors;
+    const float32_t *pSupportb;
+    const float32_t *pSupportc;
+    const float32_t *pSupportd;
+
+    pSupportb = pSupporta + S->vectorDimension;
+    pSupportc = pSupportb + S->vectorDimension;
+    pSupportd = pSupportc + S->vectorDimension;
+
+    const float32_t *pDualCoefs = S->dualCoefficients;
+
+
+    vectorBlkCnt = S->nbOfSupportVectors >> 2;
+    while (vectorBlkCnt > 0U)
+    {
+        accuma = vdupq_n_f32(0);
+        accumb = vdupq_n_f32(0);
+        accumc = vdupq_n_f32(0);
+        accumd = vdupq_n_f32(0);
+
+        pIn = in;
+
+        blkCnt = S->vectorDimension >> 2;
+        while (blkCnt > 0U)
+        {
+        
+            vec1 = vld1q_f32(pIn);
+            vec2a = vld1q_f32(pSupporta);
+            vec2b = vld1q_f32(pSupportb);
+            vec2c = vld1q_f32(pSupportc);
+            vec2d = vld1q_f32(pSupportd);
+
+            pIn += 4;
+            pSupporta += 4;
+            pSupportb += 4;
+            pSupportc += 4;
+            pSupportd += 4;
+
+            temp = vsubq_f32(vec1, vec2a);
+            accuma = vmlaq_f32(accuma, temp, temp);
+
+            temp = vsubq_f32(vec1, vec2b);
+            accumb = vmlaq_f32(accumb, temp, temp);
+
+            temp = vsubq_f32(vec1, vec2c);
+            accumc = vmlaq_f32(accumc, temp, temp);
+
+            temp = vsubq_f32(vec1, vec2d);
+            accumd = vmlaq_f32(accumd, temp, temp);
+
+            blkCnt -- ;
+        }
+        accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma));
+        dotV[0] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb));
+        dotV[1] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc));
+        dotV[2] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd));
+        dotV[3] = accum2[0] + accum2[1];
+
+
+        blkCnt = S->vectorDimension & 3;
+        while (blkCnt > 0U)
+        {
+            dotV[0] = dotV[0] + SQ(*pIn - *pSupporta);
+            dotV[1] = dotV[1] + SQ(*pIn - *pSupportb);
+            dotV[2] = dotV[2] + SQ(*pIn - *pSupportc);
+            dotV[3] = dotV[3] + SQ(*pIn - *pSupportd);
+            pSupporta++;
+            pSupportb++;
+            pSupportc++;
+            pSupportd++;
+
+            pIn++;
+
+            blkCnt -- ;
+        }
+
+        vec1 = vld1q_f32(pDualCoefs);
+        pDualCoefs += 4; 
+
+        // To vectorize later
+        dotV = vmulq_n_f32(dotV, -S->gamma);
+        dotV = vexpq_f32(dotV);
+
+        accum = vmulq_f32(vec1,dotV);
+        accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum));
+        sum += accum2[0] + accum2[1];
+
+        pSupporta += 3*S->vectorDimension;
+        pSupportb += 3*S->vectorDimension;
+        pSupportc += 3*S->vectorDimension;
+        pSupportd += 3*S->vectorDimension;
+
+        vectorBlkCnt -- ;
+    }
+
+    pSupport = pSupporta;
+    vectorBlkCnt = S->nbOfSupportVectors & 3;
+
+    while (vectorBlkCnt > 0U)
+    {
+        accum = vdupq_n_f32(0);
+        dot = 0.0;
+        pIn = in;
+
+        blkCnt = S->vectorDimension >> 2;
+        while (blkCnt > 0U)
+        {
+        
+            vec1 = vld1q_f32(pIn);
+            vec2 = vld1q_f32(pSupport);
+            pIn += 4;
+            pSupport += 4;
+
+            temp = vsubq_f32(vec1,vec2);
+            accum = vmlaq_f32(accum, temp,temp);
+
+            blkCnt -- ;
+        }
+        accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum));
+        dot = accum2[0] + accum2[1];
+
+
+        blkCnt = S->vectorDimension & 3;
+        while (blkCnt > 0U)
+        {
+
+            dot = dot + SQ(*pIn - *pSupport);
+            pIn++;
+            pSupport++;
+
+            blkCnt -- ;
+        }
+
+        sum += *pDualCoefs++ * exp(-S->gamma * dot);
+        vectorBlkCnt -- ;
+    }
+
+    *pResult=S->classes[STEP(sum)];
+}
+#else
+void arm_svm_rbf_predict_f32(
+    const arm_svm_rbf_instance_f32 *S,
+    const float32_t * in,
+    int * pResult)
+{
+    float32_t sum=S->intercept;
+    float32_t dot=0;
+    const float32_t *pSupport = S->supportVectors;
+
+    for(int i=0; i < S->nbOfSupportVectors; i++)
+    {
+        dot=0;
+        for(int j=0; j < S->vectorDimension; j++)
+        {
+            dot = dot + SQ(in[j] - *pSupport);
+            pSupport++;
+        }
+        sum += S->dualCoefficients[i] * exp(-S->gamma * dot);
+    }
+    *pResult=S->classes[STEP(sum)];
+}
+#endif
+
+
+/**
+ * @} end of groupSVM group
+ */

Source/SVMFunctions/arm_svm_sigmoid_init_f32.c

@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_svm_sigmoid_predict_f32.c
+ * Description:  SVM Sigmoid Instance Initialization
+ *
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <limits.h>
+#include <math.h>
+
+
+/**
+ * @addtogroup groupSVM
+ * @{
+ */
+
+
+/**
+ * @brief        SVM sigmoid instance init function
+ * @param[in]    nbOfSupportVectors     Number of support vectors
+ * @param[in]    vectorDimension        Dimension of vector space
+ * @param[in]    intercept              Intercept
+ * @param[in]    dualCoefficients       Array of dual coefficients
+ * @param[in]    supportVectors         Array of support vectors
+ * @param[in]    classes                Array of 2 classes ID
+ * @param[in]    coef0                  coeff0 (scikit-learn terminology)
+ * @param[in]    gamma                  gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, 
+  uint32_t nbOfSupportVectors,
+  uint32_t vectorDimension,
+  float32_t intercept,
+  const float32_t *dualCoefficients,
+  const float32_t *supportVectors,
+  const int32_t *classes,
+  float32_t coef0,
+  float32_t gamma
+  )
+{
+   S->nbOfSupportVectors = nbOfSupportVectors;
+   S->vectorDimension = vectorDimension;
+   S->intercept = intercept;
+   S->dualCoefficients = dualCoefficients;
+   S->supportVectors = supportVectors;
+   S->classes = classes;
+   S->coef0 = coef0;
+   S->gamma = gamma;
+}
+
+
+/**
+ * @} end of groupSVM group
+ */

Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c

@@ -0,0 +1,229 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_svm_sigmoid_predict_f32.c
+ * Description:  SVM Sigmoid Classifier
+ *
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include <limits.h>
+#include <math.h>
+
+/**
+ * @addtogroup groupSVM
+ * @{
+ */
+
+
+
+/**
+ * @brief SVM sigmoid prediction
+ * @param[in]    *S          points to an instance of the rbf SVM structure.
+ * @param[in]    vec_in      pointer to input vector
+ * @param[out]   *pResult    decision value
+ * @return none.
+ *
+ */
+#if defined(ARM_MATH_NEON)
+#include "NEMath.h"
+
+void arm_svm_sigmoid_predict_f32(
+    const arm_svm_sigmoid_instance_f32 *S,
+    const float32_t * in,
+    int * pResult)
+{
+    float32_t sum = S->intercept;
+   
+    float32_t dot;
+    float32x4_t dotV; 
+
+    float32x4_t accuma,accumb,accumc,accumd,accum;
+    float32x2_t accum2;
+    float32x4_t vec1;
+    float32x4_t coef0 = vdupq_n_f32(S->coef0);
+
+    float32x4_t vec2,vec2a,vec2b,vec2c,vec2d;
+
+    uint32_t blkCnt;   
+    uint32_t vectorBlkCnt;   
+
+    const float32_t *pIn = in;
+
+    const float32_t *pSupport = S->supportVectors;
+
+    const float32_t *pSupporta = S->supportVectors;
+    const float32_t *pSupportb;
+    const float32_t *pSupportc;
+    const float32_t *pSupportd;
+
+    pSupportb = pSupporta + S->vectorDimension;
+    pSupportc = pSupportb + S->vectorDimension;
+    pSupportd = pSupportc + S->vectorDimension;
+
+    const float32_t *pDualCoefs = S->dualCoefficients;
+
+    vectorBlkCnt = S->nbOfSupportVectors >> 2;
+    while (vectorBlkCnt > 0U)
+    {
+        accuma = vdupq_n_f32(0);
+        accumb = vdupq_n_f32(0);
+        accumc = vdupq_n_f32(0);
+        accumd = vdupq_n_f32(0);
+
+        pIn = in;
+
+        blkCnt = S->vectorDimension >> 2;
+        while (blkCnt > 0U)
+        {
+        
+            vec1 = vld1q_f32(pIn);
+            vec2a = vld1q_f32(pSupporta);
+            vec2b = vld1q_f32(pSupportb);
+            vec2c = vld1q_f32(pSupportc);
+            vec2d = vld1q_f32(pSupportd);
+
+            pIn += 4;
+            pSupporta += 4;
+            pSupportb += 4;
+            pSupportc += 4;
+            pSupportd += 4;
+
+            accuma = vmlaq_f32(accuma, vec1,vec2a);
+            accumb = vmlaq_f32(accumb, vec1,vec2b);
+            accumc = vmlaq_f32(accumc, vec1,vec2c);
+            accumd = vmlaq_f32(accumd, vec1,vec2d);
+
+            blkCnt -- ;
+        }
+        accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma));
+        dotV[0] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb));
+        dotV[1] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc));
+        dotV[2] = accum2[0] + accum2[1];
+
+        accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd));
+        dotV[3] = accum2[0] + accum2[1];
+
+
+        blkCnt = S->vectorDimension & 3;
+        while (blkCnt > 0U)
+        {
+            dotV[0] = dotV[0] + *pIn * *pSupporta++;
+            dotV[1] = dotV[1] + *pIn * *pSupportb++;
+            dotV[2] = dotV[2] + *pIn * *pSupportc++;
+            dotV[3] = dotV[3] + *pIn * *pSupportd++;
+
+            pIn++;
+
+            blkCnt -- ;
+        }
+
+        vec1 = vld1q_f32(pDualCoefs);
+        pDualCoefs += 4; 
+
+        // To vectorize later
+        dotV = vmulq_n_f32(dotV, S->gamma);
+        dotV = vaddq_f32(dotV, coef0);
+
+        dotV = vtanhq_f32(dotV);
+
+        accum = vmulq_f32(vec1,dotV);
+        accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum));
+        sum += accum2[0] + accum2[1];
+
+        pSupporta += 3*S->vectorDimension;
+        pSupportb += 3*S->vectorDimension;
+        pSupportc += 3*S->vectorDimension;
+        pSupportd += 3*S->vectorDimension;
+
+        vectorBlkCnt -- ;
+    }
+
+    pSupport = pSupporta;
+    vectorBlkCnt = S->nbOfSupportVectors & 3;
+
+    while (vectorBlkCnt > 0U)
+    {
+        accum = vdupq_n_f32(0);
+        dot = 0.0;
+        pIn = in;
+
+        blkCnt = S->vectorDimension >> 2;
+        while (blkCnt > 0U)
+        {
+        
+            vec1 = vld1q_f32(pIn);
+            vec2 = vld1q_f32(pSupport);
+            pIn += 4;
+            pSupport += 4;
+
+            accum = vmlaq_f32(accum, vec1,vec2);
+
+            blkCnt -- ;
+        }
+        accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum));
+        dot = accum2[0] + accum2[1];
+
+
+        blkCnt = S->vectorDimension & 3;
+        while (blkCnt > 0U)
+        {
+            dot = dot + *pIn++ * *pSupport++;
+
+            blkCnt -- ;
+        }
+
+        sum += *pDualCoefs++ * tanh(S->gamma * dot + S->coef0);
+        vectorBlkCnt -- ;
+    }
+
+    *pResult=S->classes[STEP(sum)];
+}
+#else
+void arm_svm_sigmoid_predict_f32(
+    const arm_svm_sigmoid_instance_f32 *S,
+    const float32_t * in,
+    int * pResult)
+{
+    float32_t sum=S->intercept;
+    float32_t dot=0;
+    const float32_t *pSupport = S->supportVectors;
+
+    for(int i=0; i < S->nbOfSupportVectors; i++)
+    {
+        dot=0;
+        for(int j=0; j < S->vectorDimension; j++)
+        {
+            dot = dot + in[j]* *pSupport++;
+        }
+        sum += S->dualCoefficients[i] * tanh(S->gamma * dot + S->coef0);
+    }
+    *pResult=S->classes[STEP(sum)];
+}
+
+#endif
+/**
+ * @} end of groupSVM group
+ */

Source/configDsp.cmake

@@ -18,4 +18,8 @@ if (MATRIXCHECK)
   target_compile_definitions(${project} PRIVATE ARM_MATH_MATRIX_CHECK)
 endif()
 
+if (NEON OR NEONEXPERIMENTAL)
+    target_include_directories(${project} PRIVATE "${root}/CMSIS/DSP/ComputeLibrary/Include")
+endif()
+
 endfunction()

Testing/.gitignore

@@ -2,6 +2,7 @@ bench/
 build/
 build_m7/
 build_a5/
+build_m0/
 build_sdsim_a5/
 build_sdsim_a15/
 build_m33/

Testing/CMakeLists.txt

@@ -81,6 +81,9 @@ set(TESTSRC testmain.cpp
   Source/BasicTestsF32.cpp
   Source/BasicMathsBenchmarksF32.cpp
   Source/BasicMathsBenchmarksQ31.cpp
+  Source/BasicMathsBenchmarksQ15.cpp
+  Source/BasicMathsBenchmarksQ7.cpp
+  Source/SVMF32.cpp
   Source/FullyConnected.cpp
   Source/FullyConnectedBench.cpp
   GeneratedSource/TestDesc.cpp

Testing/FrameworkSource/Timing.cpp

@@ -2,7 +2,7 @@
 
 #ifdef CORTEXM
 
-#define JTEST_SYSTICK_INITIAL_VALUE       0xFFFFFF
+#define SYSTICK_INITIAL_VALUE       0xFFFFFF
 static uint32_t startCycles=0;
 
 #if   defined ARMCM0
@@ -64,8 +64,7 @@ void initCycleMeasurement()
 {
 #ifdef CORTEXM
     SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
-    SysTick->LOAD = JTEST_SYSTICK_INITIAL_VALUE;
-    SysTick->VAL  = JTEST_SYSTICK_INITIAL_VALUE; 
+    SysTick->LOAD = SYSTICK_INITIAL_VALUE;
 #endif 
 
 #ifdef CORTEXA
@@ -101,18 +100,10 @@ void cycleMeasurementStart()
 {
 #ifdef CORTEXM
     SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
-    SysTick->LOAD = JTEST_SYSTICK_INITIAL_VALUE;
-    SysTick->VAL  = JTEST_SYSTICK_INITIAL_VALUE; 
+    SysTick->LOAD = SYSTICK_INITIAL_VALUE;
 
     SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;  
 
-    // In fast model at least, when we start the SysTick, VAL is temporarily
-    // switching to zero. If the benchmark is too quick
-    // VAL has no time to switch to JTEST_SYSTICK_INITIAL_VALUE
-    // and benchmarking value returned is JTEST_SYSTICK_INITIAL_VALUE
-    // instead of 0
-    while(SysTick->VAL == 0);
-
     startCycles = SysTick->VAL;
     
 #endif
@@ -129,8 +120,7 @@ void cycleMeasurementStop()
 {
 #ifdef CORTEXM
     SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
-    SysTick->LOAD = JTEST_SYSTICK_INITIAL_VALUE;
-    SysTick->VAL  = JTEST_SYSTICK_INITIAL_VALUE; 
+    SysTick->LOAD = SYSTICK_INITIAL_VALUE;
 #endif
 }
 

Testing/FullBenchmark/DSP/BasicMaths/BasicMathsF32/fullBenchmark.csv

@@ -1,41 +1,41 @@
-CATEGORY,NAME,ID,NB,CYCLES,OPTIMIZED,HARDFP,FASTMATH,NEON,UNROLL,ROUNDING,PLATFORM,CORE,COMPILER,VERSION
-"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,16,297,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,32,369,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,64,513,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,128,801,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,256,1377,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,16,297,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,32,369,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,64,513,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,128,801,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,256,1377,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,16,297,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,32,369,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,64,513,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,128,801,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,256,1377,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,16,277,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,32,331,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,64,439,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,128,655,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,256,1087,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,16,222,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,32,276,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,64,384,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,128,600,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,256,1032,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,16,278,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,32,332,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,64,440,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,128,656,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,256,1088,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,16,278,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,32,332,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,64,440,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,128,656,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,256,1088,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,16,243,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,32,311,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,64,447,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,128,719,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,256,1263,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
+CATEGORY,NAME,ID,OLDID,NB,CYCLES,OPTIMIZED,HARDFP,FASTMATH,NEON,UNROLL,ROUNDING,PLATFORM,CORE,COMPILER,VERSION
+"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,"0",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,"0",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,"0",64,2528,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,"0",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,"0",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,"5",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,"5",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,"5",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,"5",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_add_f32",2,"5",256,2518,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,"10",16,2510,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,"10",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,"10",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,"10",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",3,"10",256,2554,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,"15",16,2457,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,"15",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,"15",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,"15",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",4,"15",256,2499,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,"20",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,"20",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,"20",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,"20",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",5,"20",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,"25",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,"25",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,"25",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,"25",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",6,"25",256,2518,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,"30",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,"30",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,"30",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,"30",128,2518,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",7,"30",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,"38",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,"38",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,"38",64,2510,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,"38",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",8,"38",256,2538,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001

Testing/FullBenchmark/DSP/BasicMaths/BasicMathsF32/regression.csv

@@ -1,9 +1,9 @@
-"ID","CATEGORY","NAME","OPTIMIZED","HARDFP","FASTMATH","NEON","UNROLL","ROUNDING","PLATFORM","CORE","COMPILER","VERSION","Regression","MAX"
-1,"DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"224.99999999999997 + NB * 4.499999999999998",1377
-2,"DSP:BasicMaths:BasicMathsF32","vec_add_f32",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"224.99999999999997 + NB * 4.499999999999998",1377
-3,"DSP:BasicMaths:BasicMathsF32","vec_sub_f32",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"224.99999999999997 + NB * 4.499999999999998",1377
-4,"DSP:BasicMaths:BasicMathsF32","vec_abs_f32",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"222.99999999999994 + NB * 3.3749999999999982",1087
-5,"DSP:BasicMaths:BasicMathsF32","vec_negate_f32",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"168.00000000000006 + NB * 3.374999999999999",1032
-6,"DSP:BasicMaths:BasicMathsF32","vec_offset_f32",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"223.99999999999994 + NB * 3.374999999999999",1088
-7,"DSP:BasicMaths:BasicMathsF32","vec_scale_f32",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"223.99999999999994 + NB * 3.374999999999999",1088
-8,"DSP:BasicMaths:BasicMathsF32","vec_dot_f32",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"175.0 + NB * 4.249999999999999",1263
+"ID","OLDID","CATEGORY","NAME","OPTIMIZED","HARDFP","FASTMATH","NEON","UNROLL","ROUNDING","PLATFORM","CORE","COMPILER","VERSION","Regression","MAX"
+1,"0","DSP:BasicMaths:BasicMathsF32","vec_mult_f32",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"213.0 + NB * 1.4999999999999993",597
+2,"5","DSP:BasicMaths:BasicMathsF32","vec_add_f32",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"213.0 + NB * 1.4999999999999993",597
+3,"10","DSP:BasicMaths:BasicMathsF32","vec_sub_f32",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"213.0 + NB * 1.4999999999999993",597
+4,"15","DSP:BasicMaths:BasicMathsF32","vec_abs_f32",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"212.0 + NB * 1.2499999999999998",532
+5,"20","DSP:BasicMaths:BasicMathsF32","vec_negate_f32",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"177.0 + NB * 0.6249999999999998",337
+6,"25","DSP:BasicMaths:BasicMathsF32","vec_offset_f32",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"237.99999999999994 + NB * 0.6249999999999998",398
+7,"30","DSP:BasicMaths:BasicMathsF32","vec_scale_f32",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"237.99999999999994 + NB * 0.6249999999999998",398
+8,"38","DSP:BasicMaths:BasicMathsF32","vec_dot_f32",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"172.0 + NB * 1.4999999999999996",556

Testing/FullBenchmark/DSP/BasicMaths/BasicMathsQ15/fullBenchmark.csv

@@ -0,0 +1,41 @@
+CATEGORY,NAME,ID,OLDID,NB,CYCLES,OPTIMIZED,HARDFP,FASTMATH,NEON,UNROLL,ROUNDING,PLATFORM,CORE,COMPILER,VERSION
+"DSP:BasicMaths:BasicMathsQ15","vec_mult_q15",1,"3",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_mult_q15",1,"3",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_mult_q15",1,"3",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_mult_q15",1,"3",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_mult_q15",1,"3",256,2518,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_add_q15",2,"8",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_add_q15",2,"8",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_add_q15",2,"8",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_add_q15",2,"8",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_add_q15",2,"8",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_sub_q15",3,"13",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_sub_q15",3,"13",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_sub_q15",3,"13",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_sub_q15",3,"13",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_sub_q15",3,"13",256,2514,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_abs_q15",4,"18",16,2503,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_abs_q15",4,"18",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_abs_q15",4,"18",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_abs_q15",4,"18",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_abs_q15",4,"18",256,2493,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_negate_q15",5,"23",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_negate_q15",5,"23",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_negate_q15",5,"23",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_negate_q15",5,"23",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_negate_q15",5,"23",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_offset_q15",6,"28",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_offset_q15",6,"28",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_offset_q15",6,"28",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_offset_q15",6,"28",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_offset_q15",6,"28",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_scale_q15",7,"33",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_scale_q15",7,"33",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_scale_q15",7,"33",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_scale_q15",7,"33",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_scale_q15",7,"33",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_dot_q15",8,"41",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_dot_q15",8,"41",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_dot_q15",8,"41",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_dot_q15",8,"41",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ15","vec_dot_q15",8,"41",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001

Testing/FullBenchmark/DSP/BasicMaths/BasicMathsQ15/regression.csv

@@ -0,0 +1,9 @@
+"ID","OLDID","CATEGORY","NAME","OPTIMIZED","HARDFP","FASTMATH","NEON","UNROLL","ROUNDING","PLATFORM","CORE","COMPILER","VERSION","Regression","MAX"
+1,"3","DSP:BasicMaths:BasicMathsQ15","vec_mult_q15",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.00000000000017 + NB * 6.249999999999997",1815
+2,"8","DSP:BasicMaths:BasicMathsQ15","vec_add_q15",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.00000000000006 + NB * 3.249999999999999",1047
+3,"13","DSP:BasicMaths:BasicMathsQ15","vec_sub_q15",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.00000000000006 + NB * 3.249999999999999",1047
+4,"18","DSP:BasicMaths:BasicMathsQ15","vec_abs_q15",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.00000000000017 + NB * 6.249999999999997",1815
+5,"23","DSP:BasicMaths:BasicMathsQ15","vec_negate_q15",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"160.00000000000003 + NB * 2.499999999999999",800
+6,"28","DSP:BasicMaths:BasicMathsQ15","vec_offset_q15",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.0 + NB * 2.499999999999999",855
+7,"33","DSP:BasicMaths:BasicMathsQ15","vec_scale_q15",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"221.0000000000001 + NB * 5.499999999999998",1629
+8,"41","DSP:BasicMaths:BasicMathsQ15","vec_dot_q15",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"170.00000000000006 + NB * 2.499999999999999",810

Testing/FullBenchmark/DSP/BasicMaths/BasicMathsQ31/fullBenchmark.csv

@@ -1,41 +1,41 @@
-CATEGORY,NAME,ID,NB,CYCLES,OPTIMIZED,HARDFP,FASTMATH,NEON,UNROLL,ROUNDING,PLATFORM,CORE,COMPILER,VERSION
-"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,16,329,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,32,433,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,64,641,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,128,1057,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,256,1889,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,16,298,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,32,370,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,64,514,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,128,802,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,256,1378,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,16,298,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,32,370,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,64,514,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,128,802,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,256,1378,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,16,309,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,32,395,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,64,567,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,128,911,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,256,1599,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,16,224,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,32,278,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,64,386,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,128,602,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,256,1034,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,16,278,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,32,332,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,64,440,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,128,656,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,256,1088,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,16,375,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,32,515,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,64,795,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,128,1355,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,256,2475,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,16,311,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,32,429,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,64,665,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,128,1137,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,256,2081,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
+CATEGORY,NAME,ID,OLDID,NB,CYCLES,OPTIMIZED,HARDFP,FASTMATH,NEON,UNROLL,ROUNDING,PLATFORM,CORE,COMPILER,VERSION
+"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,"2",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,"2",32,2494,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,"2",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,"2",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,"2",256,2592,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,"7",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,"7",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,"7",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,"7",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",2,"7",256,2537,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,"12",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,"12",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,"12",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,"12",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",3,"12",256,2519,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,"17",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,"17",32,2520,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,"17",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,"17",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",4,"17",256,2505,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,"22",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,"22",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,"22",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,"22",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",5,"22",256,2518,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,"27",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,"27",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,"27",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,"27",128,2483,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",6,"27",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,"32",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,"32",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,"32",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,"32",128,2548,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",7,"32",256,2520,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,"40",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,"40",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,"40",64,2639,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,"40",128,2527,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",8,"40",256,2573,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001

Testing/FullBenchmark/DSP/BasicMaths/BasicMathsQ31/regression.csv

@@ -1,9 +1,9 @@
-"ID","CATEGORY","NAME","OPTIMIZED","HARDFP","FASTMATH","NEON","UNROLL","ROUNDING","PLATFORM","CORE","COMPILER","VERSION","Regression","MAX"
-1,"DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"225.00000000000003 + NB * 6.499999999999997",1889
-2,"DSP:BasicMaths:BasicMathsQ31","vec_add_q31",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"226.0 + NB * 4.499999999999998",1378
-3,"DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"226.0 + NB * 4.499999999999998",1378
-4,"DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"223.00000000000003 + NB * 5.374999999999997",1599
-5,"DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"170.0 + NB * 3.3749999999999982",1034
-6,"DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"223.99999999999994 + NB * 3.374999999999999",1088
-7,"DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"235.00000000000006 + NB * 8.749999999999996",2475
-8,"DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",1,1,1,1,1,0,"YaminFVP","ARMCM33_DSP_FP","AC6",6120001,"193.00000000000009 + NB * 7.374999999999998",2081
+"ID","OLDID","CATEGORY","NAME","OPTIMIZED","HARDFP","FASTMATH","NEON","UNROLL","ROUNDING","PLATFORM","CORE","COMPILER","VERSION","Regression","MAX"
+1,"2","DSP:BasicMaths:BasicMathsQ31","vec_mult_q31",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"214.00000000000023 + NB * 7.2499999999999964",2070
+2,"7","DSP:BasicMaths:BasicMathsQ31","vec_add_q31",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"214.0000000000001 + NB * 5.249999999999998",1558
+3,"12","DSP:BasicMaths:BasicMathsQ31","vec_sub_q31",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"214.0000000000001 + NB * 5.249999999999998",1558
+4,"17","DSP:BasicMaths:BasicMathsQ31","vec_abs_q31",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.41666666666674 + NB * 5.741767473118277",1686
+5,"22","DSP:BasicMaths:BasicMathsQ31","vec_negate_q31",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"160.0000000000001 + NB * 3.9999999999999982",1184
+6,"27","DSP:BasicMaths:BasicMathsQ31","vec_offset_q31",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.0000000000001 + NB * 3.9999999999999987",1239
+7,"32","DSP:BasicMaths:BasicMathsQ31","vec_scale_q31",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"264.00000000000034 + NB * 12.124999999999996",3368
+8,"40","DSP:BasicMaths:BasicMathsQ31","vec_dot_q31",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"192.0 + NB * 1.4999999999999993",576

Testing/FullBenchmark/DSP/BasicMaths/BasicMathsQ7/fullBenchmark.csv

@@ -0,0 +1,41 @@
+CATEGORY,NAME,ID,OLDID,NB,CYCLES,OPTIMIZED,HARDFP,FASTMATH,NEON,UNROLL,ROUNDING,PLATFORM,CORE,COMPILER,VERSION
+"DSP:BasicMaths:BasicMathsQ7","vec_mult_q7",1,"4",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_mult_q7",1,"4",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_mult_q7",1,"4",64,2491,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_mult_q7",1,"4",128,2556,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_mult_q7",1,"4",256,2499,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_add_q7",2,"9",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_add_q7",2,"9",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_add_q7",2,"9",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_add_q7",2,"9",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_add_q7",2,"9",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_sub_q7",3,"14",16,2498,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_sub_q7",3,"14",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_sub_q7",3,"14",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_sub_q7",3,"14",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_sub_q7",3,"14",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_abs_q7",4,"19",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_abs_q7",4,"19",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_abs_q7",4,"19",64,2515,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_abs_q7",4,"19",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_abs_q7",4,"19",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_negate_q7",5,"24",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_negate_q7",5,"24",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_negate_q7",5,"24",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_negate_q7",5,"24",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_negate_q7",5,"24",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_offset_q7",6,"29",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_offset_q7",6,"29",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_offset_q7",6,"29",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_offset_q7",6,"29",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_offset_q7",6,"29",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_scale_q7",7,"34",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_scale_q7",7,"34",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_scale_q7",7,"34",64,2508,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_scale_q7",7,"34",128,2534,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_scale_q7",7,"34",256,2522,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_dot_q7",8,"42",16,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_dot_q7",8,"42",32,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_dot_q7",8,"42",64,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_dot_q7",8,"42",128,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"DSP:BasicMaths:BasicMathsQ7","vec_dot_q7",8,"42",256,0,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001

Testing/FullBenchmark/DSP/BasicMaths/BasicMathsQ7/regression.csv

@@ -0,0 +1,9 @@
+"ID","OLDID","CATEGORY","NAME","OPTIMIZED","HARDFP","FASTMATH","NEON","UNROLL","ROUNDING","PLATFORM","CORE","COMPILER","VERSION","Regression","MAX"
+1,"4","DSP:BasicMaths:BasicMathsQ7","vec_mult_q7",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.00000000000017 + NB * 7.4999999999999964",2135
+2,"9","DSP:BasicMaths:BasicMathsQ7","vec_add_q7",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"214.0 + NB * 1.4999999999999998",598
+3,"14","DSP:BasicMaths:BasicMathsQ7","vec_sub_q7",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"214.0 + NB * 1.4999999999999998",598
+4,"19","DSP:BasicMaths:BasicMathsQ7","vec_abs_q7",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"215.75000000000017 + NB * 6.250504032258062",1815
+5,"24","DSP:BasicMaths:BasicMathsQ7","vec_negate_q7",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"159.0 + NB * 1.2499999999999996",479
+6,"29","DSP:BasicMaths:BasicMathsQ7","vec_offset_q7",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"220.0 + NB * 1.2499999999999996",540
+7,"34","DSP:BasicMaths:BasicMathsQ7","vec_scale_q7",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"221.00000000000017 + NB * 6.249999999999998",1821
+8,"42","DSP:BasicMaths:BasicMathsQ7","vec_dot_q7",1,1,1,1,1,0,"FVP","ARMCA5","AC6",6120001,"168.00000000000003 + NB * 2.499999999999999",808

Testing/FullBenchmark/NN/FullyConnected/fullBenchmark.csv

@@ -1,5 +1,5 @@
-CATEGORY,ID,REPEAT,CYCLES,OPTIMIZED,HARDFP,FASTMATH,NEON,UNROLL,ROUNDING,PLATFORM,CORE,COMPILER,VERSION
-"NN:FullyConnected",1,10,6235,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"NN:FullyConnected",1,20,12085,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"NN:FullyConnected",1,100,58885,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
-"NN:FullyConnected",1,200,117385,1,1,1,1,1,0,YaminFVP,ARMCM33_DSP_FP,AC6,6120001
+CATEGORY,NAME,ID,OLDID,REPEAT,CYCLES,OPTIMIZED,HARDFP,FASTMATH,NEON,UNROLL,ROUNDING,PLATFORM,CORE,COMPILER,VERSION
+"NN:FullyConnected","test_fully_connected_tflite_s8",1,"",10,5004,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"NN:FullyConnected","test_fully_connected_tflite_s8",1,"",20,12519,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"NN:FullyConnected","test_fully_connected_tflite_s8",1,"",100,67496,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001
+"NN:FullyConnected","test_fully_connected_tflite_s8",1,"",200,130049,1,1,1,0,1,0,FVP,ARMCM7_DP,AC6,6120001

Testing/GeneratedInclude/BasicMathsBenchmarksQ15_decl.h

@@ -0,0 +1,25 @@
+void vec_mult_q15();
+void vec_add_q15();
+void vec_sub_q15();
+void vec_abs_q15();
+void vec_negate_q15();
+void vec_offset_q15();
+void vec_scale_q15();
+void vec_dot_q15();
+
+// Pattern IDs
+static const int INPUT1_Q15_ID=0;
+static const int INPUT2_Q15_ID=1;
+
+// Output IDs
+static const int OUT_SAMPLES_Q15_ID=0;
+
+// Test IDs
+static const int VEC_MULT_Q15_1=1;
+static const int VEC_ADD_Q15_2=2;
+static const int VEC_SUB_Q15_3=3;
+static const int VEC_ABS_Q15_4=4;
+static const int VEC_NEGATE_Q15_5=5;
+static const int VEC_OFFSET_Q15_6=6;
+static const int VEC_SCALE_Q15_7=7;
+static const int VEC_DOT_Q15_8=8;

Testing/GeneratedInclude/BasicMathsBenchmarksQ7_decl.h

@@ -0,0 +1,25 @@
+void vec_mult_q7();
+void vec_add_q7();
+void vec_sub_q7();
+void vec_abs_q7();
+void vec_negate_q7();
+void vec_offset_q7();
+void vec_scale_q7();
+void vec_dot_q7();
+
+// Pattern IDs
+static const int INPUT1_Q7_ID=0;
+static const int INPUT2_Q7_ID=1;
+
+// Output IDs
+static const int OUT_SAMPLES_Q7_ID=0;
+
+// Test IDs
+static const int VEC_MULT_Q7_1=1;
+static const int VEC_ADD_Q7_2=2;
+static const int VEC_SUB_Q7_3=3;
+static const int VEC_ABS_Q7_4=4;
+static const int VEC_NEGATE_Q7_5=5;
+static const int VEC_OFFSET_Q7_6=6;
+static const int VEC_SCALE_Q7_7=7;
+static const int VEC_DOT_Q7_8=8;

Testing/GeneratedInclude/FullyConnectedBench_decl.h

@@ -2,13 +2,13 @@ void test_fully_connected_tflite_s8();
 
 // Pattern IDs
 static const int INPUT1_S8_ID=0;
-static const int BIAS_S8_ID=1;
-static const int WEIGHT_S8_ID=2;
+static const int BIAS1_S8_ID=1;
+static const int WEIGHT1_S8_ID=2;
 static const int REF1_S8_ID=3;
 
 // Output IDs
-static const int OUTPUT1_S8_ID=0;
-static const int TEMP1_S16_ID=1;
+static const int OUTPUT_S8_ID=0;
+static const int TEMP_S16_ID=1;
 
 // Test IDs
 static const int TEST_FULLY_CONNECTED_TFLITE_S8_1=1;

Testing/GeneratedInclude/FullyConnected_decl.h

@@ -5,94 +5,66 @@ static const int INPUT1_S8_ID=0;
 static const int BIAS1_S8_ID=1;
 static const int WEIGHT1_S8_ID=2;
 static const int REF1_S8_ID=3;
-static const int INPUT19_S8_ID=4;
-static const int BIAS19_S8_ID=5;
-static const int WEIGHT19_S8_ID=6;
-static const int REF19_S8_ID=7;
-static const int INPUT2_S8_ID=8;
-static const int BIAS2_S8_ID=9;
-static const int WEIGHT2_S8_ID=10;
-static const int REF2_S8_ID=11;
-static const int INPUT3_S8_ID=12;
-static const int BIAS3_S8_ID=13;
-static const int WEIGHT3_S8_ID=14;
-static const int REF3_S8_ID=15;
-static const int INPUT4_S8_ID=16;
-static const int BIAS4_S8_ID=17;
-static const int WEIGHT4_S8_ID=18;
-static const int REF4_S8_ID=19;
-static const int INPUT5_S8_ID=20;
-static const int BIAS5_S8_ID=21;
-static const int WEIGHT5_S8_ID=22;
-static const int REF5_S8_ID=23;
-static const int INPUT6_S8_ID=24;
-static const int BIAS6_S8_ID=25;
-static const int WEIGHT6_S8_ID=26;
-static const int REF6_S8_ID=27;
-static const int INPUT7_S8_ID=28;
-static const int BIAS7_S8_ID=29;
-static const int WEIGHT7_S8_ID=30;
-static const int REF7_S8_ID=31;
-static const int INPUT8_S8_ID=32;
-static const int BIAS8_S8_ID=33;
-static const int WEIGHT8_S8_ID=34;
-static const int REF8_S8_ID=35;
-static const int INPUT9_S8_ID=36;
-static const int BIAS9_S8_ID=37;
-static const int WEIGHT9_S8_ID=38;
-static const int REF9_S8_ID=39;
-static const int INPUT10_S8_ID=40;
-static const int BIAS10_S8_ID=41;
-static const int WEIGHT10_S8_ID=42;
-static const int REF10_S8_ID=43;
-static const int INPUT11_S8_ID=44;
-static const int BIAS11_S8_ID=45;
-static const int WEIGHT11_S8_ID=46;
-static const int REF11_S8_ID=47;
-static const int INPUT12_S8_ID=48;
-static const int BIAS12_S8_ID=49;
-static const int WEIGHT12_S8_ID=50;
-static const int REF12_S8_ID=51;
-static const int INPUT13_S8_ID=52;
-static const int BIAS13_S8_ID=53;
-static const int WEIGHT13_S8_ID=54;
-static const int REF13_S8_ID=55;
-static const int INPUT14_S8_ID=56;
-static const int BIAS14_S8_ID=57;
-static const int WEIGHT14_S8_ID=58;
-static const int REF14_S8_ID=59;
+static const int INPUT2_S8_ID=4;
+static const int BIAS2_S8_ID=5;
+static const int WEIGHT2_S8_ID=6;
+static const int REF2_S8_ID=7;
+static const int INPUT3_S8_ID=8;
+static const int BIAS3_S8_ID=9;
+static const int WEIGHT3_S8_ID=10;
+static const int REF3_S8_ID=11;
+static const int INPUT4_S8_ID=12;
+static const int BIAS4_S8_ID=13;
+static const int WEIGHT4_S8_ID=14;
+static const int REF4_S8_ID=15;
+static const int INPUT5_S8_ID=16;
+static const int BIAS5_S8_ID=17;
+static const int WEIGHT5_S8_ID=18;
+static const int REF5_S8_ID=19;
+static const int INPUT6_S8_ID=20;
+static const int BIAS6_S8_ID=21;
+static const int WEIGHT6_S8_ID=22;
+static const int REF6_S8_ID=23;
+static const int INPUT7_S8_ID=24;
+static const int BIAS7_S8_ID=25;
+static const int WEIGHT7_S8_ID=26;
+static const int REF7_S8_ID=27;
+static const int INPUT8_S8_ID=28;
+static const int BIAS8_S8_ID=29;
+static const int WEIGHT8_S8_ID=30;
+static const int REF8_S8_ID=31;
+static const int INPUT9_S8_ID=32;
+static const int BIAS9_S8_ID=33;
+static const int WEIGHT9_S8_ID=34;
+static const int REF9_S8_ID=35;
+static const int INPUT10_S8_ID=36;
+static const int BIAS10_S8_ID=37;
+static const int WEIGHT10_S8_ID=38;
+static const int REF10_S8_ID=39;
+static const int INPUT11_S8_ID=40;
+static const int BIAS11_S8_ID=41;
+static const int WEIGHT11_S8_ID=42;
+static const int REF11_S8_ID=43;
+static const int INPUT12_S8_ID=44;
+static const int BIAS12_S8_ID=45;
+static const int WEIGHT12_S8_ID=46;
+static const int REF12_S8_ID=47;
+static const int INPUT13_S8_ID=48;
+static const int BIAS13_S8_ID=49;
+static const int WEIGHT13_S8_ID=50;
+static const int REF13_S8_ID=51;
+static const int INPUT14_S8_ID=52;
+static const int BIAS14_S8_ID=53;
+static const int WEIGHT14_S8_ID=54;
+static const int REF14_S8_ID=55;
+static const int INPUT15_S8_ID=56;
+static const int BIAS15_S8_ID=57;
+static const int WEIGHT15_S8_ID=58;
+static const int REF15_S8_ID=59;
 
 // Output IDs
-static const int OUTPUT1_S8_ID=0;
-static const int TEMP1_S16_ID=1;
-static const int OUTPUT19_S8_ID=2;
-static const int TEMP19_S16_ID=3;
-static const int OUTPUT2_S8_ID=4;
-static const int TEMP2_S16_ID=5;
-static const int OUTPUT3_S8_ID=6;
-static const int TEMP3_S16_ID=7;
-static const int OUTPUT4_S8_ID=8;
-static const int TEMP4_S16_ID=9;
-static const int OUTPUT5_S8_ID=10;
-static const int TEMP5_S16_ID=11;
-static const int OUTPUT6_S8_ID=12;
-static const int TEMP6_S16_ID=13;
-static const int OUTPUT7_S8_ID=14;
-static const int TEMP7_S16_ID=15;
-static const int OUTPUT8_S8_ID=16;
-static const int TEMP8_S16_ID=17;
-static const int OUTPUT9_S8_ID=18;
-static const int TEMP9_S16_ID=19;
-static const int OUTPUT10_S8_ID=20;
-static const int TEMP10_S16_ID=21;
-static const int OUTPUT11_S8_ID=22;
-static const int TEMP11_S16_ID=23;
-static const int OUTPUT12_S8_ID=24;
-static const int TEMP12_S16_ID=25;
-static const int OUTPUT13_S8_ID=26;
-static const int TEMP13_S16_ID=27;
-static const int OUTPUT14_S8_ID=28;
-static const int TEMP14_S16_ID=29;
+static const int OUTPUT_S8_ID=0;
+static const int TEMP_S16_ID=1;
 
 // Test IDs
 static const int TEST_FULLY_CONNECTED_TFLITE_S8_1=1;

Testing/GeneratedInclude/SVMF32_decl.h

@@ -0,0 +1,36 @@
+void test_svm_linear_predict_f32();
+void test_svm_polynomial_predict_f32();
+void test_svm_rbf_predict_f32();
+void test_svm_sigmoid_predict_f32();
+
+// Pattern IDs
+static const int SAMPLES1_F32_ID=0;
+static const int PARAMS1_F32_ID=1;
+static const int DIMS1_S16_ID=2;
+static const int REF1_S32_ID=3;
+static const int SAMPLES2_F32_ID=4;
+static const int PARAMS2_F32_ID=5;
+static const int DIMS2_S16_ID=6;
+static const int REF2_S32_ID=7;
+static const int SAMPLES3_F32_ID=8;
+static const int PARAMS3_F32_ID=9;
+static const int DIMS3_S16_ID=10;
+static const int REF3_S32_ID=11;
+static const int SAMPLES4_F32_ID=12;
+static const int PARAMS4_F32_ID=13;
+static const int DIMS4_S16_ID=14;
+static const int REF4_S32_ID=15;
+static const int SAMPLES5_F32_ID=16;
+static const int PARAMS5_F32_ID=17;
+static const int DIMS5_S16_ID=18;
+static const int REF5_S32_ID=19;
+
+// Output IDs
+static const int OUT_S32_ID=0;
+
+// Test IDs
+static const int TEST_SVM_LINEAR_PREDICT_F32_1=1;
+static const int TEST_SVM_POLYNOMIAL_PREDICT_F32_2=2;
+static const int TEST_SVM_RBF_PREDICT_F32_3=3;
+static const int TEST_SVM_SIGMOID_PREDICT_F32_4=4;
+static const int TEST_SVM_RBF_PREDICT_F32_5=5;

Testing/GeneratedInclude/TestDesc.h

@@ -1,6 +1,95 @@
 #include "Test.h"
 #include "Pattern.h"
+#include "BasicTestsF32.h"
+#include "SVMF32.h"
+#include "BasicMathsBenchmarksF32.h"
+#include "BasicMathsBenchmarksQ31.h"
+#include "BasicMathsBenchmarksQ15.h"
+#include "BasicMathsBenchmarksQ7.h"
 #include "FullyConnected.h"
+#include "FullyConnectedBench.h"
+class BasicTests : public Client::Group
+{
+   public:
+     BasicTests(Testing::testID_t id):Client::Group(id)
+ ,BasicTestsF32Var(1)
+
+     { 
+        this->addContainer(&BasicTestsF32Var);
+
+     }
+    private:
+        BasicTestsF32 BasicTestsF32Var;
+;
+};
+class SVMTests : public Client::Group
+{
+   public:
+     SVMTests(Testing::testID_t id):Client::Group(id)
+ ,SVMF32Var(1)
+
+     { 
+        this->addContainer(&SVMF32Var);
+
+     }
+    private:
+        SVMF32 SVMF32Var;
+;
+};
+class DSPTests : public Client::Group
+{
+   public:
+     DSPTests(Testing::testID_t id):Client::Group(id)
+ ,BasicTestsVar(1)
+,SVMTestsVar(2)
+
+     { 
+        this->addContainer(&BasicTestsVar);
+this->addContainer(&SVMTestsVar);
+
+     }
+    private:
+        BasicTests BasicTestsVar;
+SVMTests SVMTestsVar;
+;
+};
+class BasicBenchmarks : public Client::Group
+{
+   public:
+     BasicBenchmarks(Testing::testID_t id):Client::Group(id)
+ ,BasicMathsBenchmarksF32Var(1)
+,BasicMathsBenchmarksQ31Var(2)
+,BasicMathsBenchmarksQ15Var(3)
+,BasicMathsBenchmarksQ7Var(4)
+
+     { 
+        this->addContainer(&BasicMathsBenchmarksF32Var);
+this->addContainer(&BasicMathsBenchmarksQ31Var);
+this->addContainer(&BasicMathsBenchmarksQ15Var);
+this->addContainer(&BasicMathsBenchmarksQ7Var);
+
+     }
+    private:
+        BasicMathsBenchmarksF32 BasicMathsBenchmarksF32Var;
+BasicMathsBenchmarksQ31 BasicMathsBenchmarksQ31Var;
+BasicMathsBenchmarksQ15 BasicMathsBenchmarksQ15Var;
+BasicMathsBenchmarksQ7 BasicMathsBenchmarksQ7Var;
+;
+};
+class DSPBenchmarks : public Client::Group
+{
+   public:
+     DSPBenchmarks(Testing::testID_t id):Client::Group(id)
+ ,BasicBenchmarksVar(1)
+
+     { 
+        this->addContainer(&BasicBenchmarksVar);
+
+     }
+    private:
+        BasicBenchmarks BasicBenchmarksVar;
+;
+};
 class NNTests : public Client::Group
 {
    public:
@@ -15,17 +104,40 @@ class NNTests : public Client::Group
         FullyConnected FullyConnectedVar;
 ;
 };
+class NNBenchmarks : public Client::Group
+{
+   public:
+     NNBenchmarks(Testing::testID_t id):Client::Group(id)
+ ,FullyConnectedBenchVar(1)
+
+     { 
+        this->addContainer(&FullyConnectedBenchVar);
+
+     }
+    private:
+        FullyConnectedBench FullyConnectedBenchVar;
+;
+};
 class Root : public Client::Group
 {
    public:
      Root(Testing::testID_t id):Client::Group(id)
- ,NNTestsVar(3)
+ ,DSPTestsVar(1)
+,DSPBenchmarksVar(2)
+,NNTestsVar(3)
+,NNBenchmarksVar(4)
 
      { 
-        this->addContainer(NULL);this->addContainer(NULL);this->addContainer(&NNTestsVar);
-this->addContainer(NULL);
+        this->addContainer(&DSPTestsVar);
+this->addContainer(&DSPBenchmarksVar);
+this->addContainer(&NNTestsVar);
+this->addContainer(&NNBenchmarksVar);
+
      }
     private:
-        NNTests NNTestsVar;
+        DSPTests DSPTestsVar;
+DSPBenchmarks DSPBenchmarksVar;
+NNTests NNTestsVar;
+NNBenchmarks NNBenchmarksVar;
 ;
 };

Testing/GeneratedInclude/TestDrive.h

@@ -5,6 +5,409 @@ __ALIGNED(8) const char testDesc[]={
 1,0,0,0,
 'n','n',
 3,0,0,0,
+1,0,0,0,
+'n','y','D','S','P','\0',
+3,0,0,0,
+1,0,0,0,
+'n','y','B','a','s','i','c','M','a','t','h','s','\0',
+2,0,0,0,
+1,0,0,0,
+'n','y','B','a','s','i','c','M','a','t','h','s','F','3','2','\0',
+0,0,0,0,
+12,0,0,0,
+0,0,0,0,
+0,1,0,0,
+0,4,0,0,
+0,1,0,0,
+0,8,0,0,
+0,1,0,0,
+0,12,0,0,
+0,1,0,0,
+0,16,0,0,
+0,1,0,0,
+0,20,0,0,
+0,1,0,0,
+0,24,0,0,
+0,1,0,0,
+0,28,0,0,
+0,1,0,0,
+0,32,0,0,
+1,0,0,0,
+8,32,0,0,
+1,0,0,0,
+16,32,0,0,
+1,0,0,0,
+24,32,0,0,
+0,1,0,0,
+2,0,0,0,
+'O','u','t','p','u','t','\0',
+'S','t','a','t','e','\0',
+0,0,0,0,
+1,0,0,0,
+1,0,0,0,
+'n','n',
+1,0,0,0,
+2,0,0,0,
+'n','n',
+1,0,0,0,
+3,0,0,0,
+'n','n',
+1,0,0,0,
+4,0,0,0,
+'n','n',
+1,0,0,0,
+5,0,0,0,
+'n','n',
+1,0,0,0,
+6,0,0,0,
+'n','n',
+1,0,0,0,
+7,0,0,0,
+'n','n',
+1,0,0,0,
+8,0,0,0,
+'n','n',
+1,0,0,0,
+9,0,0,0,
+'n','n',
+1,0,0,0,
+10,0,0,0,
+'n','n',
+1,0,0,0,
+11,0,0,0,
+'n','n',
+1,0,0,0,
+12,0,0,0,
+'n','n',
+1,0,0,0,
+13,0,0,0,
+'n','n',
+1,0,0,0,
+14,0,0,0,
+'n','n',
+1,0,0,0,
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+'n','n',
+1,0,0,0,
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+'n','n',
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+'n','n',
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+'n','n',
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+'n','n',
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+'n','n',
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+'n','n',
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+'n','n',
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+'n','n',
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+'n','y','S','V','M','\0',
+2,0,0,0,
+1,0,0,0,
+'n','y','S','V','M','F','3','2','\0',
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+112,73,0,0,
+232,3,0,0,
+16,89,0,0,
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+224,90,0,0,
+100,0,0,0,
+112,92,0,0,
+232,3,0,0,
+16,108,0,0,
+113,0,0,0,
+216,109,0,0,
+6,0,0,0,
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+100,0,0,0,
+120,111,0,0,
+232,3,0,0,
+24,127,0,0,
+46,0,0,0,
+208,127,0,0,
+6,0,0,0,
+224,127,0,0,
+100,0,0,0,
+1,0,0,0,
+'O','u','t','p','u','t','\0',
+0,0,0,0,
+1,0,0,0,
+1,0,0,0,
+'n','n',
+1,0,0,0,
+2,0,0,0,
+'n','n',
+1,0,0,0,
+3,0,0,0,
+'n','n',
+1,0,0,0,
+4,0,0,0,
+'n','n',
+1,0,0,0,
+5,0,0,0,
+'n','n',
+3,0,0,0,
+2,0,0,0,
+'n','y','D','S','P','\0',
+3,0,0,0,
+1,0,0,0,
+'n','y','B','a','s','i','c','M','a','t','h','s','\0',
+2,0,0,0,
+1,0,0,0,
+'y',0,0,0,0,
+'y','B','a','s','i','c','M','a','t','h','s','F','3','2','\0',
+1,0,0,0,
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+112,129,0,0,
+0,1,0,0,
+112,133,0,0,
+0,1,0,0,
+1,0,0,0,
+'O','u','t','p','u','t','\0',
+1,0,0,0,
+'g',1,0,0,0,
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+64,0,0,0,
+128,0,0,0,
+0,1,0,0,
+1,0,0,0,
+1,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+2,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+3,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+4,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+5,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+6,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+7,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+8,0,0,0,
+'y',0,0,0,0,
+'n',
+2,0,0,0,
+2,0,0,0,
+'y',0,0,0,0,
+'y','B','a','s','i','c','M','a','t','h','s','Q','3','1','\0',
+1,0,0,0,
+2,0,0,0,
+112,137,0,0,
+0,1,0,0,
+112,141,0,0,
+0,1,0,0,
+1,0,0,0,
+'O','u','t','p','u','t','\0',
+1,0,0,0,
+'g',1,0,0,0,
+6,0,0,0,
+5,0,0,0,
+1,0,0,0,
+5,0,0,0,
+16,0,0,0,
+32,0,0,0,
+64,0,0,0,
+128,0,0,0,
+0,1,0,0,
+1,0,0,0,
+1,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+2,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+3,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+4,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+5,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+6,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+7,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+8,0,0,0,
+'y',0,0,0,0,
+'n',
+2,0,0,0,
+3,0,0,0,
+'y',0,0,0,0,
+'y','B','a','s','i','c','M','a','t','h','s','Q','1','5','\0',
+1,0,0,0,
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+0,1,0,0,
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+0,1,0,0,
+1,0,0,0,
+'O','u','t','p','u','t','\0',
+1,0,0,0,
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+0,1,0,0,
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+'n',
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+'y',0,0,0,0,
+'n',
+1,0,0,0,
+3,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
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+'y',0,0,0,0,
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+'n',
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+6,0,0,0,
+'y',0,0,0,0,
+'n',
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+'y',0,0,0,0,
+'n',
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+'y',0,0,0,0,
+'n',
+2,0,0,0,
+4,0,0,0,
+'y',0,0,0,0,
+'y','B','a','s','i','c','M','a','t','h','s','Q','7','\0',
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+0,1,0,0,
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+16,0,0,0,
+32,0,0,0,
+64,0,0,0,
+128,0,0,0,
+0,1,0,0,
+1,0,0,0,
+1,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+2,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+3,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+4,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+5,0,0,0,
+'y',0,0,0,0,
+'n',
+1,0,0,0,
+6,0,0,0,
+'y',0,0,0,0,
+'n',
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+'y',0,0,0,0,
+'n',
+1,0,0,0,
+8,0,0,0,
+'y',0,0,0,0,
+'n',
+3,0,0,0,
 3,0,0,0,
 'n','y','N','N','\0',
 2,0,0,0,
@@ -12,157 +415,129 @@ __ALIGNED(8) const char testDesc[]={
 'n','y','F','u','l','l','y','C','o','n','n','e','c','t','e','d','\0',
 0,0,0,0,
 60,0,0,0,
-0,0,0,0,
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 10,0,0,0,
-16,0,0,0,
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 4,0,0,0,
-24,0,0,0,
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 40,0,0,0,
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 8,0,0,0,
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 9,0,0,0,
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 9,0,0,0,
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 10,0,0,0,
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 4,0,0,0,
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 40,0,0,0,
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 4,0,0,0,
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 9,0,0,0,
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 1,0,0,0,
-24,1,0,0,
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 9,0,0,0,
-40,1,0,0,
+152,152,0,0,
 1,0,0,0,
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 8,0,0,0,
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 8,0,0,0,
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 64,0,0,0,
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 54,0,0,0,
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+80,153,0,0,
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 9,0,0,0,
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 1,0,0,0,
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 10,0,0,0,
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 4,0,0,0,
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 8,0,0,0,
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 8,0,0,0,
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 72,0,0,0,
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 4,0,0,0,
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 32,0,0,0,
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+88,155,0,0,
 36,0,0,0,
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+128,155,0,0,
 64,0,0,0,
-80,4,0,0,
+192,155,0,0,
 5,0,0,0,
-88,4,0,0,
+200,155,0,0,
 40,0,0,0,
-128,4,0,0,
+240,155,0,0,
 40,0,0,0,
-168,4,0,0,
+24,156,0,0,
 28,0,0,0,
-200,4,0,0,
+56,156,0,0,
 3,0,0,0,
-208,4,0,0,
+64,156,0,0,
 21,0,0,0,
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+88,156,0,0,
 12,0,0,0,
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 56,0,0,0,
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+160,156,0,0,
 4,0,0,0,
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+168,156,0,0,
 28,0,0,0,
-88,5,0,0,
+200,156,0,0,
 32,0,0,0,
-30,0,0,0,
-'O','u','t','p','u','t','1','\0',
-'T','e','m','p','1','\0',
-'O','u','t','p','u','t','1','9','\0',
-'T','e','m','p','1','9','\0',
-'O','u','t','p','u','t','2','\0',
-'T','e','m','p','2','\0',
-'O','u','t','p','u','t','3','\0',
-'T','e','m','p','3','\0',
-'O','u','t','p','u','t','4','\0',
-'T','e','m','p','4','\0',
-'O','u','t','p','u','t','5','\0',
-'T','e','m','p','5','\0',
-'O','u','t','p','u','t','6','\0',
-'T','e','m','p','6','\0',
-'O','u','t','p','u','t','7','\0',
-'T','e','m','p','7','\0',
-'O','u','t','p','u','t','8','\0',
-'T','e','m','p','8','\0',
-'O','u','t','p','u','t','9','\0',
-'T','e','m','p','9','\0',
-'O','u','t','p','u','t','1','0','\0',
-'T','e','m','p','1','0','\0',
-'O','u','t','p','u','t','1','1','\0',
-'T','e','m','p','1','1','\0',
-'O','u','t','p','u','t','1','2','\0',
-'T','e','m','p','1','2','\0',
-'O','u','t','p','u','t','1','3','\0',
-'T','e','m','p','1','3','\0',
-'O','u','t','p','u','t','1','4','\0',
-'T','e','m','p','1','4','\0',
+2,0,0,0,
+'O','u','t','p','u','t','\0',
+'T','e','m','p','\0',
 0,0,0,0,
 1,0,0,0,
 1,0,0,0,
@@ -209,5 +584,38 @@ __ALIGNED(8) const char testDesc[]={
 1,0,0,0,
 15,0,0,0,
 'n','n',
+3,0,0,0,
+4,0,0,0,
+'n','y','N','N','\0',
+2,0,0,0,
+1,0,0,0,
+'n','y','F','u','l','l','y','C','o','n','n','e','c','t','e','d','\0',
+1,0,0,0,
+4,0,0,0,
+232,156,0,0,
+10,0,0,0,
+248,156,0,0,
+4,0,0,0,
+0,157,0,0,
+40,0,0,0,
+40,157,0,0,
+4,0,0,0,
+2,0,0,0,
+'O','u','t','p','u','t','\0',
+'T','e','m','p','\0',
+1,0,0,0,
+'g',1,0,0,0,
+5,0,0,0,
+4,0,0,0,
+1,0,0,0,
+4,0,0,0,
+10,0,0,0,
+20,0,0,0,
+100,0,0,0,
+200,0,0,0,
+1,0,0,0,
+1,0,0,0,
+'y',0,0,0,0,
+'n',
 };
 #endif

Testing/GeneratedSource/TestDesc.cpp

@@ -1,5 +1,102 @@
 #include "Test.h"
 
+#include "BasicTestsF32.h"
+    BasicTestsF32::BasicTestsF32(Testing::testID_t id):Client::Suite(id)
+    {
+        this->addTest(1,(Client::test)&BasicTestsF32::test_add_f32);
+this->addTest(2,(Client::test)&BasicTestsF32::test_add_f32);
+this->addTest(3,(Client::test)&BasicTestsF32::test_add_f32);
+this->addTest(4,(Client::test)&BasicTestsF32::test_sub_f32);
+this->addTest(5,(Client::test)&BasicTestsF32::test_sub_f32);
+this->addTest(6,(Client::test)&BasicTestsF32::test_sub_f32);
+this->addTest(7,(Client::test)&BasicTestsF32::test_mult_f32);
+this->addTest(8,(Client::test)&BasicTestsF32::test_mult_f32);
+this->addTest(9,(Client::test)&BasicTestsF32::test_mult_f32);
+this->addTest(10,(Client::test)&BasicTestsF32::test_negate_f32);
+this->addTest(11,(Client::test)&BasicTestsF32::test_negate_f32);
+this->addTest(12,(Client::test)&BasicTestsF32::test_negate_f32);
+this->addTest(13,(Client::test)&BasicTestsF32::test_offset_f32);
+this->addTest(14,(Client::test)&BasicTestsF32::test_offset_f32);
+this->addTest(15,(Client::test)&BasicTestsF32::test_offset_f32);
+this->addTest(16,(Client::test)&BasicTestsF32::test_scale_f32);
+this->addTest(17,(Client::test)&BasicTestsF32::test_scale_f32);
+this->addTest(18,(Client::test)&BasicTestsF32::test_scale_f32);
+this->addTest(19,(Client::test)&BasicTestsF32::test_dot_prod_f32);
+this->addTest(20,(Client::test)&BasicTestsF32::test_dot_prod_f32);
+this->addTest(21,(Client::test)&BasicTestsF32::test_dot_prod_f32);
+this->addTest(22,(Client::test)&BasicTestsF32::test_abs_f32);
+this->addTest(23,(Client::test)&BasicTestsF32::test_abs_f32);
+this->addTest(24,(Client::test)&BasicTestsF32::test_abs_f32);
+
+    }
+
+#include "SVMF32.h"
+    SVMF32::SVMF32(Testing::testID_t id):Client::Suite(id)
+    {
+        this->addTest(1,(Client::test)&SVMF32::test_svm_linear_predict_f32);
+this->addTest(2,(Client::test)&SVMF32::test_svm_polynomial_predict_f32);
+this->addTest(3,(Client::test)&SVMF32::test_svm_rbf_predict_f32);
+this->addTest(4,(Client::test)&SVMF32::test_svm_sigmoid_predict_f32);
+this->addTest(5,(Client::test)&SVMF32::test_svm_rbf_predict_f32);
+
+    }
+
+#include "BasicMathsBenchmarksF32.h"
+    BasicMathsBenchmarksF32::BasicMathsBenchmarksF32(Testing::testID_t id):Client::Suite(id)
+    {
+        this->addTest(1,(Client::test)&BasicMathsBenchmarksF32::vec_mult_f32);
+this->addTest(2,(Client::test)&BasicMathsBenchmarksF32::vec_add_f32);
+this->addTest(3,(Client::test)&BasicMathsBenchmarksF32::vec_sub_f32);
+this->addTest(4,(Client::test)&BasicMathsBenchmarksF32::vec_abs_f32);
+this->addTest(5,(Client::test)&BasicMathsBenchmarksF32::vec_negate_f32);
+this->addTest(6,(Client::test)&BasicMathsBenchmarksF32::vec_offset_f32);
+this->addTest(7,(Client::test)&BasicMathsBenchmarksF32::vec_scale_f32);
+this->addTest(8,(Client::test)&BasicMathsBenchmarksF32::vec_dot_f32);
+
+    }
+
+#include "BasicMathsBenchmarksQ31.h"
+    BasicMathsBenchmarksQ31::BasicMathsBenchmarksQ31(Testing::testID_t id):Client::Suite(id)
+    {
+        this->addTest(1,(Client::test)&BasicMathsBenchmarksQ31::vec_mult_q31);
+this->addTest(2,(Client::test)&BasicMathsBenchmarksQ31::vec_add_q31);
+this->addTest(3,(Client::test)&BasicMathsBenchmarksQ31::vec_sub_q31);
+this->addTest(4,(Client::test)&BasicMathsBenchmarksQ31::vec_abs_q31);
+this->addTest(5,(Client::test)&BasicMathsBenchmarksQ31::vec_negate_q31);
+this->addTest(6,(Client::test)&BasicMathsBenchmarksQ31::vec_offset_q31);
+this->addTest(7,(Client::test)&BasicMathsBenchmarksQ31::vec_scale_q31);
+this->addTest(8,(Client::test)&BasicMathsBenchmarksQ31::vec_dot_q31);
+
+    }
+
+#include "BasicMathsBenchmarksQ15.h"
+    BasicMathsBenchmarksQ15::BasicMathsBenchmarksQ15(Testing::testID_t id):Client::Suite(id)
+    {
+        this->addTest(1,(Client::test)&BasicMathsBenchmarksQ15::vec_mult_q15);
+this->addTest(2,(Client::test)&BasicMathsBenchmarksQ15::vec_add_q15);
+this->addTest(3,(Client::test)&BasicMathsBenchmarksQ15::vec_sub_q15);
+this->addTest(4,(Client::test)&BasicMathsBenchmarksQ15::vec_abs_q15);
+this->addTest(5,(Client::test)&BasicMathsBenchmarksQ15::vec_negate_q15);
+this->addTest(6,(Client::test)&BasicMathsBenchmarksQ15::vec_offset_q15);
+this->addTest(7,(Client::test)&BasicMathsBenchmarksQ15::vec_scale_q15);
+this->addTest(8,(Client::test)&BasicMathsBenchmarksQ15::vec_dot_q15);
+
+    }
+
+#include "BasicMathsBenchmarksQ7.h"
+    BasicMathsBenchmarksQ7::BasicMathsBenchmarksQ7(Testing::testID_t id):Client::Suite(id)
+    {
+        this->addTest(1,(Client::test)&BasicMathsBenchmarksQ7::vec_mult_q7);
+this->addTest(2,(Client::test)&BasicMathsBenchmarksQ7::vec_add_q7);
+this->addTest(3,(Client::test)&BasicMathsBenchmarksQ7::vec_sub_q7);
+this->addTest(4,(Client::test)&BasicMathsBenchmarksQ7::vec_abs_q7);
+this->addTest(5,(Client::test)&BasicMathsBenchmarksQ7::vec_negate_q7);
+this->addTest(6,(Client::test)&BasicMathsBenchmarksQ7::vec_offset_q7);
+this->addTest(7,(Client::test)&BasicMathsBenchmarksQ7::vec_scale_q7);
+this->addTest(8,(Client::test)&BasicMathsBenchmarksQ7::vec_dot_q7);
+
+    }
+
 #include "FullyConnected.h"
     FullyConnected::FullyConnected(Testing::testID_t id):Client::Suite(id)
     {
@@ -20,3 +117,10 @@ this->addTest(14,(Client::test)&FullyConnected::test_fully_connected_tflite_s8);
 this->addTest(15,(Client::test)&FullyConnected::test_fully_connected_tflite_s8);
 
     }
+
+#include "FullyConnectedBench.h"
+    FullyConnectedBench::FullyConnectedBench(Testing::testID_t id):Client::Suite(id)
+    {
+        this->addTest(1,(Client::test)&FullyConnectedBench::test_fully_connected_tflite_s8);
+
+    }

Testing/Include/BasicMathsBenchmarksQ15.h

@@ -0,0 +1,17 @@
+#include "Test.h"
+#include "Pattern.h"
+class BasicMathsBenchmarksQ15:public Client::Suite
+    {
+        public:
+            BasicMathsBenchmarksQ15(Testing::testID_t id);
+            void setUp(Testing::testID_t,std::vector<Testing::param_t>& params,Client::PatternMgr *mgr);
+            void tearDown(Testing::testID_t,Client::PatternMgr *mgr);
+        private:
+            #include "BasicMathsBenchmarksQ15_decl.h"
+            Client::Pattern<q15_t> input1;
+            Client::Pattern<q15_t> input2;
+            Client::LocalPattern<q15_t> output;
+
+            int nb;
+            
+    };

Testing/Include/BasicMathsBenchmarksQ7.h

@@ -0,0 +1,17 @@
+#include "Test.h"
+#include "Pattern.h"
+class BasicMathsBenchmarksQ7:public Client::Suite
+    {
+        public:
+            BasicMathsBenchmarksQ7(Testing::testID_t id);
+            void setUp(Testing::testID_t,std::vector<Testing::param_t>& params,Client::PatternMgr *mgr);
+            void tearDown(Testing::testID_t,Client::PatternMgr *mgr);
+        private:
+            #include "BasicMathsBenchmarksQ7_decl.h"
+            Client::Pattern<q7_t> input1;
+            Client::Pattern<q7_t> input2;
+            Client::LocalPattern<q7_t> output;
+
+            int nb;
+            
+    };

Testing/Include/SVMF32.h

@@ -0,0 +1,38 @@
+#include "Test.h"
+#include "Pattern.h"
+class SVMF32:public Client::Suite
+    {
+        public:
+            SVMF32(Testing::testID_t id);
+            void setUp(Testing::testID_t,std::vector<Testing::param_t>& params,Client::PatternMgr *mgr);
+            void tearDown(Testing::testID_t,Client::PatternMgr *mgr);
+        private:
+            #include "SVMF32_decl.h"
+            Client::Pattern<float32_t> samples;
+            Client::Pattern<int16_t> dims;
+            Client::Pattern<float32_t> params;
+
+            Client::RefPattern<int32_t> ref;
+            Client::LocalPattern<int32_t> output;
+
+            arm_svm_linear_instance_f32 linear;
+            arm_svm_polynomial_instance_f32 poly;
+            arm_svm_rbf_instance_f32 rbf;
+            arm_svm_sigmoid_instance_f32 sigmoid;
+
+            int vecDim,nbSupportVectors,nbTestSamples,degree;
+            int classes[2]={0,0};
+            float32_t intercept;
+            const float32_t *supportVectors;
+            const float32_t *dualCoefs;
+            float32_t coef0, gamma;
+
+            enum {
+                LINEAR=1,
+                POLY=2,
+                RBF=3,
+                SIGMOID=4
+            } kind;
+
+            
+    };

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_1.txt

@@ -1,3 +1,3 @@
-0x3f50f0a2
-0x3e9dfdde
-0x3f1b759e
+0x3d8ad5b6
+0x3f3faddc
+0x3e059380

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_10.txt

@@ -1,3 +1,3 @@
-0xbf93509c
-0xbf1cde02
-0xbf4d4504
+0xbd4a980f
+0xbf0bda79
+0xbdc2eb9d

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_11.txt

@@ -1,8 +1,8 @@
-0xbf93509c
-0xbf1cde02
-0xbf4d4504
-0xc0125f3b
-0xbf180356
-0x3fdf54f1
-0xbec49138
-0xbfceaf77
+0xbd4a980f
+0xbf0bda79
+0xbdc2eb9d
+0xbdaea60a
+0x3e4722af
+0x3cd77ffd
+0x3d9f7226
+0x3cf35673

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_12.txt

@@ -1,9 +1,9 @@
-0xbf93509c
-0xbf1cde02
-0xbf4d4504
-0xc0125f3b
-0xbf180356
-0x3fdf54f1
-0xbec49138
-0xbfceaf77
-0xbedf6939
+0xbd4a980f
+0xbf0bda79
+0xbdc2eb9d
+0xbdaea60a
+0x3e4722af
+0x3cd77ffd
+0x3d9f7226
+0x3cf35673
+0x3b754527

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_13.txt

@@ -1,3 +1,3 @@
-0x3fd3509c
-0x3f8e6f01
-0x3fa6a282
+0x3f0ca981
+0x3f85ed3c
+0x3f185d74

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_14.txt

@@ -1,8 +1,8 @@
-0x3fd3509c
-0x3f8e6f01
-0x3fa6a282
-0x40325f3b
-0x3f8c01ab
-0xbf9f54f1
-0x3f62489c
-0x400757bc
+0x3f0ca981
+0x3f85ed3c
+0x3f185d74
+0x3f15d4c1
+0x3e9c6ea8
+0x3ef28800
+0x3ed82376
+0x3ef0ca99

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_15.txt

@@ -1,9 +1,9 @@
-0x3fd3509c
-0x3f8e6f01
-0x3fa6a282
-0x40325f3b
-0x3f8c01ab
-0xbf9f54f1
-0x3f62489c
-0x400757bc
-0x3f6fb49c
+0x3f0ca981
+0x3f85ed3c
+0x3f185d74
+0x3f15d4c1
+0x3e9c6ea8
+0x3ef28800
+0x3ed82376
+0x3ef0ca99
+0x3efe1576

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_16.txt

@@ -1,3 +1,3 @@
-0x3f13509c
-0x3e9cde02
-0x3ecd4504
+0x3cca980f
+0x3e8bda79
+0x3d42eb9d

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_17.txt

@@ -1,8 +1,8 @@
-0x3f13509c
-0x3e9cde02
-0x3ecd4504
-0x3f925f3b
-0x3e980356
-0xbf5f54f1
-0x3e449138
-0x3f4eaf77
+0x3cca980f
+0x3e8bda79
+0x3d42eb9d
+0x3d2ea60a
+0xbdc722af
+0xbc577ffd
+0xbd1f7226
+0xbc735673

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_18.txt

@@ -1,9 +1,9 @@
-0x3f13509c
-0x3e9cde02
-0x3ecd4504
-0x3f925f3b
-0x3e980356
-0xbf5f54f1
-0x3e449138
-0x3f4eaf77
-0x3e5f6939
+0x3cca980f
+0x3e8bda79
+0x3d42eb9d
+0x3d2ea60a
+0xbdc722af
+0xbc577ffd
+0xbd1f7226
+0xbc735673
+0xbaf54527

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_2.txt

@@ -1,8 +1,8 @@
-0x3f50f0a2
-0x3e9dfdde
-0x3f1b759e
-0x3fea6ff6
-0x3ed90c26
-0xbf7bca6c
-0x3fcd7bc2
-0x3fb3463e
+0x3d8ad5b6
+0x3f3faddc
+0x3e059380
+0x3def5e52
+0xbe8876f9
+0xbd13add8
+0xbdda8834
+0xbd26c182

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_22.txt

@@ -1,3 +1,3 @@
-0x3f93509c
-0x3f1cde02
-0x3f4d4504
+0x3d4a980f
+0x3f0bda79
+0x3dc2eb9d

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_23.txt

@@ -1,8 +1,8 @@
-0x3f93509c
-0x3f1cde02
-0x3f4d4504
-0x40125f3b
-0x3f180356
-0x3fdf54f1
-0x3ec49138
-0x3fceaf77
+0x3d4a980f
+0x3f0bda79
+0x3dc2eb9d
+0x3daea60a
+0x3e4722af
+0x3cd77ffd
+0x3d9f7226
+0x3cf35673

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_24.txt

@@ -1,9 +1,9 @@
-0x3f93509c
-0x3f1cde02
-0x3f4d4504
-0x40125f3b
-0x3f180356
-0x3fdf54f1
-0x3ec49138
-0x3fceaf77
-0x3edf6939
+0x3d4a980f
+0x3f0bda79
+0x3dc2eb9d
+0x3daea60a
+0x3e4722af
+0x3cd77ffd
+0x3d9f7226
+0x3cf35673
+0x3b754527

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_3.txt

@@ -1,9 +1,9 @@
-0x3f50f0a2
-0x3e9dfdde
-0x3f1b759e
-0x3fea6ff6
-0x3ed90c26
-0xbf7bca6c
-0x3fcd7bc2
-0x3fb3463e
-0x3f472a19
+0x3d8ad5b6
+0x3f3faddc
+0x3e059380
+0x3def5e52
+0xbe8876f9
+0xbd13add8
+0xbdda8834
+0xbd26c182
+0xbba81486

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_4.txt

@@ -1,3 +1,3 @@
-0x3fbe28e7
-0x3f6abd15
-0x3f7f146a
+0x3cff0966
+0x3eb00e2c
+0x3d756072

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_5.txt

@@ -1,8 +1,8 @@
-0x3fbe28e7
-0x3f6abd15
-0x3f7f146a
-0x402f867b
-0x3f438099
-0xc0206256
-0xbf56664c
-0x3fea18b0
+0x3cff0966
+0x3eb00e2c
+0x3d756072
+0x3d5bdb84
+0xbdfaaed7
+0xbc87a449
+0xbd48b830
+0xbc9929e2

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_6.txt

@@ -1,9 +1,9 @@
-0x3fbe28e7
-0x3f6abd15
-0x3f7f146a
-0x402f867b
-0x3f438099
-0xc0206256
-0xbf56664c
-0x3fea18b0
-0x3dc1f900
+0x3cff0966
+0x3eb00e2c
+0x3d756072
+0x3d5bdb84
+0xbdfaaed7
+0xbc87a449
+0xbd48b830
+0xbc9929e2
+0xbb1a6143

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_7.txt

@@ -1,3 +1,3 @@
-0xbec53d86
-0xbe3edddf
-0xbe1fc20a
+0x3a6da77a
+0x3de2800b
+0x3b5bfdf2

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_8.txt

@@ -1,8 +1,8 @@
-0xbec53d86
-0xbe3edddf
-0xbe1fc20a
-0xbf8559d7
-0xbdce9786
-0xbfaa0151
-0x3ef01749
-0xbeb10ba9
+0x3a6da77a
+0x3de2800b
+0x3b5bfdf2
+0x3b309cec
+0x3c659c04
+0x398672e2
+0x3b13342e
+0x39ab6d83

Testing/Output/DSP/BasicMaths/BasicMathsF32/Output_9.txt

@@ -1,9 +1,9 @@
-0xbec53d86
-0xbe3edddf
-0xbe1fc20a
-0xbf8559d7
-0xbdce9786
-0xbfaa0151
-0x3ef01749
-0xbeb10ba9
-0x3e18a694
+0x3a6da77a
+0x3de2800b
+0x3b5bfdf2
+0x3b309cec
+0x3c659c04
+0x398672e2
+0x3b13342e
+0x39ab6d83
+0x36ae294d

Testing/Output/DSP/SVM/SVMF32/Output_1.txt

@@ -0,0 +1,100 @@
+0x00000000
+0x00000001
+0x00000001
+0x00000000
+0x00000000
+0x00000000
+0x00000001
+0x00000001
+0x00000000
+0x00000000
+0x00000001
+0x00000001
+0x00000000
+0x00000000
+0x00000000
+0x00000001
+0x00000001
+0x00000001
+0x00000001
+0x00000001
+0x00000001
+0x00000000
+0x00000000
+0x00000000
+0x00000000
+0x00000001
+0x00000001
+0x00000001
+0x00000000
+0x00000001
+0x00000001
+0x00000000
+0x00000000
+0x00000000
+0x00000001
+0x00000000
+0x00000000
+0x00000000
+0x00000000
+0x00000001
+0x00000000
+0x00000001
+0x00000000
+0x00000001
+0x00000000
+0x00000000
+0x00000001
+0x00000001
+0x00000001
+0x00000001
+0x00000001
+0x00000000
+0x00000000
+0x00000001
+0x00000000
+0x00000000
+0x00000001
+0x00000000
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+0x00000001

Testing/Output/DSP/SVM/SVMF32/Output_2.txt

@@ -0,0 +1,100 @@
+0x00000000
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+0x00000001

Testing/Output/DSP/SVM/SVMF32/Output_3.txt

@@ -0,0 +1,100 @@
+0x00000001
+0x00000000
+0x00000001
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Testing/Output/DSP/SVM/SVMF32/Output_4.txt

@@ -0,0 +1,100 @@
+0x00000000
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+0x00000001

Testing/Output/DSP/SVM/SVMF32/Output_5.txt

@@ -0,0 +1,100 @@
+0x00000001
+0xffffffff
+0x00000001
+0xffffffff
+0xffffffff
+0xffffffff
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+0xffffffff

Testing/PatternGeneration/BasicMaths.py

@@ -1,241 +1,7 @@
 import os.path
 import numpy as np
-import struct
 import itertools
-
-
-def createMissingDir(destPath):
-  theDir=os.path.normpath(destPath)
-  if not os.path.exists(theDir):
-      os.makedirs(theDir)
-
-def float_to_hex(f):
-    """ Convert and x86 float to an ARM unsigned long int.
-  
-    Args:
-      f (float): value to be converted
-    Raises:
-      Nothing 
-    Returns:
-      str : representation of the hex value
-    """
-    return hex(struct.unpack('<I', struct.pack('<f', f))[0])
-
-def to_q31(v):
-    r = int(round(v * 2**31))
-    if (r > 0x07FFFFFFF):
-      r = 0x07FFFFFFF
-    if (r < -0x080000000):
-      r = -0x080000000
-    return hex(struct.unpack('<I', struct.pack('<i', r))[0])
-
-def to_q15(v):
-    r = int(round(v * 2**15))
-    if (r > 0x07FFF):
-      r = 0x07FFF
-    if (r < -0x08000):
-      r = -0x08000
-    return hex(struct.unpack('<H', struct.pack('<h', r))[0])
-
-def to_q7(v):
-    r = int(round(v * 2**7))
-    if (r > 0x07F):
-      r = 0x07F
-    if (r < -0x080):
-      r = -0x080
-    return hex(struct.unpack('<B', struct.pack('<b', r))[0])
-
-class Config:
-    def __init__(self,patternDir,paramDir,ext):
-      self._patternDir = "%s%s" % (patternDir,ext.upper())
-      self._paramDir = "%s%s" % (paramDir,ext.upper())
-      self._ext = ext 
-
-      createMissingDir(self._patternDir)
-      createMissingDir(self._paramDir)
-
-    
-    def inputP(self,i):
-        """ Path to a reference pattern from the ID
-      
-        Args:
-          i (int): ID to the reference pattern
-        Raises:
-          Nothing 
-        Returns:
-          str : path to the file where to generate the pattern data
-        """
-        return(os.path.join(self._patternDir,"Input%d_%s.txt" % (i,self._ext)))
-
-    def refP(self,i):
-        """ Path to a reference pattern from the ID
-      
-        Args:
-          i (int): ID to the reference pattern
-        Raises:
-          Nothing 
-        Returns:
-          str : path to the file where to generate the pattern data
-        """
-        return(os.path.join(self._patternDir,"Reference%d_%s.txt" % (i,self._ext)))
-
-    def paramP(self,i):
-        """ Path to a parameters from the ID
-      
-        Args:
-          i (int): ID to the params
-        Raises:
-          Nothing 
-        Returns:
-          str : path to the file where to generate the pattern data
-        """
-        return(os.path.join(self._paramDir,"Params%d.txt" % i))
-
-    def _writeVectorF32(self,i,data):
-        """ Write pattern data
-        
-        The format is recognized by the text framework script.
-        First line is the sample width (B,H or W for 8,16 or 32 bits)
-        Second line is number of samples
-        Other lines are hexadecimal representation of the samples in format
-        which can be read on big endian ARM.
-        
-          Args:
-            j (int): ID of pattern file
-            data (array): Vector containing the data
-          Raises:
-            Nothing 
-          Returns:
-            Nothing
-        """
-        with open(i,"w") as f:
-            # Write sample dimension nb sample header
-            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
-            f.write("W\n%d\n" % len(data))
-            for v in data:
-                f.write("// %f\n" % v)
-                f.write("%s\n" % float_to_hex(v))
-
-    def _writeVectorQ31(self,i,data):
-        """ Write pattern data
-        
-        The format is recognized by the text framework script.
-        First line is the sample width (B,H or W for 8,16 or 32 bits)
-        Second line is number of samples
-        Other lines are hexadecimal representation of the samples in format
-        which can be read on big endian ARM.
-        
-          Args:
-            j (int): ID of pattern file
-            data (array): Vector containing the data
-          Raises:
-            Nothing 
-          Returns:
-            Nothing
-        """
-        with open(i,"w") as f:
-            # Write sample dimension nb sample header
-            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
-            f.write("W\n%d\n" % len(data))
-            for v in data:
-                f.write("// %f\n" % v)
-                f.write("%s\n" % to_q31(v))
-
-    def _writeVectorQ15(self,i,data):
-        """ Write pattern data
-        
-        The format is recognized by the text framework script.
-        First line is the sample width (B,H or W for 8,16 or 32 bits)
-        Second line is number of samples
-        Other lines are hexadecimal representation of the samples in format
-        which can be read on big endian ARM.
-        
-          Args:
-            j (int): ID of pattern file
-            data (array): Vector containing the data
-          Raises:
-            Nothing 
-          Returns:
-            Nothing
-        """
-        with open(i,"w") as f:
-            # Write sample dimension nb sample header
-            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
-            f.write("H\n%d\n" % len(data))
-            for v in data:
-                f.write("// %f\n" % v)
-                f.write("%s\n" % to_q15(v))
-
-    def _writeVectorQ7(self,i,data):
-        """ Write pattern data
-        
-        The format is recognized by the text framework script.
-        First line is the sample width (B,H or W for 8,16 or 32 bits)
-        Second line is number of samples
-        Other lines are hexadecimal representation of the samples in format
-        which can be read on big endian ARM.
-        
-          Args:
-            j (int): ID of pattern file
-            data (array): Vector containing the data
-          Raises:
-            Nothing 
-          Returns:
-            Nothing
-        """
-        with open(i,"w") as f:
-            # Write sample dimension nb sample header
-            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
-            f.write("B\n%d\n" % len(data))
-            for v in data:
-                f.write("// %f\n" % v)
-                f.write("%s\n" % to_q7(v))
-
-    def writeVector(self,j,data):
-        if (self._ext == "f32"):
-          self._writeVectorF32(self.refP(j),data)
-        if (self._ext == "q31"):
-          self._writeVectorQ31(self.refP(j),data)
-        if (self._ext == "q15"):
-          self._writeVectorQ15(self.refP(j),data)
-        if (self._ext == "q7"):
-          self._writeVectorQ7(self.refP(j),data)
-
-    def writeInput(self,j,data):
-        if (self._ext == "f32"):
-          self._writeVectorF32(self.inputP(j),data)
-        if (self._ext == "q31"):
-          self._writeVectorQ31(self.inputP(j),data)
-        if (self._ext == "q15"):
-          self._writeVectorQ15(self.inputP(j),data)
-        if (self._ext == "q7"):
-          self._writeVectorQ7(self.inputP(j),data)
-
-    def writeParam(self,j,data):
-        """ Write pattern data
-        
-        The format is recognized by the text framework script.
-        First line is the sample width (B,H or W for 8,16 or 32 bits)
-        Second line is number of samples
-        Other lines are hexadecimal representation of the samples in format
-        which can be read on big endian ARM.
-        
-          Args:
-            j (int): ID of parameter file
-            data (array): Vector containing the data
-          Raises:
-            Nothing 
-          Returns:
-            Nothing
-        """
-        i=self.paramP(j)
-        with open(i,"w") as f:
-            # Write sample dimension nb sample header
-            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
-            f.write("%d\n" % len(data))
-            for v in data:
-                f.write("%d\n" % v)
-
+import Tools
 
 
 
@@ -254,46 +20,46 @@ def writeTests(config):
     config.writeInput(2, data2)
     
     ref = data1 + data2
-    config.writeVector(1, ref)
+    config.writeReference(1, ref)
     
     ref = data1 - data2
-    config.writeVector(2, ref)
+    config.writeReference(2, ref)
     
     ref = data1 * data2
-    config.writeVector(3, ref)
+    config.writeReference(3, ref)
     
     ref = -data1
-    config.writeVector(4, ref)
+    config.writeReference(4, ref)
     
     ref = data1 + 0.5
-    config.writeVector(5, ref)
+    config.writeReference(5, ref)
     
     ref = data1 * 0.5
-    config.writeVector(6, ref)
+    config.writeReference(6, ref)
     
     nb = 3
     ref = np.array([np.dot(data1[0:nb] ,data2[0:nb])])
-    config.writeVector(7, ref)
+    config.writeReference(7, ref)
     
     nb = 8
     ref = np.array([np.dot(data1[0:nb] ,data2[0:nb])])
-    config.writeVector(8, ref)
+    config.writeReference(8, ref)
     
     nb = 9
     ref = np.array([np.dot(data1[0:nb] ,data2[0:nb])])
-    config.writeVector(9, ref)
+    config.writeReference(9, ref)
     
     ref = abs(data1)
-    config.writeVector(10, ref)
+    config.writeReference(10, ref)
 
 
 PATTERNDIR = os.path.join("Patterns","DSP","BasicMaths","BasicMaths")
 PARAMDIR = os.path.join("Parameters","DSP","BasicMaths","BasicMaths")
 
-configf32=Config(PATTERNDIR,PARAMDIR,"f32")
-configq31=Config(PATTERNDIR,PARAMDIR,"q31")
-configq15=Config(PATTERNDIR,PARAMDIR,"q15")
-configq7=Config(PATTERNDIR,PARAMDIR,"q7")
+configf32=Tools.Config(PATTERNDIR,PARAMDIR,"f32")
+configq31=Tools.Config(PATTERNDIR,PARAMDIR,"q31")
+configq15=Tools.Config(PATTERNDIR,PARAMDIR,"q15")
+configq7=Tools.Config(PATTERNDIR,PARAMDIR,"q7")
 
 
 

Testing/PatternGeneration/SVM.py

@@ -0,0 +1,150 @@
+import os.path
+import itertools
+import Tools
+from sklearn import svm
+import random
+import numpy as np
+
+# Number of vectors to test for each test
+NBTESTSAMPLE = 100
+# Dimension of the vectors
+VECDIM = 10
+
+# Number of vectors for training
+NBVECTORS=10
+# Distance between the two centers (training vectors are gaussianly 
+# distributed around the centers)
+CENTER_DISTANCE = 1
+
+# SVM KIND
+LINEAR=1
+POLY=2
+RBF=3
+SIGMOID=4
+
+C0 = np.zeros((1,VECDIM))
+C1 = np.copy(C0)
+C1[0,0] = C1[0,0] + CENTER_DISTANCE
+
+# Data for training
+
+X = []
+Xone = []
+y = []
+
+class1 = 0 
+class2 = 1
+
+for i in range(NBVECTORS):
+    v = np.random.randn(1,VECDIM)
+    v = v * CENTER_DISTANCE/2.0/10 
+    # 2 classes are needed
+    if i == 0:
+        c = 0 
+    elif i == 1:
+        c = 1
+    else:
+        c = np.random.choice([0,1])
+    if (c == 0):
+        v = v + C0
+        y.append(class1)
+    else:
+        v = v + C1 
+        y.append(class2)
+    if c == 0:
+        Xone.append(v[0].tolist())
+    X.append(v[0].tolist())
+
+def newSVMTest(config,kind,theclass,clf,nb):
+    inputs = [] 
+    references = []
+    for i in range(NBTESTSAMPLE):
+            v = np.random.randn(1,VECDIM)
+            v = v * CENTER_DISTANCE/2.0/6.0 
+            c = np.random.choice([0,1])
+            if (c == 0):
+               v = v + C0 
+            else:
+               v = v + C1 
+            inputs.append(v[0].tolist())
+            toPredict=[v[0].tolist()]
+            references.append(clf.predict(toPredict))
+    inputs=np.array(inputs)
+    inputs=inputs.reshape(NBTESTSAMPLE*VECDIM)
+
+    config.writeInput(nb, inputs,"Samples")
+
+    references=np.array(references)
+    references=references.reshape(NBTESTSAMPLE)
+
+    # Classifier description
+    supportShape = clf.support_vectors_.shape
+
+    nbSupportVectors=supportShape[0]
+    vectorDimensions=supportShape[1]
+    intercept = np.array(clf.intercept_)
+    dualCoefs=clf.dual_coef_ 
+    dualCoefs=dualCoefs.reshape(nbSupportVectors)
+    supportVectors=clf.support_vectors_
+    supportVectors = supportVectors.reshape(nbSupportVectors*VECDIM)
+    
+    if kind == LINEAR:
+       dims=np.array([kind,theclass[0],theclass[1],NBTESTSAMPLE,VECDIM,nbSupportVectors])
+    elif kind==POLY:
+       dims=np.array([kind,theclass[0],theclass[1],NBTESTSAMPLE,VECDIM,nbSupportVectors,clf.degree])
+    elif kind==RBF:
+       dims=np.array([kind,theclass[0],theclass[1],NBTESTSAMPLE,VECDIM,nbSupportVectors])
+    elif kind==SIGMOID:
+       dims=np.array([kind,theclass[0],theclass[1],NBTESTSAMPLE,VECDIM,nbSupportVectors])
+    
+    config.writeInputS16(nb, dims,"Dims")
+
+    if kind == LINEAR:
+       params=np.concatenate((supportVectors,dualCoefs,intercept))
+    elif kind == POLY:
+       coef0 = np.array([clf.coef0])
+       gamma = np.array([clf._gamma])
+       params=np.concatenate((supportVectors,dualCoefs,intercept,coef0,gamma))
+    elif kind == RBF:
+       gamma = np.array([clf._gamma])
+       params=np.concatenate((supportVectors,dualCoefs,intercept,gamma))
+    elif kind == SIGMOID:
+       coef0 = np.array([clf.coef0])
+       gamma = np.array([clf._gamma])
+       params=np.concatenate((supportVectors,dualCoefs,intercept,coef0,gamma))
+
+    config.writeInput(nb, params,"Params")
+
+    config.writeReferenceS32(nb, references,"Reference")
+
+
+def writeTests(config):
+    clf = svm.SVC(kernel='linear')
+    clf.fit(X, y)
+    newSVMTest(config,LINEAR,[class1,class2],clf,1)
+
+    clf = svm.SVC(kernel='poly',gamma='auto', coef0=1.1)
+    clf.fit(X, y)
+    newSVMTest(config,POLY,[class1,class2],clf,2)
+
+    clf = svm.SVC(kernel='rbf',gamma='auto')
+    clf.fit(X, y)
+    newSVMTest(config,RBF,[class1,class2],clf,3)
+
+    clf = svm.SVC(kernel='sigmoid',gamma='auto')
+    clf.fit(X, y)
+    newSVMTest(config,SIGMOID,[class1,class2],clf,4)
+
+    clf = svm.OneClassSVM(nu=0.1, kernel="rbf", gamma=0.1)
+    clf.fit(X)
+    newSVMTest(config,RBF,[-1,1],clf,5)
+
+    
+
+
+PATTERNDIR = os.path.join("Patterns","DSP","SVM","SVM")
+PARAMDIR = os.path.join("Parameters","DSP","SVM","SVM")
+
+configf32=Tools.Config(PATTERNDIR,PARAMDIR,"f32")
+
+writeTests(configf32)

Testing/PatternGeneration/Tools.py

@@ -0,0 +1,356 @@
+import os.path
+import struct
+
+def createMissingDir(destPath):
+  theDir=os.path.normpath(destPath)
+  if not os.path.exists(theDir):
+      os.makedirs(theDir)
+
+def float_to_hex(f):
+    """ Convert and x86 float to an ARM unsigned long int.
+  
+    Args:
+      f (float): value to be converted
+    Raises:
+      Nothing 
+    Returns:
+      str : representation of the hex value
+    """
+    return hex(struct.unpack('<I', struct.pack('<f', f))[0])
+
+def to_q31(v):
+    r = int(round(v * 2**31))
+    if (r > 0x07FFFFFFF):
+      r = 0x07FFFFFFF
+    if (r < -0x080000000):
+      r = -0x080000000
+    return ("0x%s" % format(struct.unpack('<I', struct.pack('<i', r))[0],'08X'))
+
+def to_q15(v):
+    r = int(round(v * 2**15))
+    if (r > 0x07FFF):
+      r = 0x07FFF
+    if (r < -0x08000):
+      r = -0x08000
+    return ("0x%s" % format(struct.unpack('<H', struct.pack('<h', r))[0],'04X'))
+
+def to_q7(v):
+    r = int(round(v * 2**7))
+    if (r > 0x07F):
+      r = 0x07F
+    if (r < -0x080):
+      r = -0x080
+    return ("0x%s" % format(struct.unpack('<B', struct.pack('<b', r))[0],'02X'))
+
+def s16(r):
+  return ("0x%s" % format(struct.unpack('<H', struct.pack('<h', r))[0],'04X'))
+
+def s32(r):
+  return ("0x%s" % format(struct.unpack('<I', struct.pack('<i', r))[0],'08X'))
+
+class Config:
+    def __init__(self,patternDir,paramDir,ext):
+      self._patternDir = "%s%s" % (patternDir,ext.upper())
+      self._paramDir = "%s%s" % (paramDir,ext.upper())
+      self._ext = ext 
+
+      createMissingDir(self._patternDir)
+      createMissingDir(self._paramDir)
+
+    
+    def inputP(self,i,name=None):
+        """ Path to a reference pattern from the ID
+      
+        Args:
+          i (int): ID to the reference pattern
+        Raises:
+          Nothing 
+        Returns:
+          str : path to the file where to generate the pattern data
+        """
+        if name:
+          return(os.path.join(self._patternDir,"%s%d_%s.txt" % (name,i,self._ext)))
+        else:
+          return(os.path.join(self._patternDir,"Input%d_%s.txt" % (i,self._ext)))
+
+    def inputS16P(self,i,name=None):
+        """ Path to a reference pattern from the ID
+      
+        Args:
+          i (int): ID to the reference pattern
+        Raises:
+          Nothing 
+        Returns:
+          str : path to the file where to generate the pattern data
+        """
+        if name:
+          return(os.path.join(self._patternDir,"%s%d_%s.txt" % (name,i,"s16")))
+        else:
+          return(os.path.join(self._patternDir,"Input%d_%s.txt" % (i,"s16")))
+
+    def refP(self,i,name=None):
+        """ Path to a reference pattern from the ID
+      
+        Args:
+          i (int): ID to the reference pattern
+        Raises:
+          Nothing 
+        Returns:
+          str : path to the file where to generate the pattern data
+        """
+        if name:
+          return(os.path.join(self._patternDir,"%s%d_%s.txt" % (name,i,self._ext)))
+        else:
+          return(os.path.join(self._patternDir,"Reference%d_%s.txt" % (i,self._ext)))
+
+    def refS16P(self,i,name=None):
+        """ Path to a reference pattern from the ID
+      
+        Args:
+          i (int): ID to the reference pattern
+        Raises:
+          Nothing 
+        Returns:
+          str : path to the file where to generate the pattern data
+        """
+        if name:
+          return(os.path.join(self._patternDir,"%s%d_%s.txt" % (name,i,"s16")))
+        else:
+          return(os.path.join(self._patternDir,"Reference%d_%s.txt" % (i,"s16")))
+
+    def refS32P(self,i,name=None):
+        """ Path to a reference pattern from the ID
+      
+        Args:
+          i (int): ID to the reference pattern
+        Raises:
+          Nothing 
+        Returns:
+          str : path to the file where to generate the pattern data
+        """
+        if name:
+          return(os.path.join(self._patternDir,"%s%d_%s.txt" % (name,i,"s32")))
+        else:
+          return(os.path.join(self._patternDir,"Reference%d_%s.txt" % (i,"s32")))
+
+    def paramP(self,i,name=None):
+        """ Path to a parameters from the ID
+      
+        Args:
+          i (int): ID to the params
+        Raises:
+          Nothing 
+        Returns:
+          str : path to the file where to generate the pattern data
+        """
+        if name:
+          return(os.path.join(self._paramDir,"%s%d.txt" % (name,i)))
+        else:
+          return(os.path.join(self._paramDir,"Params%d.txt" % i))
+
+    def _writeVectorF32(self,i,data):
+        """ Write pattern data
+        
+        The format is recognized by the text framework script.
+        First line is the sample width (B,H or W for 8,16 or 32 bits)
+        Second line is number of samples
+        Other lines are hexadecimal representation of the samples in format
+        which can be read on big endian ARM.
+        
+          Args:
+            j (int): ID of pattern file
+            data (array): Vector containing the data
+          Raises:
+            Nothing 
+          Returns:
+            Nothing
+        """
+        with open(i,"w") as f:
+            # Write sample dimension nb sample header
+            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
+            f.write("W\n%d\n" % len(data))
+            for v in data:
+                f.write("// %f\n" % v)
+                f.write("%s\n" % float_to_hex(v))
+
+    def _writeVectorQ31(self,i,data):
+        """ Write pattern data
+        
+        The format is recognized by the text framework script.
+        First line is the sample width (B,H or W for 8,16 or 32 bits)
+        Second line is number of samples
+        Other lines are hexadecimal representation of the samples in format
+        which can be read on big endian ARM.
+        
+          Args:
+            j (int): ID of pattern file
+            data (array): Vector containing the data
+          Raises:
+            Nothing 
+          Returns:
+            Nothing
+        """
+        with open(i,"w") as f:
+            # Write sample dimension nb sample header
+            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
+            f.write("W\n%d\n" % len(data))
+            for v in data:
+                f.write("// %f\n" % v)
+                f.write("%s\n" % to_q31(v))
+
+    def _writeVectorQ15(self,i,data):
+        """ Write pattern data
+        
+        The format is recognized by the text framework script.
+        First line is the sample width (B,H or W for 8,16 or 32 bits)
+        Second line is number of samples
+        Other lines are hexadecimal representation of the samples in format
+        which can be read on big endian ARM.
+        
+          Args:
+            j (int): ID of pattern file
+            data (array): Vector containing the data
+          Raises:
+            Nothing 
+          Returns:
+            Nothing
+        """
+        with open(i,"w") as f:
+            # Write sample dimension nb sample header
+            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
+            f.write("H\n%d\n" % len(data))
+            for v in data:
+                f.write("// %f\n" % v)
+                f.write("%s\n" % to_q15(v))
+
+    def _writeVectorS16(self,i,data):
+        """ Write pattern data
+        
+        The format is recognized by the text framework script.
+        First line is the sample width (B,H or W for 8,16 or 32 bits)
+        Second line is number of samples
+        Other lines are hexadecimal representation of the samples in format
+        which can be read on big endian ARM.
+        
+          Args:
+            j (int): ID of pattern file
+            data (array): Vector containing the data
+          Raises:
+            Nothing 
+          Returns:
+            Nothing
+        """
+        with open(i,"w") as f:
+            # Write sample dimension nb sample header
+            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
+            f.write("H\n%d\n" % len(data))
+            for v in data:
+                f.write("// %d\n" % v)
+                f.write("%s\n" % s16(v))
+
+    def _writeVectorS32(self,i,data):
+        """ Write pattern data
+        
+        The format is recognized by the text framework script.
+        First line is the sample width (B,H or W for 8,16 or 32 bits)
+        Second line is number of samples
+        Other lines are hexadecimal representation of the samples in format
+        which can be read on big endian ARM.
+        
+          Args:
+            j (int): ID of pattern file
+            data (array): Vector containing the data
+          Raises:
+            Nothing 
+          Returns:
+            Nothing
+        """
+        with open(i,"w") as f:
+            # Write sample dimension nb sample header
+            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
+            f.write("W\n%d\n" % len(data))
+            for v in data:
+                f.write("// %d\n" % v)
+                f.write("%s\n" % s32(v))
+
+    def _writeVectorQ7(self,i,data):
+        """ Write pattern data
+        
+        The format is recognized by the text framework script.
+        First line is the sample width (B,H or W for 8,16 or 32 bits)
+        Second line is number of samples
+        Other lines are hexadecimal representation of the samples in format
+        which can be read on big endian ARM.
+        
+          Args:
+            j (int): ID of pattern file
+            data (array): Vector containing the data
+          Raises:
+            Nothing 
+          Returns:
+            Nothing
+        """
+        with open(i,"w") as f:
+            # Write sample dimension nb sample header
+            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
+            f.write("B\n%d\n" % len(data))
+            for v in data:
+                f.write("// %f\n" % v)
+                f.write("%s\n" % to_q7(v))
+
+    def writeReference(self,j,data,name=None):
+        if (self._ext == "f32"):
+          self._writeVectorF32(self.refP(j,name),data)
+        if (self._ext == "q31"):
+          self._writeVectorQ31(self.refP(j,name),data)
+        if (self._ext == "q15"):
+          self._writeVectorQ15(self.refP(j,name),data)
+        if (self._ext == "q7"):
+          self._writeVectorQ7(self.refP(j,name),data)
+
+    def writeReferenceS16(self,j,data,name=None):
+        self._writeVectorS16(self.refS16P(j,name),data)
+       
+    def writeReferenceS32(self,j,data,name=None):
+        self._writeVectorS32(self.refS32P(j,name),data)
+
+    def writeInput(self,j,data,name=None):
+        if (self._ext == "f32"):
+          self._writeVectorF32(self.inputP(j,name),data)
+        if (self._ext == "q31"):
+          self._writeVectorQ31(self.inputP(j,name),data)
+        if (self._ext == "q15"):
+          self._writeVectorQ15(self.inputP(j,name),data)
+        if (self._ext == "q7"):
+          self._writeVectorQ7(self.inputP(j,name),data)
+
+    def writeInputS16(self,j,data,name=None):
+        self._writeVectorS16(self.inputS16P(j,name),data)
+
+    def writeParam(self,j,data,name=None):
+        """ Write pattern data
+        
+        The format is recognized by the text framework script.
+        First line is the sample width (B,H or W for 8,16 or 32 bits)
+        Second line is number of samples
+        Other lines are hexadecimal representation of the samples in format
+        which can be read on big endian ARM.
+        
+          Args:
+            j (int): ID of parameter file
+            data (array): Vector containing the data
+          Raises:
+            Nothing 
+          Returns:
+            Nothing
+        """
+        i=self.paramP(j,name)
+        with open(i,"w") as f:
+            # Write sample dimension nb sample header
+            #np.savetxt(i, data, newline="\n", header="W\n%d" % len(data),comments ="" )
+            f.write("%d\n" % len(data))
+            for v in data:
+                f.write("%d\n" % v)
+
+
+

Testing/Patterns/DSP/BasicMaths/BasicMathsF32/Reference7_f32.txt

@@ -1,4 +1,4 @@
 W
 1
-// 0.122055
-0x3df9f827
+// 0.114859
+0x3deb3b4b