|
|
|
|
@ -61,7 +61,9 @@ static uint32_t startCycles=0;
|
|
|
|
|
#endif /* CORTEXM*/
|
|
|
|
|
|
|
|
|
|
#if defined(CORTEXA) || defined(CORTEXR)
|
|
|
|
|
#if !defined(__GNUC_PYTHON__)
|
|
|
|
|
#include "cmsis_cp15.h"
|
|
|
|
|
#endif
|
|
|
|
|
unsigned int startCycles;
|
|
|
|
|
|
|
|
|
|
#define DO_RESET 1
|
|
|
|
|
@ -84,7 +86,9 @@ void initCycleMeasurement()
|
|
|
|
|
#if defined(CORTEXA) || defined(CORTEXR)
|
|
|
|
|
|
|
|
|
|
// in general enable all counters (including cycle counter)
|
|
|
|
|
#if !defined(__GNUC_PYTHON__)
|
|
|
|
|
int32_t value = 1;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// peform reset:
|
|
|
|
|
if (DO_RESET)
|
|
|
|
|
@ -95,9 +99,10 @@ void initCycleMeasurement()
|
|
|
|
|
|
|
|
|
|
if (ENABLE_DIVIDER)
|
|
|
|
|
value |= 8; // enable "by 64" divider for CCNT.
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
//value |= 16;
|
|
|
|
|
|
|
|
|
|
#if !defined(__GNUC_PYTHON__)
|
|
|
|
|
// program the performance-counter control-register:
|
|
|
|
|
__set_CP(15, 0, value, 9, 12, 0);
|
|
|
|
|
|
|
|
|
|
@ -114,6 +119,7 @@ void initCycleMeasurement()
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void cycleMeasurementStart()
|
|
|
|
|
@ -137,7 +143,7 @@ void cycleMeasurementStart()
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CORTEXA) || defined(CORTEXR)
|
|
|
|
|
#if (defined(CORTEXA) || defined(CORTEXR)) && !defined(__GNUC_PYTHON__)
|
|
|
|
|
unsigned int value;
|
|
|
|
|
// Read CCNT Register
|
|
|
|
|
__get_CP(15, 0, value, 9, 13, 0);
|
|
|
|
|
@ -187,11 +193,14 @@ return(0);
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CORTEXA) || defined(CORTEXR)
|
|
|
|
|
#if (defined(CORTEXA) || defined(CORTEXR)) && !defined(__GNUC_PYTHON__)
|
|
|
|
|
unsigned int value;
|
|
|
|
|
// Read CCNT Register
|
|
|
|
|
__get_CP(15, 0, value, 9, 13, 0);
|
|
|
|
|
return(value - startCycles);
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
#if defined(__GNUC_PYTHON__)
|
|
|
|
|
return(0);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|