Corrected small issues when building for aarch64.

pull/42/head
Christophe Favergeon 3 years ago
parent b416800e17
commit 305b12c4a7

@ -54,7 +54,7 @@ void arm_accumulate_f64(
uint32_t blkCnt; /* Loop counter */
/*Neon buffers*/
float64x2_t vSum = vdupq_n_f64(0.0f);
float64x2_t vSum = vdupq_n_f64(0.0);
float64x2_t afterLoad ;
float64_t sum = 0.; /* Temporary result storage */

@ -165,7 +165,7 @@ void arm_max_f32(
uint32x4_t countV;
uint32x2_t countV2;
maxIdx = vdupq_n_u32(ULONG_MAX);
maxIdx = vdupq_n_u32(UINT_MAX);
delta = vdupq_n_u32(4);
index = vld1q_u32(indexInit);
countV = vld1q_u32(countVInit);

@ -166,7 +166,7 @@ void arm_min_f32(
uint32x4_t countV;
uint32x2_t countV2;
maxIdx = vdupq_n_u32(ULONG_MAX);
maxIdx = vdupq_n_u32(UINT_MAX);
delta = vdupq_n_u32(4);
index = vld1q_u32(indexInit);
countV = vld1q_u32(countVInit);

@ -89,7 +89,11 @@ void assert_near_equal(unsigned long nb,q63_t pa, q63_t pb, q63_t threshold)
if (abs(pa - pb) > threshold)
{
char details[200];
#if __sizeof_long == 8
sprintf(details,"diff %ld > %ld (0x%016lX,0x%016lX)",abs(pa - pb) , threshold,pa,pb);
#else
sprintf(details,"diff %lld > %lld (0x%016llX,0x%016llX)",abs(pa - pb) , threshold,pa,pb);
#endif
throw (Error(EQUAL_ERROR,nb,details));
}
};

@ -737,7 +737,11 @@ namespace Client
{
v = data[i];
t = TOINT64(v);
#if __sizeof_long == 8
printf("D: 0x%016lx\n",t);
#else
printf("D: 0x%016llx\n",t);
#endif
}
printf("D: END\n");
}
@ -796,7 +800,11 @@ namespace Client
{
v = data[i];
t = (uint64_t)v;
#if __sizeof_long == 8
printf("D: 0x%016lx\n",t);
#else
printf("D: 0x%016llx\n",t);
#endif
}
printf("D: END\n");
}
@ -872,7 +880,11 @@ namespace Client
{
v = data[i];
t = (uint64_t)v;
#if __sizeof_long == 8
printf("D: 0x%016lx\n",t);
#else
printf("D: 0x%016llx\n",t);
#endif
}
printf("D: END\n");
}

@ -108,7 +108,7 @@ So to ensure the conditions are always the same, the instruction cache
and branch predictor are flushed.
*/
#ifdef CORTEXA
#if defined(CORTEXA) && !defined(__GNUC_PYTHON__)
__set_BPIALL(0);
__DSB();
__ISB();
@ -269,7 +269,7 @@ fast models.
// Run the test once to force the code to be in cache.
// By default it is disabled in the suite.
#ifdef CORTEXA
#if defined(CORTEXA) && !defined(__GNUC_PYTHON__)
__set_BPIALL(0);
__DSB();
__ISB();

@ -61,7 +61,9 @@ static uint32_t startCycles=0;
#endif /* CORTEXM*/
#if defined(CORTEXA) || defined(CORTEXR)
#if !defined(__GNUC_PYTHON__)
#include "cmsis_cp15.h"
#endif
unsigned int startCycles;
#define DO_RESET 1
@ -84,8 +86,10 @@ void initCycleMeasurement()
#if defined(CORTEXA) || defined(CORTEXR)
// in general enable all counters (including cycle counter)
#if !defined(__GNUC_PYTHON__)
int32_t value = 1;
// peform reset:
if (DO_RESET)
{
@ -95,9 +99,10 @@ void initCycleMeasurement()
if (ENABLE_DIVIDER)
value |= 8; // enable "by 64" divider for CCNT.
#endif
//value |= 16;
#if !defined(__GNUC_PYTHON__)
// program the performance-counter control-register:
__set_CP(15, 0, value, 9, 12, 0);
@ -114,6 +119,7 @@ void initCycleMeasurement()
#endif
#endif
#endif
#endif
}
void cycleMeasurementStart()
@ -137,7 +143,7 @@ void cycleMeasurementStart()
#endif
#if defined(CORTEXA) || defined(CORTEXR)
#if (defined(CORTEXA) || defined(CORTEXR)) && !defined(__GNUC_PYTHON__)
unsigned int value;
// Read CCNT Register
__get_CP(15, 0, value, 9, 13, 0);
@ -187,11 +193,14 @@ return(0);
#endif
#endif
#if defined(CORTEXA) || defined(CORTEXR)
#if (defined(CORTEXA) || defined(CORTEXR)) && !defined(__GNUC_PYTHON__)
unsigned int value;
// Read CCNT Register
__get_CP(15, 0, value, 9, 13, 0);
return(value - startCycles);
#endif
#endif
#if defined(__GNUC_PYTHON__)
return(0);
#endif
}

@ -4,7 +4,7 @@
#include "Test.h"
#define SNR_THRESHOLD 305
#define SNR_THRESHOLD 303
/*
Reference patterns are generated with

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