Added support for A5, A7 and A9 to test framework with cmsis build tools.
AC6 only. There are still some limitations with gcc.pull/32/head
Christophe Favergeon
4 years ago
parent
65cf6252ca
commit
ae24b870e7
@ -0,0 +1,181 @@
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#include "mem_ARMCA5.h"
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MEMORY
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{
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ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
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L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE
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RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
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}
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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Image$$VECTORS$$Base = .;
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* (RESET)
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KEEP(*(.isr_vector))
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Image$$VECTORS$$Limit = .;
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*(SVC_TABLE)
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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Image$$RO_DATA$$Base = .;
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*(.rodata*)
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Image$$RO_DATA$$Limit = .;
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KEEP(*(.eh_frame*))
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} > ROM
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > ROM
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > ROM
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__exidx_end = .;
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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__copy_table_end__ = .;
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} > ROM
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG (__bss_end__ - __bss_start__)
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__zero_table_end__ = .;
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} > ROM
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__etext = .;
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.ttb :
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{
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Image$$TTB$$ZI$$Base = .;
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. += __TTB_SIZE;
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Image$$TTB$$ZI$$Limit = .;
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} > L_TTB
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.data : AT (__etext)
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{
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Image$$RW_DATA$$Base = .;
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__data_start__ = .;
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*(vtable)
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*(.data*)
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Image$$RW_DATA$$Limit = .;
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. = ALIGN(4);
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/* preinit data */
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PROVIDE (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE (__fini_array_end = .);
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > RAM
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.bss ALIGN(0x400):
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{
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Image$$ZI_DATA$$Base = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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__bss_end__ = .;
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Image$$ZI_DATA$$Limit = .;
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__end__ = .;
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end = __end__;
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} > RAM
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#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
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.heap (NOLOAD):
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{
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. = ALIGN(8);
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Image$$HEAP$$ZI$$Base = .;
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. += __HEAP_SIZE;
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Image$$HEAP$$ZI$$Limit = .;
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__HeapLimit = .;
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} > RAM
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#endif
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.stack (NOLOAD):
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{
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. = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
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. = ALIGN(8);
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__StackTop = .;
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Image$$SYS_STACK$$ZI$$Base = .;
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. += __STACK_SIZE;
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Image$$SYS_STACK$$ZI$$Limit = .;
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__stack = .;
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Image$$FIQ_STACK$$ZI$$Base = .;
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. += __FIQ_STACK_SIZE;
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Image$$FIQ_STACK$$ZI$$Limit = .;
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Image$$IRQ_STACK$$ZI$$Base = .;
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. += __IRQ_STACK_SIZE;
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Image$$IRQ_STACK$$ZI$$Limit = .;
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Image$$SVC_STACK$$ZI$$Base = .;
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. += __SVC_STACK_SIZE;
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Image$$SVC_STACK$$ZI$$Limit = .;
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Image$$ABT_STACK$$ZI$$Base = .;
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. += __ABT_STACK_SIZE;
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Image$$ABT_STACK$$ZI$$Limit = .;
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Image$$UND_STACK$$ZI$$Base = .;
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. += __UND_STACK_SIZE;
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Image$$UND_STACK$$ZI$$Limit = .;
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} > RAM
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}
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@ -0,0 +1,77 @@
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc
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;**************************************************
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; Copyright (c) 2017 ARM Ltd. All rights reserved.
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;**************************************************
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; Scatter-file for RTX Example on Versatile Express
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; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
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; This platform has 2GB SDRAM starting at 0x80000000.
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#include "mem_ARMCA5.h"
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SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
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{
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VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
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{
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* (RESET, +FIRST) ; Vector table and other startup code
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* (InRoot$$Sections) ; All (library) code that must be in a root region
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* (+RO-CODE) ; Application RO code (.text)
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* (+RO-DATA) ; Application RO data (.constdata)
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}
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RW_DATA __RAM_BASE __RW_DATA_SIZE
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{ * (+RW) } ; Application RW data (.data)
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ZI_DATA (__RAM_BASE+
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__RW_DATA_SIZE) __ZI_DATA_SIZE
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{ * (+ZI) } ; Application ZI data (.bss)
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ARM_LIB_HEAP (__RAM_BASE
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+__RW_DATA_SIZE
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+__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
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{ }
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ARM_LIB_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE
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-__IRQ_STACK_SIZE
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-__SVC_STACK_SIZE
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-__ABT_STACK_SIZE
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-__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
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{ }
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UND_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE
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-__IRQ_STACK_SIZE
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-__SVC_STACK_SIZE
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-__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
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{ }
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ABT_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE
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-__IRQ_STACK_SIZE
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-__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
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{ }
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SVC_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE
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-__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
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{ }
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IRQ_STACK (__RAM_BASE
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+__RAM_SIZE
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-__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
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{ }
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FIQ_STACK (__RAM_BASE
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+__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
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{ }
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TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
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{ }
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}
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@ -0,0 +1,100 @@
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/**************************************************************************//**
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* @file mem_ARMCA5.h
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* @brief Memory base and size definitions (used in scatter file)
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* @version V1.1.0
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* @date 15. May 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __MEM_ARMCA5_H
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#define __MEM_ARMCA5_H
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/*----------------------------------------------------------------------------
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User Stack & Heap size definition
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*----------------------------------------------------------------------------*/
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- ROM Configuration ------------------------------------
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//
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// <h> ROM Configuration
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// <i> For compatibility with MMU config the sections must be multiple of 1MB
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// <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
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// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __ROM_BASE 0x80000000
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#define __ROM_SIZE 0x00200000
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/*--------------------- RAM Configuration -----------------------------------
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// <h> RAM Configuration
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// <i> For compatibility with MMU config the sections must be multiple of 1MB
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// <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000>
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// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
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// <h> Data Sections
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// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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// <h> Stack / Heap Configuration
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// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <h> Exceptional Modes
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// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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// </h>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __RAM_BASE 0x80200000
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#define __RAM_SIZE 0x00300000
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#define __RW_DATA_SIZE 0x00100000
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#define __ZI_DATA_SIZE 0x000F0000
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#define __STACK_SIZE 0x00002000
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#define __HEAP_SIZE 0x00100000
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#define __UND_STACK_SIZE 0x00000100
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#define __ABT_STACK_SIZE 0x00000100
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#define __SVC_STACK_SIZE 0x00000100
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#define __IRQ_STACK_SIZE 0x00000100
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#define __FIQ_STACK_SIZE 0x00000100
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/*----------------------------------------------------------------------------*/
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/*--------------------- TTB Configuration ------------------------------------
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//
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// <h> TTB Configuration
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// <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
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// <i> The TLB L2 entries are placed after the L1 in the MMU config
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// <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
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// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __TTB_BASE 0x80500000
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#define __TTB_SIZE 0x00005000
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#endif /* __MEM_ARMCA5_H */
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@ -0,0 +1,232 @@
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/**************************************************************************//**
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* @file mmu_ARMCA5.c
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* @brief MMU Configuration for ARM Cortex-A5 Device Series
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* @version V1.2.0
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* @date 15. May 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
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Memory Type
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0xffffffff |--------------------------| ------------
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| FLAG SYNC | Device Memory
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0xfffff000 |--------------------------| ------------
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| Fault | Fault
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0xfff00000 |--------------------------| ------------
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| | Normal
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| |
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| Daughterboard |
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| memory |
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| |
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0x80505000 |--------------------------| ------------
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|TTB (L2 Sync Flags ) 4k | Normal
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0x80504C00 |--------------------------| ------------
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|TTB (L2 Peripherals-B) 16k| Normal
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0x80504800 |--------------------------| ------------
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|TTB (L2 Peripherals-A) 16k| Normal
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0x80504400 |--------------------------| ------------
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|TTB (L2 Priv Periphs) 4k | Normal
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0x80504000 |--------------------------| ------------
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| TTB (L1 Descriptors) | Normal
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0x80500000 |--------------------------| ------------
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| Stack | Normal
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|--------------------------| ------------
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| Heap | Normal
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0x80400000 |--------------------------| ------------
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| ZI Data | Normal
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0x80300000 |--------------------------| ------------
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| RW Data | Normal
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0x80200000 |--------------------------| ------------
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| RO Data | Normal
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|--------------------------| ------------
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| RO Code | USH Normal
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0x80000000 |--------------------------| ------------
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| Daughterboard | Fault
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| HSB AXI buses |
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0x40000000 |--------------------------| ------------
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| Daughterboard | Fault
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| test chips peripherals |
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0x2c002000 |--------------------------| ------------
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| Private Address | Device Memory
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0x2c000000 |--------------------------| ------------
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| Daughterboard | Fault
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| test chips peripherals |
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0x20000000 |--------------------------| ------------
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| Peripherals | Device Memory RW/RO
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| | & Fault
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0x00000000 |--------------------------|
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*/
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// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
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// Write-Through support *not* available
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// Write-Back support available.
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// Read allocation support available.
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// Write allocation support available.
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//Note: You should use the Shareable attribute carefully.
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//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
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//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
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//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
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//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
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//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
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//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
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//Following MMU configuration is expected
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//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
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//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
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//Domain 0 is always the Client domain
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//Descriptors should place all memory in domain 0
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#include "ARMCA5.h"
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#include "mem_ARMCA5.h"
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// TTB base address
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#define TTB_BASE ((uint32_t*)__TTB_BASE)
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// L2 table pointers
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//----------------------------------------
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#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
|
||||
// into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
|
||||
// The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
|
||||
|
||||
#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
|
||||
#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
|
||||
#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
|
||||
#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
|
||||
|
||||
//--------------------- PERIPHERALS -------------------
|
||||
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
|
||||
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
|
||||
|
||||
//--------------------- SYNC FLAGS --------------------
|
||||
#define FLAG_SYNC 0xFFFFF000
|
||||
#define F_SYNC_BASE 0xFFF00000 //1M aligned
|
||||
|
||||
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
|
||||
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
|
||||
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
|
||||
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
|
||||
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
|
||||
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
|
||||
|
||||
/* Define global descriptors */
|
||||
static uint32_t Page_L1_4k = 0x0; //generic
|
||||
static uint32_t Page_L1_64k = 0x0; //generic
|
||||
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
|
||||
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
|
||||
|
||||
void MMU_CreateTranslationTable(void)
|
||||
{
|
||||
mmu_region_attributes_Type region;
|
||||
|
||||
//Create 4GB of faulting entries
|
||||
MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
|
||||
|
||||
/*
|
||||
* Generate descriptors. Refer to core_ca.h to get information about attributes
|
||||
*
|
||||
*/
|
||||
//Create descriptors for Vectors, RO, RW, ZI sections
|
||||
section_normal(Sect_Normal, region);
|
||||
section_normal_cod(Sect_Normal_Cod, region);
|
||||
section_normal_ro(Sect_Normal_RO, region);
|
||||
section_normal_rw(Sect_Normal_RW, region);
|
||||
//Create descriptors for peripherals
|
||||
section_device_ro(Sect_Device_RO, region);
|
||||
section_device_rw(Sect_Device_RW, region);
|
||||
//Create descriptors for 64k pages
|
||||
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
|
||||
//Create descriptors for 4k pages
|
||||
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
|
||||
|
||||
|
||||
/*
|
||||
* Define MMU flat-map regions and attributes
|
||||
*
|
||||
*/
|
||||
|
||||
//Define Image
|
||||
MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
|
||||
MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
|
||||
|
||||
//--------------------- PERIPHERALS -------------------
|
||||
MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR
|
||||
MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR
|
||||
MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
|
||||
MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
|
||||
MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);
|
||||
MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE , 16, Sect_Device_RW);
|
||||
|
||||
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
|
||||
MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
|
||||
// Define peripheral range 0x1C000000-0x1C00FFFF
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
|
||||
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
|
||||
MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
|
||||
// Define peripheral range 0x1C100000-0x1C10FFFF
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
|
||||
// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
|
||||
MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
|
||||
// Define private address space entry.
|
||||
MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
// Define L2CC entry. Uncomment if PL310 is present
|
||||
// MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
|
||||
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
|
||||
MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
|
||||
// Define synchronization space entry.
|
||||
MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
|
||||
/* Set location of level 1 page table
|
||||
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
|
||||
; 13:7 - 0x0
|
||||
; 6 - IRGN[0] 0x1 (Inner WB WA)
|
||||
; 5 - NOS 0x0 (Non-shared)
|
||||
; 4:3 - RGN 0x01 (Outer WB WA)
|
||||
; 2 - IMP 0x0 (Implementation Defined)
|
||||
; 1 - S 0x0 (Non-shared)
|
||||
; 0 - IRGN[1] 0x0 (Inner WB WA) */
|
||||
__set_TTBR0(__TTB_BASE | 0x48);
|
||||
__ISB();
|
||||
|
||||
/* Set up domain access control register
|
||||
; We set domain 0 to Client and all other domains to No Access.
|
||||
; All translation table entries specify domain 0 */
|
||||
__set_DACR(1);
|
||||
__ISB();
|
||||
}
|
||||
@ -0,0 +1,136 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCA5.c
|
||||
* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <ARMCA5.h>
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define USR_MODE 0x10 // User mode
|
||||
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
|
||||
#define IRQ_MODE 0x12 // Interrupt Request mode
|
||||
#define SVC_MODE 0x13 // Supervisor mode
|
||||
#define ABT_MODE 0x17 // Abort mode
|
||||
#define UND_MODE 0x1B // Undefined Instruction mode
|
||||
#define SYS_MODE 0x1F // System mode
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Vectors (void) __attribute__ ((naked, section("RESET")));
|
||||
void Reset_Handler (void) __attribute__ ((naked));
|
||||
void Default_Handler(void) __attribute__ ((noreturn));
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector Table
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Vectors(void) {
|
||||
__ASM volatile(
|
||||
"LDR PC, =Reset_Handler \n"
|
||||
"LDR PC, =Undef_Handler \n"
|
||||
"LDR PC, =SVC_Handler \n"
|
||||
"LDR PC, =PAbt_Handler \n"
|
||||
"LDR PC, =DAbt_Handler \n"
|
||||
"NOP \n"
|
||||
"LDR PC, =IRQ_Handler \n"
|
||||
"LDR PC, =FIQ_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void) {
|
||||
__ASM volatile(
|
||||
|
||||
// Mask interrupts
|
||||
"CPSID if \n"
|
||||
|
||||
// Put any cores other than 0 to sleep
|
||||
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
|
||||
"ANDS R0, R0, #3 \n"
|
||||
"goToSleep: \n"
|
||||
"WFINE \n"
|
||||
"BNE goToSleep \n"
|
||||
|
||||
// Reset SCTLR Settings
|
||||
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
|
||||
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
|
||||
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
|
||||
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
|
||||
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
|
||||
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
|
||||
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
|
||||
"ISB \n"
|
||||
|
||||
// Configure ACTLR
|
||||
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
|
||||
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
|
||||
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
|
||||
|
||||
// Set Vector Base Address Register (VBAR) to point to this application's vector table
|
||||
"LDR R0, =Vectors \n"
|
||||
"MCR p15, 0, R0, c12, c0, 0 \n"
|
||||
|
||||
// Setup Stack for each exceptional mode
|
||||
"CPS #0x11 \n"
|
||||
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x12 \n"
|
||||
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x13 \n"
|
||||
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x17 \n"
|
||||
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x1B \n"
|
||||
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x1F \n"
|
||||
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
|
||||
|
||||
// Call SystemInit
|
||||
"BL SystemInit \n"
|
||||
|
||||
// Unmask interrupts
|
||||
"CPSIE if \n"
|
||||
|
||||
// Call __main
|
||||
"BL __main \n"
|
||||
);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void) {
|
||||
while(1);
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
/******************************************************************************
|
||||
* @file system_ARMCA5.c
|
||||
* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
|
||||
* @version V1.0.1
|
||||
* @date 13. February 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "irq_ctrl.h"
|
||||
|
||||
#define SYSTEM_CLOCK 12000000U
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Initialization
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* do not use global variables because this function is called before
|
||||
reaching pre-main. RW section may be overwritten afterwards. */
|
||||
|
||||
// Invalidate entire Unified TLB
|
||||
__set_TLBIALL(0);
|
||||
|
||||
// Invalidate entire branch predictor array
|
||||
__set_BPIALL(0);
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
// Invalidate instruction cache and flush branch target cache
|
||||
__set_ICIALLU(0);
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
// Invalidate data cache
|
||||
L1C_InvalidateDCacheAll();
|
||||
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
// Enable FPU
|
||||
__FPU_Enable();
|
||||
#endif
|
||||
|
||||
// Create Translation Table
|
||||
MMU_CreateTranslationTable();
|
||||
|
||||
// Enable MMU
|
||||
MMU_Enable();
|
||||
|
||||
// Enable Caches
|
||||
L1C_EnableCaches();
|
||||
L1C_EnableBTAC();
|
||||
|
||||
#if (__L2C_PRESENT == 1)
|
||||
// Enable GIC
|
||||
L2C_Enable();
|
||||
#endif
|
||||
|
||||
// IRQ Initialize
|
||||
IRQ_Initialize();
|
||||
}
|
||||
@ -0,0 +1,65 @@
|
||||
/******************************************************************************
|
||||
* @file system_ARMCA5.h
|
||||
* @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
|
||||
* @version V1.00
|
||||
* @date 10. January 2018
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_ARMCA5_H
|
||||
#define __SYSTEM_ARMCA5_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
\brief Setup the microcontroller system.
|
||||
|
||||
Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Update SystemCoreClock variable.
|
||||
|
||||
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
/**
|
||||
\brief Create Translation Table.
|
||||
|
||||
Creates Memory Management Unit Translation Table.
|
||||
*/
|
||||
extern void MMU_CreateTranslationTable(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_ARMCA5_H */
|
||||
@ -0,0 +1,181 @@
|
||||
#include "mem_ARMCA7.h"
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
|
||||
L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE
|
||||
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
|
||||
Image$$VECTORS$$Base = .;
|
||||
* (RESET)
|
||||
KEEP(*(.isr_vector))
|
||||
Image$$VECTORS$$Limit = .;
|
||||
|
||||
*(SVC_TABLE)
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
Image$$RO_DATA$$Base = .;
|
||||
*(.rodata*)
|
||||
Image$$RO_DATA$$Limit = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > ROM
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > ROM
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ROM
|
||||
__exidx_end = .;
|
||||
|
||||
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > ROM
|
||||
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > ROM
|
||||
|
||||
__etext = .;
|
||||
|
||||
.ttb :
|
||||
{
|
||||
Image$$TTB$$ZI$$Base = .;
|
||||
. += __TTB_SIZE;
|
||||
Image$$TTB$$ZI$$Limit = .;
|
||||
} > L_TTB
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
Image$$RW_DATA$$Base = .;
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
Image$$RW_DATA$$Limit = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
|
||||
.bss ALIGN(0x400):
|
||||
{
|
||||
Image$$ZI_DATA$$Base = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
Image$$ZI_DATA$$Limit = .;
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
} > RAM
|
||||
|
||||
#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
Image$$HEAP$$ZI$$Base = .;
|
||||
. += __HEAP_SIZE;
|
||||
Image$$HEAP$$ZI$$Limit = .;
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
#endif
|
||||
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
|
||||
__StackTop = .;
|
||||
Image$$SYS_STACK$$ZI$$Base = .;
|
||||
. += __STACK_SIZE;
|
||||
Image$$SYS_STACK$$ZI$$Limit = .;
|
||||
__stack = .;
|
||||
|
||||
Image$$FIQ_STACK$$ZI$$Base = .;
|
||||
. += __FIQ_STACK_SIZE;
|
||||
Image$$FIQ_STACK$$ZI$$Limit = .;
|
||||
|
||||
Image$$IRQ_STACK$$ZI$$Base = .;
|
||||
. += __IRQ_STACK_SIZE;
|
||||
Image$$IRQ_STACK$$ZI$$Limit = .;
|
||||
|
||||
Image$$SVC_STACK$$ZI$$Base = .;
|
||||
. += __SVC_STACK_SIZE;
|
||||
Image$$SVC_STACK$$ZI$$Limit = .;
|
||||
|
||||
Image$$ABT_STACK$$ZI$$Base = .;
|
||||
. += __ABT_STACK_SIZE;
|
||||
Image$$ABT_STACK$$ZI$$Limit = .;
|
||||
|
||||
Image$$UND_STACK$$ZI$$Base = .;
|
||||
. += __UND_STACK_SIZE;
|
||||
Image$$UND_STACK$$ZI$$Limit = .;
|
||||
|
||||
} > RAM
|
||||
}
|
||||
@ -0,0 +1,77 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc
|
||||
;**************************************************
|
||||
; Copyright (c) 2017 ARM Ltd. All rights reserved.
|
||||
;**************************************************
|
||||
|
||||
; Scatter-file for RTX Example on Versatile Express
|
||||
|
||||
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
|
||||
|
||||
; This platform has 2GB SDRAM starting at 0x80000000.
|
||||
|
||||
#include "mem_ARMCA7.h"
|
||||
|
||||
SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
|
||||
{
|
||||
VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
|
||||
{
|
||||
* (RESET, +FIRST) ; Vector table and other startup code
|
||||
* (InRoot$$Sections) ; All (library) code that must be in a root region
|
||||
* (+RO-CODE) ; Application RO code (.text)
|
||||
* (+RO-DATA) ; Application RO data (.constdata)
|
||||
}
|
||||
|
||||
RW_DATA __RAM_BASE __RW_DATA_SIZE
|
||||
{ * (+RW) } ; Application RW data (.data)
|
||||
|
||||
ZI_DATA (__RAM_BASE+
|
||||
__RW_DATA_SIZE) __ZI_DATA_SIZE
|
||||
{ * (+ZI) } ; Application ZI data (.bss)
|
||||
|
||||
ARM_LIB_HEAP (__RAM_BASE
|
||||
+__RW_DATA_SIZE
|
||||
+__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
|
||||
{ }
|
||||
|
||||
ARM_LIB_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE
|
||||
-__IRQ_STACK_SIZE
|
||||
-__SVC_STACK_SIZE
|
||||
-__ABT_STACK_SIZE
|
||||
-__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
|
||||
{ }
|
||||
|
||||
UND_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE
|
||||
-__IRQ_STACK_SIZE
|
||||
-__SVC_STACK_SIZE
|
||||
-__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
|
||||
{ }
|
||||
|
||||
ABT_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE
|
||||
-__IRQ_STACK_SIZE
|
||||
-__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
|
||||
{ }
|
||||
|
||||
SVC_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE
|
||||
-__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
|
||||
{ }
|
||||
|
||||
IRQ_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
|
||||
{ }
|
||||
|
||||
FIQ_STACK (__RAM_BASE
|
||||
+__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
|
||||
{ }
|
||||
|
||||
TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
|
||||
{ }
|
||||
}
|
||||
@ -0,0 +1,100 @@
|
||||
/**************************************************************************//**
|
||||
* @file mem_ARMCA7.h
|
||||
* @brief Memory base and size definitions (used in scatter file)
|
||||
* @version V1.1.0
|
||||
* @date 15. May 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __MEM_ARMCA7_H
|
||||
#define __MEM_ARMCA7_H
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
User Stack & Heap size definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- ROM Configuration ------------------------------------
|
||||
//
|
||||
// <h> ROM Configuration
|
||||
// <i> For compatibility with MMU config the sections must be multiple of 1MB
|
||||
// <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
|
||||
// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
|
||||
// </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __ROM_BASE 0x80000000
|
||||
#define __ROM_SIZE 0x00200000
|
||||
|
||||
/*--------------------- RAM Configuration -----------------------------------
|
||||
// <h> RAM Configuration
|
||||
// <i> For compatibility with MMU config the sections must be multiple of 1MB
|
||||
// <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000>
|
||||
// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
|
||||
// <h> Data Sections
|
||||
// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
// <h> Stack / Heap Configuration
|
||||
// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <h> Exceptional Modes
|
||||
// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_BASE 0x80200000
|
||||
#define __RAM_SIZE 0x00300000
|
||||
|
||||
#define __RW_DATA_SIZE 0x00100000
|
||||
#define __ZI_DATA_SIZE 0x000F0000
|
||||
|
||||
#define __STACK_SIZE 0x00002000
|
||||
#define __HEAP_SIZE 0x00100000
|
||||
|
||||
#define __UND_STACK_SIZE 0x00000100
|
||||
#define __ABT_STACK_SIZE 0x00000100
|
||||
#define __SVC_STACK_SIZE 0x00000100
|
||||
#define __IRQ_STACK_SIZE 0x00000100
|
||||
#define __FIQ_STACK_SIZE 0x00000100
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/*--------------------- TTB Configuration ------------------------------------
|
||||
//
|
||||
// <h> TTB Configuration
|
||||
// <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
|
||||
// <i> The TLB L2 entries are placed after the L1 in the MMU config
|
||||
// <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
|
||||
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __TTB_BASE 0x80500000
|
||||
#define __TTB_SIZE 0x00005000
|
||||
|
||||
#endif /* __MEM_ARMCA7_H */
|
||||
@ -0,0 +1,232 @@
|
||||
/**************************************************************************//**
|
||||
* @file mmu_ARMCA7.c
|
||||
* @brief MMU Configuration for Arm Cortex-A7 Device Series
|
||||
* @version V1.2.0
|
||||
* @date 15. May 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
|
||||
|
||||
Memory Type
|
||||
0xffffffff |--------------------------| ------------
|
||||
| FLAG SYNC | Device Memory
|
||||
0xfffff000 |--------------------------| ------------
|
||||
| Fault | Fault
|
||||
0xfff00000 |--------------------------| ------------
|
||||
| | Normal
|
||||
| |
|
||||
| Daughterboard |
|
||||
| memory |
|
||||
| |
|
||||
0x80505000 |--------------------------| ------------
|
||||
|TTB (L2 Sync Flags ) 4k | Normal
|
||||
0x80504C00 |--------------------------| ------------
|
||||
|TTB (L2 Peripherals-B) 16k| Normal
|
||||
0x80504800 |--------------------------| ------------
|
||||
|TTB (L2 Peripherals-A) 16k| Normal
|
||||
0x80504400 |--------------------------| ------------
|
||||
|TTB (L2 Priv Periphs) 4k | Normal
|
||||
0x80504000 |--------------------------| ------------
|
||||
| TTB (L1 Descriptors) | Normal
|
||||
0x80500000 |--------------------------| ------------
|
||||
| Stack | Normal
|
||||
|--------------------------| ------------
|
||||
| Heap | Normal
|
||||
0x80400000 |--------------------------| ------------
|
||||
| ZI Data | Normal
|
||||
0x80300000 |--------------------------| ------------
|
||||
| RW Data | Normal
|
||||
0x80200000 |--------------------------| ------------
|
||||
| RO Data | Normal
|
||||
|--------------------------| ------------
|
||||
| RO Code | USH Normal
|
||||
0x80000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| HSB AXI buses |
|
||||
0x40000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| test chips peripherals |
|
||||
0x2c002000 |--------------------------| ------------
|
||||
| Private Address | Device Memory
|
||||
0x2c000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| test chips peripherals |
|
||||
0x20000000 |--------------------------| ------------
|
||||
| Peripherals | Device Memory RW/RO
|
||||
| | & Fault
|
||||
0x00000000 |--------------------------|
|
||||
*/
|
||||
|
||||
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
|
||||
// Write-Through support *not* available
|
||||
// Write-Back support available.
|
||||
// Read allocation support available.
|
||||
// Write allocation support available.
|
||||
|
||||
//Note: You should use the Shareable attribute carefully.
|
||||
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
|
||||
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
|
||||
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
|
||||
|
||||
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
|
||||
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
|
||||
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
|
||||
|
||||
|
||||
//Following MMU configuration is expected
|
||||
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
|
||||
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
|
||||
//Domain 0 is always the Client domain
|
||||
//Descriptors should place all memory in domain 0
|
||||
|
||||
#include "ARMCA7.h"
|
||||
#include "mem_ARMCA7.h"
|
||||
|
||||
// TTB base address
|
||||
#define TTB_BASE ((uint32_t*)__TTB_BASE)
|
||||
|
||||
// L2 table pointers
|
||||
//----------------------------------------
|
||||
#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
|
||||
// into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
|
||||
// The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
|
||||
|
||||
#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
|
||||
#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
|
||||
#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
|
||||
#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
|
||||
|
||||
//--------------------- PERIPHERALS -------------------
|
||||
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
|
||||
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
|
||||
|
||||
//--------------------- SYNC FLAGS --------------------
|
||||
#define FLAG_SYNC 0xFFFFF000
|
||||
#define F_SYNC_BASE 0xFFF00000 //1M aligned
|
||||
|
||||
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
|
||||
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
|
||||
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
|
||||
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
|
||||
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
|
||||
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
|
||||
|
||||
/* Define global descriptors */
|
||||
static uint32_t Page_L1_4k = 0x0; //generic
|
||||
static uint32_t Page_L1_64k = 0x0; //generic
|
||||
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
|
||||
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
|
||||
|
||||
void MMU_CreateTranslationTable(void)
|
||||
{
|
||||
mmu_region_attributes_Type region;
|
||||
|
||||
//Create 4GB of faulting entries
|
||||
MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
|
||||
|
||||
/*
|
||||
* Generate descriptors. Refer to core_ca.h to get information about attributes
|
||||
*
|
||||
*/
|
||||
//Create descriptors for Vectors, RO, RW, ZI sections
|
||||
section_normal(Sect_Normal, region);
|
||||
section_normal_cod(Sect_Normal_Cod, region);
|
||||
section_normal_ro(Sect_Normal_RO, region);
|
||||
section_normal_rw(Sect_Normal_RW, region);
|
||||
//Create descriptors for peripherals
|
||||
section_device_ro(Sect_Device_RO, region);
|
||||
section_device_rw(Sect_Device_RW, region);
|
||||
//Create descriptors for 64k pages
|
||||
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
|
||||
//Create descriptors for 4k pages
|
||||
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
|
||||
|
||||
|
||||
/*
|
||||
* Define MMU flat-map regions and attributes
|
||||
*
|
||||
*/
|
||||
|
||||
//Define Image
|
||||
MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
|
||||
MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
|
||||
|
||||
//--------------------- PERIPHERALS -------------------
|
||||
MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR
|
||||
MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR
|
||||
MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
|
||||
MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
|
||||
MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW);
|
||||
MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE , 16, Sect_Device_RW);
|
||||
|
||||
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
|
||||
MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
|
||||
// Define peripheral range 0x1C000000-0x1C00FFFF
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
|
||||
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
|
||||
MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
|
||||
// Define peripheral range 0x1C100000-0x1C10FFFF
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
|
||||
// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
|
||||
MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
|
||||
// Define private address space entry.
|
||||
MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
// Define L2CC entry. Uncomment if PL310 is present
|
||||
// MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
|
||||
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
|
||||
MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
|
||||
// Define synchronization space entry.
|
||||
MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
|
||||
/* Set location of level 1 page table
|
||||
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
|
||||
; 13:7 - 0x0
|
||||
; 6 - IRGN[0] 0x1 (Inner WB WA)
|
||||
; 5 - NOS 0x0 (Non-shared)
|
||||
; 4:3 - RGN 0x01 (Outer WB WA)
|
||||
; 2 - IMP 0x0 (Implementation Defined)
|
||||
; 1 - S 0x0 (Non-shared)
|
||||
; 0 - IRGN[1] 0x0 (Inner WB WA) */
|
||||
__set_TTBR0(__TTB_BASE | 0x48);
|
||||
__ISB();
|
||||
|
||||
/* Set up domain access control register
|
||||
; We set domain 0 to Client and all other domains to No Access.
|
||||
; All translation table entries specify domain 0 */
|
||||
__set_DACR(1);
|
||||
__ISB();
|
||||
}
|
||||
@ -0,0 +1,136 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCA7.c
|
||||
* @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <ARMCA7.h>
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define USR_MODE 0x10 // User mode
|
||||
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
|
||||
#define IRQ_MODE 0x12 // Interrupt Request mode
|
||||
#define SVC_MODE 0x13 // Supervisor mode
|
||||
#define ABT_MODE 0x17 // Abort mode
|
||||
#define UND_MODE 0x1B // Undefined Instruction mode
|
||||
#define SYS_MODE 0x1F // System mode
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Vectors (void) __attribute__ ((naked, section("RESET")));
|
||||
void Reset_Handler (void) __attribute__ ((naked));
|
||||
void Default_Handler(void) __attribute__ ((noreturn));
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector Table
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Vectors(void) {
|
||||
__ASM volatile(
|
||||
"LDR PC, =Reset_Handler \n"
|
||||
"LDR PC, =Undef_Handler \n"
|
||||
"LDR PC, =SVC_Handler \n"
|
||||
"LDR PC, =PAbt_Handler \n"
|
||||
"LDR PC, =DAbt_Handler \n"
|
||||
"NOP \n"
|
||||
"LDR PC, =IRQ_Handler \n"
|
||||
"LDR PC, =FIQ_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void) {
|
||||
__ASM volatile(
|
||||
|
||||
// Mask interrupts
|
||||
"CPSID if \n"
|
||||
|
||||
// Put any cores other than 0 to sleep
|
||||
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
|
||||
"ANDS R0, R0, #3 \n"
|
||||
"goToSleep: \n"
|
||||
"WFINE \n"
|
||||
"BNE goToSleep \n"
|
||||
|
||||
// Reset SCTLR Settings
|
||||
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
|
||||
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
|
||||
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
|
||||
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
|
||||
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
|
||||
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
|
||||
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
|
||||
"ISB \n"
|
||||
|
||||
// Configure ACTLR
|
||||
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
|
||||
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
|
||||
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
|
||||
|
||||
// Set Vector Base Address Register (VBAR) to point to this application's vector table
|
||||
"LDR R0, =Vectors \n"
|
||||
"MCR p15, 0, R0, c12, c0, 0 \n"
|
||||
|
||||
// Setup Stack for each exceptional mode
|
||||
"CPS #0x11 \n"
|
||||
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x12 \n"
|
||||
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x13 \n"
|
||||
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x17 \n"
|
||||
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x1B \n"
|
||||
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x1F \n"
|
||||
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
|
||||
|
||||
// Call SystemInit
|
||||
"BL SystemInit \n"
|
||||
|
||||
// Unmask interrupts
|
||||
"CPSIE if \n"
|
||||
|
||||
// Call __main
|
||||
"BL __main \n"
|
||||
);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void) {
|
||||
while(1);
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
/******************************************************************************
|
||||
* @file system_ARMCA7.c
|
||||
* @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
|
||||
* @version V1.0.1
|
||||
* @date 13. February 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "irq_ctrl.h"
|
||||
|
||||
#define SYSTEM_CLOCK 12000000U
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Initialization
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* do not use global variables because this function is called before
|
||||
reaching pre-main. RW section may be overwritten afterwards. */
|
||||
|
||||
// Invalidate entire Unified TLB
|
||||
__set_TLBIALL(0);
|
||||
|
||||
// Invalidate entire branch predictor array
|
||||
__set_BPIALL(0);
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
// Invalidate instruction cache and flush branch target cache
|
||||
__set_ICIALLU(0);
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
// Invalidate data cache
|
||||
L1C_InvalidateDCacheAll();
|
||||
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
// Enable FPU
|
||||
__FPU_Enable();
|
||||
#endif
|
||||
|
||||
// Create Translation Table
|
||||
MMU_CreateTranslationTable();
|
||||
|
||||
// Enable MMU
|
||||
MMU_Enable();
|
||||
|
||||
// Enable Caches
|
||||
L1C_EnableCaches();
|
||||
L1C_EnableBTAC();
|
||||
|
||||
#if (__L2C_PRESENT == 1)
|
||||
// Enable GIC
|
||||
L2C_Enable();
|
||||
#endif
|
||||
|
||||
// IRQ Initialize
|
||||
IRQ_Initialize();
|
||||
}
|
||||
@ -0,0 +1,65 @@
|
||||
/******************************************************************************
|
||||
* @file system_ARMCA7.h
|
||||
* @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series
|
||||
* @version V1.00
|
||||
* @date 10. January 2018
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_ARMCA7_H
|
||||
#define __SYSTEM_ARMCA7_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
\brief Setup the microcontroller system.
|
||||
|
||||
Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Update SystemCoreClock variable.
|
||||
|
||||
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
/**
|
||||
\brief Create Translation Table.
|
||||
|
||||
Creates Memory Management Unit Translation Table.
|
||||
*/
|
||||
extern void MMU_CreateTranslationTable(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_ARMCA7_H */
|
||||
@ -0,0 +1,181 @@
|
||||
#include "mem_ARMCA9.h"
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
|
||||
L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE
|
||||
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
|
||||
Image$$VECTORS$$Base = .;
|
||||
* (RESET)
|
||||
KEEP(*(.isr_vector))
|
||||
Image$$VECTORS$$Limit = .;
|
||||
|
||||
*(SVC_TABLE)
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
Image$$RO_DATA$$Base = .;
|
||||
*(.rodata*)
|
||||
Image$$RO_DATA$$Limit = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > ROM
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > ROM
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ROM
|
||||
__exidx_end = .;
|
||||
|
||||
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > ROM
|
||||
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > ROM
|
||||
|
||||
__etext = .;
|
||||
|
||||
.ttb :
|
||||
{
|
||||
Image$$TTB$$ZI$$Base = .;
|
||||
. += __TTB_SIZE;
|
||||
Image$$TTB$$ZI$$Limit = .;
|
||||
} > L_TTB
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
Image$$RW_DATA$$Base = .;
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
Image$$RW_DATA$$Limit = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
|
||||
.bss ALIGN(0x400):
|
||||
{
|
||||
Image$$ZI_DATA$$Base = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
Image$$ZI_DATA$$Limit = .;
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
} > RAM
|
||||
|
||||
#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
Image$$HEAP$$ZI$$Base = .;
|
||||
. += __HEAP_SIZE;
|
||||
Image$$HEAP$$ZI$$Limit = .;
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
#endif
|
||||
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
|
||||
__StackTop = .;
|
||||
Image$$SYS_STACK$$ZI$$Base = .;
|
||||
. += __STACK_SIZE;
|
||||
Image$$SYS_STACK$$ZI$$Limit = .;
|
||||
__stack = .;
|
||||
|
||||
Image$$FIQ_STACK$$ZI$$Base = .;
|
||||
. += __FIQ_STACK_SIZE;
|
||||
Image$$FIQ_STACK$$ZI$$Limit = .;
|
||||
|
||||
Image$$IRQ_STACK$$ZI$$Base = .;
|
||||
. += __IRQ_STACK_SIZE;
|
||||
Image$$IRQ_STACK$$ZI$$Limit = .;
|
||||
|
||||
Image$$SVC_STACK$$ZI$$Base = .;
|
||||
. += __SVC_STACK_SIZE;
|
||||
Image$$SVC_STACK$$ZI$$Limit = .;
|
||||
|
||||
Image$$ABT_STACK$$ZI$$Base = .;
|
||||
. += __ABT_STACK_SIZE;
|
||||
Image$$ABT_STACK$$ZI$$Limit = .;
|
||||
|
||||
Image$$UND_STACK$$ZI$$Base = .;
|
||||
. += __UND_STACK_SIZE;
|
||||
Image$$UND_STACK$$ZI$$Limit = .;
|
||||
|
||||
} > RAM
|
||||
}
|
||||
@ -0,0 +1,77 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc
|
||||
;**************************************************
|
||||
; Copyright (c) 2017 ARM Ltd. All rights reserved.
|
||||
;**************************************************
|
||||
|
||||
; Scatter-file for RTX Example on Versatile Express
|
||||
|
||||
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
|
||||
|
||||
; This platform has 2GB SDRAM starting at 0x80000000.
|
||||
|
||||
#include "mem_ARMCA9.h"
|
||||
|
||||
SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
|
||||
{
|
||||
VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
|
||||
{
|
||||
* (RESET, +FIRST) ; Vector table and other startup code
|
||||
* (InRoot$$Sections) ; All (library) code that must be in a root region
|
||||
* (+RO-CODE) ; Application RO code (.text)
|
||||
* (+RO-DATA) ; Application RO data (.constdata)
|
||||
}
|
||||
|
||||
RW_DATA __RAM_BASE __RW_DATA_SIZE
|
||||
{ * (+RW) } ; Application RW data (.data)
|
||||
|
||||
ZI_DATA (__RAM_BASE+
|
||||
__RW_DATA_SIZE) __ZI_DATA_SIZE
|
||||
{ * (+ZI) } ; Application ZI data (.bss)
|
||||
|
||||
ARM_LIB_HEAP (__RAM_BASE
|
||||
+__RW_DATA_SIZE
|
||||
+__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
|
||||
{ }
|
||||
|
||||
ARM_LIB_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE
|
||||
-__IRQ_STACK_SIZE
|
||||
-__SVC_STACK_SIZE
|
||||
-__ABT_STACK_SIZE
|
||||
-__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
|
||||
{ }
|
||||
|
||||
UND_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE
|
||||
-__IRQ_STACK_SIZE
|
||||
-__SVC_STACK_SIZE
|
||||
-__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
|
||||
{ }
|
||||
|
||||
ABT_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE
|
||||
-__IRQ_STACK_SIZE
|
||||
-__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
|
||||
{ }
|
||||
|
||||
SVC_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE
|
||||
-__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
|
||||
{ }
|
||||
|
||||
IRQ_STACK (__RAM_BASE
|
||||
+__RAM_SIZE
|
||||
-__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
|
||||
{ }
|
||||
|
||||
FIQ_STACK (__RAM_BASE
|
||||
+__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
|
||||
{ }
|
||||
|
||||
TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
|
||||
{ }
|
||||
}
|
||||
@ -0,0 +1,100 @@
|
||||
/**************************************************************************//**
|
||||
* @file mem_ARMCA9.h
|
||||
* @brief Memory base and size definitions (used in scatter file)
|
||||
* @version V1.1.0
|
||||
* @date 15. May 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __MEM_ARMCA9_H
|
||||
#define __MEM_ARMCA9_H
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
User Stack & Heap size definition
|
||||
*----------------------------------------------------------------------------*/
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- ROM Configuration ------------------------------------
|
||||
//
|
||||
// <h> ROM Configuration
|
||||
// <i> For compatibility with MMU config the sections must be multiple of 1MB
|
||||
// <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
|
||||
// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
|
||||
// </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __ROM_BASE 0x80000000
|
||||
#define __ROM_SIZE 0x00200000
|
||||
|
||||
/*--------------------- RAM Configuration -----------------------------------
|
||||
// <h> RAM Configuration
|
||||
// <i> For compatibility with MMU config the sections must be multiple of 1MB
|
||||
// <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000>
|
||||
// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
|
||||
// <h> Data Sections
|
||||
// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
// <h> Stack / Heap Configuration
|
||||
// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <h> Exceptional Modes
|
||||
// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __RAM_BASE 0x80200000
|
||||
#define __RAM_SIZE 0x00300000
|
||||
|
||||
#define __RW_DATA_SIZE 0x00100000
|
||||
#define __ZI_DATA_SIZE 0x000F0000
|
||||
|
||||
#define __STACK_SIZE 0x00002000
|
||||
#define __HEAP_SIZE 0x00100000
|
||||
|
||||
#define __UND_STACK_SIZE 0x00000100
|
||||
#define __ABT_STACK_SIZE 0x00000100
|
||||
#define __SVC_STACK_SIZE 0x00000100
|
||||
#define __IRQ_STACK_SIZE 0x00000100
|
||||
#define __FIQ_STACK_SIZE 0x00000100
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/*--------------------- TTB Configuration ------------------------------------
|
||||
//
|
||||
// <h> TTB Configuration
|
||||
// <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
|
||||
// <i> The TLB L2 entries are placed after the L1 in the MMU config
|
||||
// <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
|
||||
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __TTB_BASE 0x80500000
|
||||
#define __TTB_SIZE 0x00005000
|
||||
|
||||
#endif /* __MEM_ARMCA9_H */
|
||||
@ -0,0 +1,232 @@
|
||||
/**************************************************************************//**
|
||||
* @file mmu_ARMCA9.c
|
||||
* @brief MMU Configuration for Arm Cortex-A9 Device Series
|
||||
* @version V1.2.0
|
||||
* @date 15. May 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
|
||||
|
||||
Memory Type
|
||||
0xffffffff |--------------------------| ------------
|
||||
| FLAG SYNC | Device Memory
|
||||
0xfffff000 |--------------------------| ------------
|
||||
| Fault | Fault
|
||||
0xfff00000 |--------------------------| ------------
|
||||
| | Normal
|
||||
| |
|
||||
| Daughterboard |
|
||||
| memory |
|
||||
| |
|
||||
0x80505000 |--------------------------| ------------
|
||||
|TTB (L2 Sync Flags ) 4k | Normal
|
||||
0x80504C00 |--------------------------| ------------
|
||||
|TTB (L2 Peripherals-B) 16k| Normal
|
||||
0x80504800 |--------------------------| ------------
|
||||
|TTB (L2 Peripherals-A) 16k| Normal
|
||||
0x80504400 |--------------------------| ------------
|
||||
|TTB (L2 Priv Periphs) 4k | Normal
|
||||
0x80504000 |--------------------------| ------------
|
||||
| TTB (L1 Descriptors) | Normal
|
||||
0x80500000 |--------------------------| ------------
|
||||
| Stack | Normal
|
||||
|--------------------------| ------------
|
||||
| Heap | Normal
|
||||
0x80400000 |--------------------------| ------------
|
||||
| ZI Data | Normal
|
||||
0x80300000 |--------------------------| ------------
|
||||
| RW Data | Normal
|
||||
0x80200000 |--------------------------| ------------
|
||||
| RO Data | Normal
|
||||
|--------------------------| ------------
|
||||
| RO Code | USH Normal
|
||||
0x80000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| HSB AXI buses |
|
||||
0x40000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| test chips peripherals |
|
||||
0x2c002000 |--------------------------| ------------
|
||||
| Private Address | Device Memory
|
||||
0x2c000000 |--------------------------| ------------
|
||||
| Daughterboard | Fault
|
||||
| test chips peripherals |
|
||||
0x20000000 |--------------------------| ------------
|
||||
| Peripherals | Device Memory RW/RO
|
||||
| | & Fault
|
||||
0x00000000 |--------------------------|
|
||||
*/
|
||||
|
||||
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
|
||||
// Write-Through support *not* available
|
||||
// Write-Back support available.
|
||||
// Read allocation support available.
|
||||
// Write allocation support available.
|
||||
|
||||
//Note: You should use the Shareable attribute carefully.
|
||||
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
|
||||
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
|
||||
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
|
||||
|
||||
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
|
||||
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
|
||||
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
|
||||
|
||||
|
||||
//Following MMU configuration is expected
|
||||
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
|
||||
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
|
||||
//Domain 0 is always the Client domain
|
||||
//Descriptors should place all memory in domain 0
|
||||
|
||||
#include "ARMCA9.h"
|
||||
#include "mem_ARMCA9.h"
|
||||
|
||||
// TTB base address
|
||||
#define TTB_BASE ((uint32_t*)__TTB_BASE)
|
||||
|
||||
// L2 table pointers
|
||||
//----------------------------------------
|
||||
#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
|
||||
// into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
|
||||
// The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
|
||||
|
||||
#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
|
||||
#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
|
||||
#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
|
||||
#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
|
||||
|
||||
//--------------------- PERIPHERALS -------------------
|
||||
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
|
||||
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
|
||||
|
||||
//--------------------- SYNC FLAGS --------------------
|
||||
#define FLAG_SYNC 0xFFFFF000
|
||||
#define F_SYNC_BASE 0xFFF00000 //1M aligned
|
||||
|
||||
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
|
||||
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
|
||||
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
|
||||
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
|
||||
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
|
||||
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
|
||||
|
||||
/* Define global descriptors */
|
||||
static uint32_t Page_L1_4k = 0x0; //generic
|
||||
static uint32_t Page_L1_64k = 0x0; //generic
|
||||
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
|
||||
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
|
||||
|
||||
void MMU_CreateTranslationTable(void)
|
||||
{
|
||||
mmu_region_attributes_Type region;
|
||||
|
||||
//Create 4GB of faulting entries
|
||||
MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
|
||||
|
||||
/*
|
||||
* Generate descriptors. Refer to core_ca.h to get information about attributes
|
||||
*
|
||||
*/
|
||||
//Create descriptors for Vectors, RO, RW, ZI sections
|
||||
section_normal(Sect_Normal, region);
|
||||
section_normal_cod(Sect_Normal_Cod, region);
|
||||
section_normal_ro(Sect_Normal_RO, region);
|
||||
section_normal_rw(Sect_Normal_RW, region);
|
||||
//Create descriptors for peripherals
|
||||
section_device_ro(Sect_Device_RO, region);
|
||||
section_device_rw(Sect_Device_RW, region);
|
||||
//Create descriptors for 64k pages
|
||||
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
|
||||
//Create descriptors for 4k pages
|
||||
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
|
||||
|
||||
|
||||
/*
|
||||
* Define MMU flat-map regions and attributes
|
||||
*
|
||||
*/
|
||||
|
||||
//Define Image
|
||||
MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
|
||||
MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
|
||||
|
||||
//--------------------- PERIPHERALS -------------------
|
||||
MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR
|
||||
MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR
|
||||
MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
|
||||
MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
|
||||
MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);
|
||||
MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE , 16, Sect_Device_RW);
|
||||
|
||||
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
|
||||
MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
|
||||
// Define peripheral range 0x1C000000-0x1C00FFFF
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
|
||||
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
|
||||
MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
|
||||
// Define peripheral range 0x1C100000-0x1C10FFFF
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
|
||||
|
||||
// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
|
||||
MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
|
||||
// Define private address space entry.
|
||||
MMU_TTPage4k (TTB_BASE, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
// Define L2CC entry. Uncomment if PL310 is present
|
||||
// MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
|
||||
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
|
||||
MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
|
||||
// Define synchronization space entry.
|
||||
MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
|
||||
|
||||
/* Set location of level 1 page table
|
||||
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
|
||||
; 13:7 - 0x0
|
||||
; 6 - IRGN[0] 0x1 (Inner WB WA)
|
||||
; 5 - NOS 0x0 (Non-shared)
|
||||
; 4:3 - RGN 0x01 (Outer WB WA)
|
||||
; 2 - IMP 0x0 (Implementation Defined)
|
||||
; 1 - S 0x0 (Non-shared)
|
||||
; 0 - IRGN[1] 0x0 (Inner WB WA) */
|
||||
__set_TTBR0(__TTB_BASE | 0x48);
|
||||
__ISB();
|
||||
|
||||
/* Set up domain access control register
|
||||
; We set domain 0 to Client and all other domains to No Access.
|
||||
; All translation table entries specify domain 0 */
|
||||
__set_DACR(1);
|
||||
__ISB();
|
||||
}
|
||||
@ -0,0 +1,136 @@
|
||||
/******************************************************************************
|
||||
* @file startup_ARMCA9.c
|
||||
* @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <ARMCA9.h>
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define USR_MODE 0x10 // User mode
|
||||
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
|
||||
#define IRQ_MODE 0x12 // Interrupt Request mode
|
||||
#define SVC_MODE 0x13 // Supervisor mode
|
||||
#define ABT_MODE 0x17 // Abort mode
|
||||
#define UND_MODE 0x1B // Undefined Instruction mode
|
||||
#define SYS_MODE 0x1F // System mode
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Internal References
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Vectors (void) __attribute__ ((naked, section("RESET")));
|
||||
void Reset_Handler (void) __attribute__ ((naked));
|
||||
void Default_Handler(void) __attribute__ ((noreturn));
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Exception / Interrupt Vector Table
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Vectors(void) {
|
||||
__ASM volatile(
|
||||
"LDR PC, =Reset_Handler \n"
|
||||
"LDR PC, =Undef_Handler \n"
|
||||
"LDR PC, =SVC_Handler \n"
|
||||
"LDR PC, =PAbt_Handler \n"
|
||||
"LDR PC, =DAbt_Handler \n"
|
||||
"NOP \n"
|
||||
"LDR PC, =IRQ_Handler \n"
|
||||
"LDR PC, =FIQ_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Reset Handler called on controller reset
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void) {
|
||||
__ASM volatile(
|
||||
|
||||
// Mask interrupts
|
||||
"CPSID if \n"
|
||||
|
||||
// Put any cores other than 0 to sleep
|
||||
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
|
||||
"ANDS R0, R0, #3 \n"
|
||||
"goToSleep: \n"
|
||||
"WFINE \n"
|
||||
"BNE goToSleep \n"
|
||||
|
||||
// Reset SCTLR Settings
|
||||
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
|
||||
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
|
||||
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
|
||||
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
|
||||
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
|
||||
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
|
||||
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
|
||||
"ISB \n"
|
||||
|
||||
// Configure ACTLR
|
||||
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
|
||||
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
|
||||
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
|
||||
|
||||
// Set Vector Base Address Register (VBAR) to point to this application's vector table
|
||||
"LDR R0, =Vectors \n"
|
||||
"MCR p15, 0, R0, c12, c0, 0 \n"
|
||||
|
||||
// Setup Stack for each exceptional mode
|
||||
"CPS #0x11 \n"
|
||||
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x12 \n"
|
||||
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x13 \n"
|
||||
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x17 \n"
|
||||
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x1B \n"
|
||||
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
|
||||
"CPS #0x1F \n"
|
||||
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
|
||||
|
||||
// Call SystemInit
|
||||
"BL SystemInit \n"
|
||||
|
||||
// Unmask interrupts
|
||||
"CPSIE if \n"
|
||||
|
||||
// Call __main
|
||||
"BL __main \n"
|
||||
);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Default Handler for Exceptions / Interrupts
|
||||
*----------------------------------------------------------------------------*/
|
||||
void Default_Handler(void) {
|
||||
while(1);
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
/******************************************************************************
|
||||
* @file system_ARMCA9.c
|
||||
* @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
|
||||
* @version V1.0.1
|
||||
* @date 13. February 2019
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "irq_ctrl.h"
|
||||
|
||||
#define SYSTEM_CLOCK 12000000U
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = SYSTEM_CLOCK;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update function
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Initialization
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* do not use global variables because this function is called before
|
||||
reaching pre-main. RW section may be overwritten afterwards. */
|
||||
|
||||
// Invalidate entire Unified TLB
|
||||
__set_TLBIALL(0);
|
||||
|
||||
// Invalidate entire branch predictor array
|
||||
__set_BPIALL(0);
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
// Invalidate instruction cache and flush branch target cache
|
||||
__set_ICIALLU(0);
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
// Invalidate data cache
|
||||
L1C_InvalidateDCacheAll();
|
||||
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
// Enable FPU
|
||||
__FPU_Enable();
|
||||
#endif
|
||||
|
||||
// Create Translation Table
|
||||
MMU_CreateTranslationTable();
|
||||
|
||||
// Enable MMU
|
||||
MMU_Enable();
|
||||
|
||||
// Enable Caches
|
||||
L1C_EnableCaches();
|
||||
L1C_EnableBTAC();
|
||||
|
||||
#if (__L2C_PRESENT == 1)
|
||||
// Enable GIC
|
||||
L2C_Enable();
|
||||
#endif
|
||||
|
||||
// IRQ Initialize
|
||||
IRQ_Initialize();
|
||||
}
|
||||
@ -0,0 +1,65 @@
|
||||
/******************************************************************************
|
||||
* @file system_ARMCA9.h
|
||||
* @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series
|
||||
* @version V1.00
|
||||
* @date 10. January 2018
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_ARMCA9_H
|
||||
#define __SYSTEM_ARMCA9_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
\brief Setup the microcontroller system.
|
||||
|
||||
Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Update SystemCoreClock variable.
|
||||
|
||||
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
/**
|
||||
\brief Create Translation Table.
|
||||
|
||||
Creates Memory Management Unit Translation Table.
|
||||
*/
|
||||
extern void MMU_CreateTranslationTable(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_ARMCA9_H */
|
||||
@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'test.Release+FVP_A5Neon'
|
||||
* Target: 'test.Release+FVP_A5Neon'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCA5.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'test.Release+FVP_A7Neon'
|
||||
* Target: 'test.Release+FVP_A7Neon'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCA7.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'test.Release+FVP_A9Neon'
|
||||
* Target: 'test.Release+FVP_A9Neon'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "ARMCA9.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@ -1,19 +1,13 @@
|
||||
|
||||
|
||||
cbuild "test.Release+VHT_M0P.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+VHT_M23.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+VHT_M3.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+VHT_M4.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+VHT_M7.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+VHT_M33.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+VHT-Corstone-300.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+VHT-Corstone-310.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+FVP_M55.cprj" --outdir=Objects --intdir=Tmp
|
||||
# cbuild "test.Release+VHT_M0P.cprj" --outdir=Objects --intdir=Tmp
|
||||
# cbuild "test.Release+VHT_M23.cprj" --outdir=Objects --intdir=Tmp
|
||||
# cbuild "test.Release+VHT_M3.cprj" --outdir=Objects --intdir=Tmp
|
||||
# cbuild "test.Release+VHT_M4.cprj" --outdir=Objects --intdir=Tmp
|
||||
# cbuild "test.Release+VHT_M7.cprj" --outdir=Objects --intdir=Tmp
|
||||
# cbuild "test.Release+VHT_M33.cprj" --outdir=Objects --intdir=Tmp
|
||||
#cbuild "test.Release+VHT-Corstone-300.cprj" --outdir=Objects --intdir=Tmp
|
||||
# cbuild "test.Release+VHT-Corstone-310.cprj" --outdir=Objects --intdir=Tmp
|
||||
# cbuild "test.Release+FVP_M55.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
cbuild "test.Release+FVP_A5Neon.cprj" --outdir=Objects --intdir=Tmp
|
||||
#cbuild "test.Release+FVP_A7Neon.cprj" --outdir=Objects --intdir=Tmp
|
||||
#cbuild "test.Release+FVP_A9Neon.cprj" --outdir=Objects --intdir=Tmp
|
||||
|
||||
@ -0,0 +1,21 @@
|
||||
# Parameters:
|
||||
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
|
||||
#----------------------------------------------------------------------------------------------
|
||||
motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
|
||||
cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
|
||||
cluster.cpu0.ase-present=1 # (bool , init-time) default = '1' : Set whether model has NEON support
|
||||
cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
|
||||
cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
|
||||
cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]
|
||||
cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF]
|
||||
cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]
|
||||
cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F]
|
||||
cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
|
||||
cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
|
||||
cluster.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation
|
||||
cluster.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation
|
||||
#----------------------------------------------------------------------------------------------
|
||||
@ -0,0 +1,22 @@
|
||||
# Parameters:
|
||||
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
|
||||
#----------------------------------------------------------------------------------------------
|
||||
motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
|
||||
cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether CT model has been built with VFP support
|
||||
cluster.cpu0.ase-present=1 # (bool , init-time) default = '1' : Set whether CT model has been built with NEON support
|
||||
cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
|
||||
cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
|
||||
cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]
|
||||
cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF]
|
||||
cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]
|
||||
cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F]
|
||||
cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
|
||||
cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
|
||||
cluster.l1_icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L1 I-cache has stateful implementation
|
||||
cluster.l1_dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L1 D-cache has stateful implementation
|
||||
cluster.l2_cache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L2 cache has stateful implementation
|
||||
#----------------------------------------------------------------------------------------------
|
||||
@ -0,0 +1,21 @@
|
||||
# Parameters:
|
||||
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
|
||||
#----------------------------------------------------------------------------------------------
|
||||
motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
|
||||
cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
|
||||
cluster.cpu0.ase-present=1 # (bool , init-time) default = '1' : Set whether model has NEON support
|
||||
cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
|
||||
cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
|
||||
cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]
|
||||
cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF]
|
||||
cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]
|
||||
cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F]
|
||||
cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
|
||||
cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
|
||||
cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
|
||||
cluster.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation
|
||||
cluster.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation
|
||||
#----------------------------------------------------------------------------------------------
|
||||
@ -0,0 +1,11 @@
|
||||
"C:\Program Files\ARM\Development Studio 2022.0\bin\FVP_VE_Cortex-A5x1.exe" ^
|
||||
-f configs/ARMCA5neon_config.txt ^
|
||||
Objects\test.Release+FVP_A5Neon.axf
|
||||
|
||||
REM "C:\Program Files\ARM\Development Studio 2022.0\bin\FVP_VE_Cortex-A7x1.exe" ^
|
||||
REM -f configs/ARMCA7neon_config.txt ^
|
||||
REM Objects\test.Release+FVP_A7Neon.axf
|
||||
|
||||
REM "C:\Program Files\ARM\Development Studio 2022.0\bin\FVP_VE_Cortex-A9x1.exe" ^
|
||||
REM -f configs/ARMCA9neon_config.txt ^
|
||||
REM Objects\test.Release+FVP_A9Neon.axf
|
||||
@ -0,0 +1,167 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
|
||||
<created timestamp="2022-07-11T12:56:52" tool="csolution 0.9.6"/>
|
||||
|
||||
<info isLayer="false">
|
||||
<description>Automatically generated project</description>
|
||||
</info>
|
||||
|
||||
<packages>
|
||||
<package name="CMSIS-DSP" vendor="ARM" version="1.10.1:1.10.1"/>
|
||||
<package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
|
||||
</packages>
|
||||
|
||||
<compilers>
|
||||
<compiler name="AC6" version="6.18.0"/>
|
||||
</compilers>
|
||||
|
||||
<target Dfpu="DP_FPU" Dname="ARMCA5" Dsecure="Non-secure" Dvendor="ARM:82">
|
||||
<output intdir="test.Release+FVP_A5Neon_IntDir/" name="test.Release+FVP_A5Neon" outdir="test.Release+FVP_A5Neon_OutDir/" type="exe"/>
|
||||
<asflags add="-masm=auto" compiler="AC6"/>
|
||||
<cflags add="-std=c11 -Ofast -ffast-math" compiler="AC6"/>
|
||||
<cxxflags add="-std=c++11 -Ofast -ffast-math" compiler="AC6"/>
|
||||
<ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="RTE/Device/ARMCA5/ARMCA5.sct"/>
|
||||
<defines>EMBEDDED;NORMALFVP;CORTEXA</defines>
|
||||
<includes>../FrameworkInclude;../GeneratedInclude;../Include/Tests</includes>
|
||||
</target>
|
||||
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.2.1"/>
|
||||
<component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.10.1">
|
||||
<defines>ARM_MATH_NEON</defines>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.1"/>
|
||||
<component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Cvendor="ARM" Cversion="1.0.2"/>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1">
|
||||
<file attr="config" category="header" name="Device/ARM/ARMCA5/Config/mem_ARMCA5.h" version="1.1.0"/>
|
||||
<file attr="config" category="header" name="Device/ARM/ARMCA5/Config/system_ARMCA5.h" version="1.0.0"/>
|
||||
<file attr="config" category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct" version="1.0.0"/>
|
||||
<file attr="config" category="sourceC" name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.1"/>
|
||||
<file attr="config" category="sourceC" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.2.0"/>
|
||||
<file attr="config" category="sourceC" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.1"/>
|
||||
</component>
|
||||
</components>
|
||||
|
||||
<files>
|
||||
<group name="App">
|
||||
<file category="sourceCpp" name="../main.cpp"/>
|
||||
<file category="sourceC" name="../patterndata.c"/>
|
||||
<file category="sourceCpp" name="../testmain.cpp"/>
|
||||
</group>
|
||||
<group name="TestFramework">
|
||||
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|
||||
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||||
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|
||||
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||||
|
||||
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|
||||
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|
||||
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|
||||
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||||
|
||||
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|
||||
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|
||||
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||||
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
|
||||
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||||
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||||
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||||
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||||
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|
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@ -0,0 +1,167 @@
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|
||||
|
||||
<info isLayer="false">
|
||||
<description>Automatically generated project</description>
|
||||
</info>
|
||||
|
||||
<packages>
|
||||
<package name="CMSIS-DSP" vendor="ARM" version="1.10.1:1.10.1"/>
|
||||
<package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
|
||||
</packages>
|
||||
|
||||
<compilers>
|
||||
<compiler name="AC6" version="6.18.0"/>
|
||||
</compilers>
|
||||
|
||||
<target Dfpu="DP_FPU" Dname="ARMCA9" Dsecure="Non-secure" Dvendor="ARM:82">
|
||||
<output intdir="test.Release+FVP_A9Neon_IntDir/" name="test.Release+FVP_A9Neon" outdir="test.Release+FVP_A9Neon_OutDir/" type="exe"/>
|
||||
<asflags add="-masm=auto" compiler="AC6"/>
|
||||
<cflags add="-std=c11 -Ofast -ffast-math" compiler="AC6"/>
|
||||
<cxxflags add="-std=c++11 -Ofast -ffast-math" compiler="AC6"/>
|
||||
<ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="RTE/Device/ARMCA9/ARMCA9.sct"/>
|
||||
<defines>EMBEDDED;NORMALFVP;CORTEXA</defines>
|
||||
<includes>../FrameworkInclude;../GeneratedInclude;../Include/Tests</includes>
|
||||
</target>
|
||||
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.2.1"/>
|
||||
<component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.10.1">
|
||||
<defines>ARM_MATH_AUTOVECTORIZE</defines>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.1"/>
|
||||
<component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Cvendor="ARM" Cversion="1.0.2"/>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.2">
|
||||
<file attr="config" category="header" name="Device/ARM/ARMCA9/Config/mem_ARMCA9.h" version="1.1.0"/>
|
||||
<file attr="config" category="header" name="Device/ARM/ARMCA9/Config/system_ARMCA9.h" version="1.0.0"/>
|
||||
<file attr="config" category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct" version="1.0.0"/>
|
||||
<file attr="config" category="sourceC" name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.1"/>
|
||||
<file attr="config" category="sourceC" name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c" version="1.2.0"/>
|
||||
<file attr="config" category="sourceC" name="Device/ARM/ARMCA9/Source/system_ARMCA9.c" version="1.0.1"/>
|
||||
</component>
|
||||
</components>
|
||||
|
||||
<files>
|
||||
<group name="App">
|
||||
<file category="sourceCpp" name="../main.cpp"/>
|
||||
<file category="sourceC" name="../patterndata.c"/>
|
||||
<file category="sourceCpp" name="../testmain.cpp"/>
|
||||
</group>
|
||||
<group name="TestFramework">
|
||||
<file category="sourceCpp" name="../FrameworkSource/ArrayMemory.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/Calibrate.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/Error.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/FPGA.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/Generators.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/IORunner.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/Pattern.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/PatternMgr.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/Test.cpp"/>
|
||||
<file category="sourceCpp" name="../FrameworkSource/Timing.cpp"/>
|
||||
</group>
|
||||
<group name="GeneratedConfig">
|
||||
<file category="sourceCpp" name="../GeneratedSource/TestDesc.cpp"/>
|
||||
</group>
|
||||
<group name="Tests">
|
||||
<file category="sourceCpp" name="../Source/Tests/BasicTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BasicTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BasicTestsF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BasicTestsQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BasicTestsQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BasicTestsQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BayesF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BayesF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BinaryTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BinaryTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BinaryTestsF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BinaryTestsQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BinaryTestsQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BinaryTestsQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BIQUADF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BIQUADF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BIQUADF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BIQUADQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/BIQUADQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ComplexTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ComplexTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ComplexTestsF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ComplexTestsQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ComplexTestsQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/DECIMF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/DECIMQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/DECIMQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/DistanceTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/DistanceTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/DistanceTestsF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/DistanceTestsU32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ExampleCategoryF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FastMathF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FastMathF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FastMathF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FastMathQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FastMathQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FastMathQ63.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FIRF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FIRF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FIRF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FIRQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FIRQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/FIRQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/InterpolationTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/InterpolationTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ31.cpp"/>
|
||||
<file category="sourceC" name="../Source/Tests/mfccdata.c"/>
|
||||
<file category="sourceC" name="../Source/Tests/mfccdata_f16.c"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MFCCF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MFCCF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MFCCQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MFCCQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MISCF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MISCF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MISCF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MISCQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MISCQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/MISCQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/QuaternionTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/StatsTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/StatsTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/StatsTestsF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/StatsTestsQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/StatsTestsQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/StatsTestsQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SupportBarTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SupportBarTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SupportTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SupportTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SupportTestsF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SupportTestsQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SupportTestsQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SupportTestsQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SVMF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/SVMF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformCF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformCF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformCF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformCQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformCQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformRF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformRF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformRF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformRQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/TransformRQ31.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/UnaryTestsF16.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/UnaryTestsF32.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/UnaryTestsF64.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/UnaryTestsQ7.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/UnaryTestsQ15.cpp"/>
|
||||
<file category="sourceCpp" name="../Source/Tests/UnaryTestsQ31.cpp"/>
|
||||
</group>
|
||||
</files>
|
||||
</cprj>
|
||||
|
||||
Loading…
Reference in New Issue