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710 lines
27 KiB
C
710 lines
27 KiB
C
/**
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******************************************************************************
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* @file py32f403_ll_bus.h
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* @author MCU Application Team
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* @brief Header file of BUS LL module.
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@verbatim
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##### RCC Limitations #####
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==============================================================================
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[..]
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A delay between an RCC peripheral clock enable and the effective peripheral
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enabling should be taken into account in order to manage the peripheral read/write
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from/to registers.
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(+) This delay depends on the peripheral mapping.
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(++) AHB & APB peripherals, 1 dummy read is necessary
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[..]
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Workarounds:
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(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
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inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2023 Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by Puya under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef PY32F403_LL_BUS_H
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#define PY32F403_LL_BUS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "py32f4xx.h"
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/** @addtogroup PY32F403_LL_Driver
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* @{
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*/
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#if defined(RCC)
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/** @defgroup BUS_LL BUS
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
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* @{
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*/
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/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
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* @{
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*/
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#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
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#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
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#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHB1ENR_SRAMEN
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#define LL_AHB1_GRP1_PERIPH_FMC RCC_AHB1ENR_FMCEN
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#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
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#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHB1ENR_SDIOEN
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#define LL_AHB1_GRP1_PERIPH_ESMC RCC_AHB1ENR_ESMCEN
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
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* @{
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*/
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#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_IOPAEN
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#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_IOPBEN
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#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_IOPCEN
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#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_IOPDEN
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#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_IOPEEN
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
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* @{
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*/
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#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
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#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
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#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
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#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
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#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
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#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
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#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
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#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
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#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
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#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
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#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
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#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
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#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
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#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
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#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
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#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
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#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
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#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
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#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
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#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
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#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
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#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
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#define LL_APB1_GRP1_PERIPH_CTC RCC_APB1ENR_CTCEN
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
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* @{
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*/
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#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
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#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
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#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
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#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
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#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
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#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
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#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
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#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
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#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
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#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
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#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
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* @{
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*/
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/** @defgroup BUS_LL_EF_AHB1_GRP1 AHB1 GRP1
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* @{
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*/
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/**
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* @brief Enable AHB1 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_FMC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_SDIO
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* @arg @ref LL_AHB1_GRP1_PERIPH_ESMC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHB1ENR, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Check if AHB1 peripheral clock is enabled or not
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_FMC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_SDIO
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* @arg @ref LL_AHB1_GRP1_PERIPH_ESMC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval State of Periphs (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
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{
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return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
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}
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/**
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* @brief Disable AHB1 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_FMC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_SDIO
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* @arg @ref LL_AHB1_GRP1_PERIPH_ESMC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHB1ENR, Periphs);
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}
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/**
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* @brief Force AHB1 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_SDIO
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* @arg @ref LL_AHB1_GRP1_PERIPH_ESMC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
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{
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SET_BIT(RCC->AHB1RSTR, Periphs);
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}
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/**
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* @brief Release AHB1 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_SDIO
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* @arg @ref LL_AHB1_GRP1_PERIPH_ESMC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHB1RSTR, Periphs);
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}
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EF_AHB2_GRP1 AHB2 GRP1
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* @{
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*/
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/**
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* @brief Enable AHB2 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHB2ENR, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Check if AHB2 peripheral clock is enabled or not
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval State of Periphs (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
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{
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return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
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}
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/**
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* @brief Disable AHB2 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHB2ENR, Periphs);
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}
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/**
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* @brief Force AHB2 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
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{
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SET_BIT(RCC->AHB2RSTR, Periphs);
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}
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/**
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* @brief Release AHB2 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
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* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHB2RSTR, Periphs);
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}
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
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* @{
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*/
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/**
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* @brief Enable APB1 GRP1 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
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* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
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* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
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* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
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* @arg @ref LL_APB1_GRP1_PERIPH_USART2
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* @arg @ref LL_APB1_GRP1_PERIPH_USART3
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* @arg @ref LL_APB1_GRP1_PERIPH_USART4
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* @arg @ref LL_APB1_GRP1_PERIPH_USART5
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* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
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* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
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* @arg @ref LL_APB1_GRP1_PERIPH_USB
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* @arg @ref LL_APB1_GRP1_PERIPH_CAN
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_BKP
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CTC
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APB1ENR, Periphs);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
|
|
(void)tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Check if APB1 GRP1 peripheral clock is enabled or not
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CAN
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_BKP
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CTC
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval State of Periphs (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
|
|
{
|
|
return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable APB1 GRP1 peripherals clock.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CAN
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_BKP
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CTC
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APB1ENR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Force APB1 GRP1 peripherals reset.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CAN
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CTC
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
|
|
{
|
|
SET_BIT(RCC->APB1RSTR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Release APB1 GRP1 peripherals reset.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CAN
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CTC
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APB1RSTR, Periphs);
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup BUS_LL_EF_APB2_GRP1 APB2 GRP1
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable APB2 GRP1 peripherals clock.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APB2ENR, Periphs);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
|
|
(void)tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Check if APB2 GRP1 peripheral clock is enabled or not
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval State of Periphs (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
|
|
{
|
|
return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable APB2 GRP1 peripherals clock.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APB2ENR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Force APB2 GRP1 peripherals reset.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
|
|
{
|
|
SET_BIT(RCC->APB2RSTR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Release APB2 GRP1 peripherals reset.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
|
|
* @note Depending on devices and packages, some peripherals may not be available.
|
|
* Refer to device datasheet for peripherals availability.
|
|
* @note (*) peripheral not available on all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APB2RSTR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* RCC */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* PY32F403_LL_BUS_H */
|
|
|
|
/************************ (C) COPYRIGHT Puya *****END OF FILE****/
|