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616 lines
18 KiB
C
616 lines
18 KiB
C
/**
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******************************************************************************
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* @file py32f403_ll_rcc.c
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* @author MCU Application Team
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* @brief RCC LL module driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2023 Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by Puya under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "py32f403_ll_rcc.h"
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#ifdef USE_FULL_ASSERT
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#include "py32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif
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/** @addtogroup PY32F403_LL_Driver
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* @{
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*/
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#if defined(RCC)
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/** @addtogroup RCC_LL
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup RCC_LL_Private_Macros
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* @{
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*/
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#define IS_LL_RCC_MCO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_MCO_CLKSOURCE))
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup RCC_LL_Private_Functions RCC Private functions
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* @{
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*/
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uint32_t RCC_GetSystemClockFreq(void);
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uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
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uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
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uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
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#if defined(RCC_PLL_SUPPORT)
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uint32_t RCC_PLL_GetFreqDomain_SYS(void);
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#endif
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup RCC_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup RCC_LL_EF_Init
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* @{
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*/
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/**
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* @brief Reset the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - HSI ON and used as system clock source
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* - HSE and PLL OFF
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* - AHB and APB1 prescaler set to 1.
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* - CSS, MCO OFF
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* - All interrupts disabled
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* @note This function does not modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: RCC registers are de-initialized
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* - ERROR: not applicable
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*/
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ErrorStatus LL_RCC_DeInit(void)
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{
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uint32_t vl_mask;
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/* Set HSION bit and wait for HSI READY bit */
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() != 1U)
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{}
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/* Set HSITRIM bits to reset value*/
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LL_RCC_HSI_SetCalibTrimming(0x10U);
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/* Reset whole CFGR register, but keep HSI as the system clock source and
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do not modify the clock configuration of PLL, ADC, and USB */
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CLEAR_BIT(RCC->CFGR, ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL | \
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RCC_CFGR_ADCPRE | RCC_CFGR_USBPRE));
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/* Wait till SYSCLK is HSI */
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
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{}
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/* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */
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LL_RCC_WriteReg(CR, RCC_CR_HSION);
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while (LL_RCC_HSE_IsReady() != 0U)
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{}
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LL_RCC_WriteReg(CR, RCC_CR_HSION);
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#if defined(RCC_PLL_SUPPORT)
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/* Wait for PLL READY bit to be reset */
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while (LL_RCC_PLL_IsReady() != 0U)
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{}
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/* Reset configuration of PLL */
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CLEAR_BIT(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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#endif
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/* Disable all interrupts */
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LL_RCC_WriteReg(CIR, 0x00000000U);
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/* Clear all interrupts flags */
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vl_mask = RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | \
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RCC_CIR_PLLRDYC | RCC_CIR_HSI48RDYC | RCC_CIR_CSSC;
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LL_RCC_WriteReg(CIR, vl_mask);
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/* Clear reset flags */
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LL_RCC_ClearResetFlags();
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return SUCCESS;
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}
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/**
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* @}
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*/
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/** @addtogroup RCC_LL_EF_Get_Freq
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* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
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* and different peripheral clocks available on the device.
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* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
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* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
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* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
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* or HSI_VALUE(**) multiplied/divided by the PLL factors.
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* @note (**) HSI_VALUE is a constant defined in this file (default value
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* 8 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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* @note (***) HSE_VALUE is a constant defined in this file (default value
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* 24 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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* @note The result of this function could be incorrect when using fractional
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* value for HSE crystal.
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* @note This function can be used by the user application to compute the
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* baud-rate for the communication peripherals or configure other parameters.
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* @{
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*/
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/**
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* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
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* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
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* must be called to update structure fields. Otherwise, any
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* configuration based on this function will be incorrect.
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* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
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* @retval None
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*/
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void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
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{
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/* Get SYSCLK frequency */
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RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
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/* HCLK clock frequency */
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RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
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/* PCLK1 clock frequency */
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RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
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/* PCLK2 clock frequency */
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RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
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}
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/**
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* @brief Return MCO clock frequency
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* @param MCOx This parameter can be one of the following values:
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* @arg @ref LL_RCC_MCO_CLKSOURCE
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* @retval MCO clock frequency (in Hz)
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* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSE, LSI or LSE) is not ready
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* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
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*/
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uint32_t LL_RCC_GetMCOClockFreq(uint32_t MCOx)
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{
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uint32_t mco_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* Check parameter */
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assert_param(IS_LL_RCC_MCO_CLKSOURCE(MCOx));
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switch (LL_RCC_GetMCOClockSource(MCOx))
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{
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#if defined(RCC_LSE_SUPPORT)
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case LL_RCC_MCOSOURCE_LSE: /* MCO Clock is LSE */
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if (LL_RCC_LSE_IsReady() == 1U)
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{
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mco_frequency = LSE_VALUE;
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}
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break;
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#endif
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case LL_RCC_MCOSOURCE_LSI: /* MCO Clock is LSI */
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if (LL_RCC_LSI_IsReady() == 1U)
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{
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mco_frequency = LSI_VALUE;
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}
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break;
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case LL_RCC_MCOSOURCE_HSI48M: /* MCO Clock is HSI48M */
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mco_frequency = HSI48_VALUE;
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break;
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case LL_RCC_MCOSOURCE_SYSCLK: /* MCO Clock is SYSCLK */
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mco_frequency = SystemCoreClock;
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break;
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case LL_RCC_MCOSOURCE_HSI: /* MCO Clock is HSI */
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mco_frequency = HSI_VALUE;
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break;
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case LL_RCC_MCOSOURCE_HSE: /* MCO Clock is HSE */
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if (LL_RCC_HSE_IsReady() == 1U)
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{
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mco_frequency = HSE_VALUE;
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}
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break;
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#if defined(RCC_PLL_SUPPORT)
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case LL_RCC_MCOSOURCE_PLL: /* MCO Clock is PLLCLK */
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mco_frequency = RCC_PLL_GetFreqDomain_SYS();
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break;
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#endif
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case LL_RCC_MCOSOURCE_NOCLOCK: /* No clock used as MCO clock source */
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default:
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mco_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
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return mco_frequency;
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}
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mco_frequency = mco_frequency / (1U << (LL_RCC_GetMCODiv(MCOx) >> RCC_CFGR1_MCOPRE_Pos));
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return mco_frequency;
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}
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#if defined(RCC_BDCR_RTCSEL)
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/**
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* @brief Return RTC clock frequency
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* @retval RTC clock frequency (in Hz)
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* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
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* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
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*/
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uint32_t LL_RCC_GetRTCClockFreq(void)
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{
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uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* RTCCLK clock frequency */
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switch (LL_RCC_GetRTCClockSource())
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{
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#if defined(RCC_LSE_SUPPORT)
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case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */
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if (LL_RCC_LSE_IsReady() == 1U)
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{
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rtc_frequency = LSE_VALUE;
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}
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break;
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#endif
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case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */
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if (LL_RCC_LSI_IsReady() == 1U)
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{
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rtc_frequency = LSI_VALUE;
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}
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break;
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case LL_RCC_RTC_CLKSOURCE_HSE_DIV128: /* HSE/128 clock used as RTC clock source */
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if (LL_RCC_HSE_IsReady() == 1U)
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{
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rtc_frequency = HSE_VALUE / 128U;
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}
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break;
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case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */
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default:
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rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
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break;
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}
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return rtc_frequency;
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}
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#endif
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/**
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* @brief Return USB clock frequency
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* @retval USB clock frequency (in Hz)
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* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (PLL or HSI48) are not ready
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* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
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*/
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uint32_t LL_RCC_GetUSBClockFreq(void)
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{
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uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* RTCCLK clock frequency */
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switch (LL_RCC_GetUSBClockSource())
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{
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#if defined(RCC_PLL_SUPPORT)
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case LL_RCC_USB_CLKSOURCE_PLL: /* PLL used as USB clock source */
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if (LL_RCC_HSE_IsReady() == 1U)
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{
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switch (LL_RCC_GetUSBPrescaler())
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{
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case LL_RCC_USB_DIV_1P5:
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usb_frequency = RCC_PLL_GetFreqDomain_SYS() * 2U / 3U;
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break;
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case LL_RCC_USB_DIV_1:
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usb_frequency = RCC_PLL_GetFreqDomain_SYS();
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break;
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case LL_RCC_USB_DIV_2P5:
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usb_frequency = RCC_PLL_GetFreqDomain_SYS() * 2U / 5U;
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break;
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case LL_RCC_USB_DIV_2:
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usb_frequency = RCC_PLL_GetFreqDomain_SYS() / 2U;
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break;
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case LL_RCC_USB_DIV_3:
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usb_frequency = RCC_PLL_GetFreqDomain_SYS() / 3U;
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break;
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case LL_RCC_USB_DIV_3P5:
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usb_frequency = RCC_PLL_GetFreqDomain_SYS() * 2U / 7U;
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break;
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case LL_RCC_USB_DIV_4:
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usb_frequency = RCC_PLL_GetFreqDomain_SYS() / 4U;
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break;
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default:
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{
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break;
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}
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}
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}
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break;
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#endif
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case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
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usb_frequency = HSI48_VALUE;
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break;
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default:
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usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
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break;
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}
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return usb_frequency;
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}
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#if defined(CANFD)
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/**
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* @brief Return CANFD clock frequency
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* @retval CANFD clock frequency (in Hz)
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* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (PLL or HSE) are not ready
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* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
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*/
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uint32_t LL_RCC_GetCANFDClockFreq(void)
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{
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uint32_t canfd_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* CANFD clock frequency */
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switch (LL_RCC_GetCANFDClockSource())
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{
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case LL_RCC_CANFD_CLKSOURCE_HSE: /* HSE clock used as CANFD clock source */
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if (LL_RCC_HSE_IsReady() == 1U)
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{
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canfd_frequency = HSE_VALUE;
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}
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break;
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#if defined(RCC_PLL_SUPPORT)
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case LL_RCC_CANFD_CLKSOURCE_PLL: /* PLL used as CANFD clock source */
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if (LL_RCC_PLL_IsReady() == 1U)
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{
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canfd_frequency = RCC_PLL_GetFreqDomain_SYS();
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}
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break;
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case LL_RCC_CANFD_CLKSOURCE_PLL_DIV2: /* PLL/2 clock used as CANFD clock source */
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if (LL_RCC_PLL_IsReady() == 1U)
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{
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canfd_frequency = RCC_PLL_GetFreqDomain_SYS() / 2U;
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}
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break;
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case LL_RCC_CANFD_CLKSOURCE_PLL_DIV3: /* PLL/3 clock used as CANFD clock source */
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if (LL_RCC_PLL_IsReady() == 1U)
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{
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canfd_frequency = RCC_PLL_GetFreqDomain_SYS() / 3U;
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}
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break;
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case LL_RCC_CANFD_CLKSOURCE_PLL_DIV4: /* PLL/4 clock used as CANFD clock source */
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if (LL_RCC_PLL_IsReady() == 1U)
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{
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canfd_frequency = RCC_PLL_GetFreqDomain_SYS() / 4U;
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}
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break;
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case LL_RCC_CANFD_CLKSOURCE_PLL_DIV5: /* PLL/5 clock used as CANFD clock source */
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if (LL_RCC_PLL_IsReady() == 1U)
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{
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canfd_frequency = RCC_PLL_GetFreqDomain_SYS() / 5U;
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}
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break;
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case LL_RCC_CANFD_CLKSOURCE_PLL_DIV6: /* PLL/6 clock used as CANFD clock source */
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if (LL_RCC_PLL_IsReady() == 1U)
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{
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canfd_frequency = RCC_PLL_GetFreqDomain_SYS() / 6U;
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}
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break;
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case LL_RCC_CANFD_CLKSOURCE_PLL_DIV7: /* PLL/7 clock used as CANFD clock source */
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if (LL_RCC_PLL_IsReady() == 1U)
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{
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canfd_frequency = RCC_PLL_GetFreqDomain_SYS() / 7U;
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}
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break;
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case LL_RCC_CANFD_CLKSOURCE_PLL_DIV8: /* PLL/8 clock used as CANFD clock source */
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if (LL_RCC_PLL_IsReady() == 1U)
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{
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canfd_frequency = RCC_PLL_GetFreqDomain_SYS() / 8U;
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}
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break;
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#endif
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default:
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canfd_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
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break;
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}
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return canfd_frequency;
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}
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#endif /* CANFD */
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/**
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* @brief Return ADC clock frequency
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* @retval ADC clock frequency (in Hz)
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*/
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uint32_t LL_RCC_GetADCClockFreq(void)
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{
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uint32_t adc_frequency = 0U;
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/* ADCCLK clock frequency */
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switch (LL_RCC_GetADCClockSource())
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{
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case LL_RCC_ADC_CLKSOURCE_PCLK2_DIV4: /* PCLK/4 clock selected as ADC clock */
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adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) / 4;
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break;
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case LL_RCC_ADC_CLKSOURCE_PCLK2_DIV6: /* PCLK/6 clock selected as ADC clock */
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adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) / 6;
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break;
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case LL_RCC_ADC_CLKSOURCE_PCLK2_DIV8: /* PCLK/8 clock selected as ADC clock */
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adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) / 8;
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break;
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case LL_RCC_ADC_CLKSOURCE_PCLK2_DIV12: /* PCLK/12 clock selected as ADC clock */
|
|
adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) / 12;
|
|
break;
|
|
|
|
case LL_RCC_ADC_CLKSOURCE_PCLK2_DIV16: /* PCLK/16 clock selected as ADC clock */
|
|
adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) / 16;
|
|
break;
|
|
|
|
case LL_RCC_ADC_CLKSOURCE_PCLK2_DIV2: /* PCLK/2 clock selected as ADC clock */
|
|
default:
|
|
adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) / 2;
|
|
break;
|
|
}
|
|
return adc_frequency;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup RCC_LL_Private_Functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Return SYSTEM clock frequency
|
|
* @retval SYSTEM clock frequency (in Hz)
|
|
*/
|
|
uint32_t RCC_GetSystemClockFreq(void)
|
|
{
|
|
uint32_t frequency;
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (LL_RCC_GetSysClkSource())
|
|
{
|
|
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
|
|
frequency = HSE_VALUE;
|
|
break;
|
|
#if defined(RCC_PLL_SUPPORT)
|
|
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
|
|
frequency = RCC_PLL_GetFreqDomain_SYS();
|
|
break;
|
|
#endif
|
|
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default:
|
|
frequency = HSI_VALUE;
|
|
break;
|
|
}
|
|
|
|
return frequency;
|
|
}
|
|
|
|
/**
|
|
* @brief Return HCLK clock frequency
|
|
* @param SYSCLK_Frequency SYSCLK clock frequency
|
|
* @retval HCLK clock frequency (in Hz)
|
|
*/
|
|
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
|
|
{
|
|
/* HCLK clock frequency */
|
|
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
|
|
}
|
|
|
|
/**
|
|
* @brief Return PCLK1 clock frequency
|
|
* @param HCLK_Frequency HCLK clock frequency
|
|
* @retval PCLK1 clock frequency (in Hz)
|
|
*/
|
|
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
|
|
{
|
|
/* PCLK1 clock frequency */
|
|
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
|
|
}
|
|
|
|
/**
|
|
* @brief Return PCLK2 clock frequency
|
|
* @param HCLK_Frequency HCLK clock frequency
|
|
* @retval PCLK2 clock frequency (in Hz)
|
|
*/
|
|
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
|
|
{
|
|
/* PCLK2 clock frequency */
|
|
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
|
|
}
|
|
#if defined(RCC_PLL_SUPPORT)
|
|
/**
|
|
* @brief Return PLL clock frequency used for system domain
|
|
* @retval PLL clock frequency (in Hz)
|
|
*/
|
|
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
|
|
{
|
|
uint32_t pllinputfreq;
|
|
uint32_t pllsource;
|
|
|
|
pllsource = LL_RCC_PLL_GetMainSource();
|
|
|
|
switch (pllsource)
|
|
{
|
|
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllinputfreq = HSE_VALUE / ((LL_RCC_PLL_GetPrediv() >> RCC_CFGR_PLLXTPRE_Pos) + 1U);
|
|
break;
|
|
|
|
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
default:
|
|
pllinputfreq = HSI_VALUE;
|
|
break;
|
|
}
|
|
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMulFactor());
|
|
}
|
|
#endif
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* defined(RCC) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|
|
/************************ (C) COPYRIGHT Puya*****END OF FILE****/
|