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@ -1,11 +1,11 @@
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/******************************************************************************
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* @file gcc_arm.ld
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* @brief GNU Linker Script for Cortex-M based device
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* @version V2.0.0
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* @date 21. May 2019
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* @version V1.1.0
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* @date 04. August 2020
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -21,18 +21,86 @@
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "mem_ARMv81MML.h"
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__STACK_SIZE = 0x2000;
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__HEAP_SIZE = 0x50000;
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/*
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*-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
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*/
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/* memory regions are:
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secure ROM: 0x10000000
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non-secure ROM: 0x00000000
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secure RAM: 0x30000000
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non-secure RAM: 0x20000000
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*/
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/*---------------------- Flash Configuration ----------------------------------
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<h> Flash Configuration
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<o0> Flash Base Address <0x0-0xFFFFFFFF:8>
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<o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__ROM_BASE = 0x00000000;
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__ROM_SIZE = 0x00110000;
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/*--------------------- Embedded RAM Configuration ----------------------------
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<h> RAM Configuration
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<o0> RAM Base Address <0x0-0xFFFFFFFF:8>
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<o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__RAM_BASE = 0x20000000;
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__RAM_SIZE = 0x00100000;
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/*--------------------- Stack / Heap Configuration ----------------------------
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<h> Stack / Heap Configuration
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<o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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<o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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</h>
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-----------------------------------------------------------------------------*/
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__STACK_SIZE = 0x00002000;
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__HEAP_SIZE = 0x00050000;
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/*
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*-------------------- <<< end of configuration section >>> -------------------
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*/
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MEMORY
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{
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ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 512K
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DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
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DTCM2 (xrw) : ORIGIN = 0x20020000, LENGTH = 384K
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FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
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RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __copy_table_start__
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* __copy_table_end__
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* __zero_table_start__
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* __zero_table_end__
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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@ -62,7 +130,7 @@ SECTIONS
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*(.rodata*)
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KEEP(*(.eh_frame*))
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} > ITCM
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} > FLASH
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/*
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* SG veneers:
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@ -79,30 +147,32 @@ SECTIONS
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > ITCM
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > ITCM
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} > FLASH
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__exidx_end = .;
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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LONG ((__data_end__ - __data_start__) / 4)
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/* Add each additional data section here */
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/*
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LONG (__etext2)
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LONG (__data2_start__)
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LONG (__data2_end__ - __data2_start__)
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LONG ((__data2_end__ - __data2_start__) / 4)
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*/
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__copy_table_end__ = .;
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} > ITCM
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} > FLASH
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.zero.table :
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{
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@ -111,18 +181,19 @@ SECTIONS
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/* Add each additional bss section here */
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/*
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LONG (__bss2_start__)
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LONG (__bss2_end__ - __bss2_start__)
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LONG ((__bss2_end__ - __bss2_start__) / 4)
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*/
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__zero_table_end__ = .;
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} > DTCM
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} > FLASH
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/**
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* Location counter can end up 2byte aligned with narrow Thumb code but
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* __etext is assumed by startup code to be the LMA of a section in RAM
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* which must be 4byte aligned
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*/
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__etext = ALIGN (4);
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.data :
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.data : AT (__etext)
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{
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__data_start__ = .;
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*(vtable)
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@ -142,7 +213,6 @@ SECTIONS
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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@ -155,9 +225,7 @@ SECTIONS
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/* All data end */
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__data_end__ = .;
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} > ITCM AT > DTCM
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__etext = ADDR(.data);
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} > RAM
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/*
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* Secondary data section, optional
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@ -190,7 +258,7 @@ SECTIONS
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > DTCM2
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} > RAM AT > RAM
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/*
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* Secondary bss section, optional
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@ -219,21 +287,19 @@ SECTIONS
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. = . + __HEAP_SIZE;
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. = ALIGN(8);
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__HeapLimit = .;
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} > DTCM2
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} > RAM
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PROVIDE(__HeapBase = __end__);
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.stack (ORIGIN(DTCM2) + LENGTH(DTCM2) - __STACK_SIZE) (COPY) :
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.stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :
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{
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. = ALIGN(8);
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__StackLimit = .;
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. = . + __STACK_SIZE;
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. = ALIGN(8);
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__StackTop = .;
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} > DTCM2
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} > RAM
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PROVIDE(__stack = __StackTop);
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/* Check if data + heap + stack exceeds DTCM2 limit */
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ASSERT(__StackLimit >= __HeapLimit, "region DTCM2 overflowed with stack")
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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}
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Christophe Favergeon
5 years ago