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@ -63,8 +63,18 @@ static uint32_t startCycles=0;
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#if defined(CORTEXA) || defined(CORTEXR)
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#if !defined(__GNUC_PYTHON__)
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#include "cmsis_cp15.h"
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#else
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#if defined(__aarch64__)
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#include "timing_aarch64.h"
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#define AARCH64_TIMING
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#endif
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#endif
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#if defined(CORTEXA) && defined(AARCH64_TIMING)
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unsigned long long startCycles;
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#else
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unsigned int startCycles;
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#endif
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#define DO_RESET 1
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#define ENABLE_DIVIDER 0
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@ -84,9 +94,9 @@ void initCycleMeasurement()
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#endif
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#if defined(CORTEXA) || defined(CORTEXR)
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#if !defined(AARCH64_TIMING)
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// in general enable all counters (including cycle counter)
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#if !defined(__GNUC_PYTHON__)
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int32_t value = 1;
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@ -99,10 +109,8 @@ void initCycleMeasurement()
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if (ENABLE_DIVIDER)
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value |= 8; // enable "by 64" divider for CCNT.
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#endif
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//value |= 16;
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#if !defined(__GNUC_PYTHON__)
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// program the performance-counter control-register:
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__set_CP(15, 0, value, 9, 12, 0);
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@ -117,6 +125,8 @@ void initCycleMeasurement()
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value = value | (0x8000 << 12);
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__set_CP(15, 0, value, 14, 15, 7);
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#endif
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#else
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enable_timing();
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#endif
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#endif
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#endif
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@ -143,11 +153,15 @@ void cycleMeasurementStart()
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#endif
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#if (defined(CORTEXA) || defined(CORTEXR)) && !defined(__GNUC_PYTHON__)
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#if (defined(CORTEXA) || defined(CORTEXR))
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#if !defined(AARCH64_TIMING)
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unsigned int value;
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// Read CCNT Register
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__get_CP(15, 0, value, 9, 13, 0);
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startCycles = value;
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#else
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startCycles = readCCNT();
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#endif
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#endif
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#endif
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#endif
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@ -193,14 +207,18 @@ return(0);
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#endif
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#endif
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#if (defined(CORTEXA) || defined(CORTEXR)) && !defined(__GNUC_PYTHON__)
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#if (defined(CORTEXA) || defined(CORTEXR))
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#if !defined(AARCH64_TIMING)
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unsigned int value;
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// Read CCNT Register
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__get_CP(15, 0, value, 9, 13, 0);
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return(value - startCycles);
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#else
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unsigned long long value;
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value = readCCNT();
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return((Testing::cycles_t)(value - startCycles));
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#endif
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#endif
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#endif
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#if defined(__GNUC_PYTHON__)
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return(0);
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#endif
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}
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